CMX
CMX firmware code in-line documentation
 All Classes Namespaces Files Functions Variables
CMX_top_Base.vhd
Go to the documentation of this file.
1 ----------------------------------------------------------------------------------
7 ----------------------------------------------------------------------------------
8 library IEEE;
9 use IEEE.STD_LOGIC_1164.ALL;
10 use IEEE.NUMERIC_STD.ALL;
11 
12 library UNISIM;
13 use UNISIM.VComponents.all;
14 
15 library work;
16 use work.CMXpackage.all;
17 use work.CMX_VME_defs.all;
18 use work.CMX_local_package.all;
19 use work.CMX_flavor_package.all;
20 
21 
22 
23 entity CMX_top_Base is
24  port (
25 
26  ----------------------------------------------------------------------------
27  -- VME-- backplane (65 signals)
28  ----------------------------------------------------------------------------
29  --GEOADDR0: in std_logic; -- GeoAddr0
30  OCB_GEO_ADRS_0: in std_logic;
31  --VMEADDR: in std_logic_vector(23 downto 1); -- Address bus
32  OCB_A01: in std_logic;
33  OCB_A02: in std_logic;
34  OCB_A03: in std_logic;
35  OCB_A04: in std_logic;
36  OCB_A05: in std_logic;
37  OCB_A06: in std_logic;
38  OCB_A07: in std_logic;
39  OCB_A08: in std_logic;
40  OCB_A09: in std_logic;
41  OCB_A10: in std_logic;
42  OCB_A11: in std_logic;
43  OCB_A12: in std_logic;
44  OCB_A13: in std_logic;
45  OCB_A14: in std_logic;
46  OCB_A15: in std_logic;
47  OCB_A16: in std_logic;
48  OCB_A17: in std_logic;
49  OCB_A18: in std_logic;
50  OCB_A19: in std_logic;
51  OCB_A20: in std_logic;
52  OCB_A21: in std_logic;
53  OCB_A22: in std_logic;
54  OCB_A23: in std_logic;
55  --VMEDS_L: in std_logic; -- DS strobe VMEDS_L
56  OCB_DS_B: in std_logic;
57  --VMEWR_L: in std_logic; -- VME Write VMEWR_L
58  OCB_WRITE_B: in std_logic;
59  --VMERST_L: in std_logic; -- System reset VMERST_L
60  OCB_SYS_RESET_B: in std_logic;
61  --VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA
62  OCB_D: inout std_logic_vector(15 downto 0);
63  ----------------------------------------------------------------------------
64  --system monitor
65  BF_SYSMON_01_P : in STD_LOGIC; -- Auxiliary Channel 1
66  BF_SYSMON_01_N : in STD_LOGIC;
67  BF_SYSMON_03_P : in STD_LOGIC; -- Auxiliary Channel 3
68  BF_SYSMON_03_N : in STD_LOGIC;
69  BF_SYSMON_04_P : in STD_LOGIC; -- Auxiliary Channel 4
70  BF_SYSMON_04_N : in STD_LOGIC;
71  BF_SYSMON_07_P : in STD_LOGIC; -- Auxiliary Channel 7
72  BF_SYSMON_07_N : in STD_LOGIC;
73  BF_SYSMON_08_P : in STD_LOGIC; -- Auxiliary Channel 8
74  BF_SYSMON_08_N : in STD_LOGIC;
75  BF_SYSMON_09_P : in STD_LOGIC; -- Auxiliary Channel 9
76  BF_SYSMON_09_N : in STD_LOGIC;
77  BF_SYSMON_10_P : in STD_LOGIC; -- Auxiliary Channel 10
78  BF_SYSMON_10_N : in STD_LOGIC;
79  BF_SYSMON_11_P : in STD_LOGIC; -- Auxiliary Channel 11
80  BF_SYSMON_11_N : in STD_LOGIC;
81  BF_SYSMON_12_P : in STD_LOGIC; -- Auxiliary Channel 12
82  BF_SYSMON_12_N : in STD_LOGIC;
83  BF_SYSMON_13_P : in STD_LOGIC; -- Auxiliary Channel 13
84  BF_SYSMON_13_N : in STD_LOGIC;
85  BF_SYSMON_14_P : in STD_LOGIC; -- Auxiliary Channel 14
86  BF_SYSMON_14_N : in STD_LOGIC;
87  BF_SYSMON_15_P : in STD_LOGIC; -- Auxiliary Channel 15
88  BF_SYSMON_15_N : in STD_LOGIC;
89 
90  P0_0 : in std_logic;
91  P0_1 : in std_logic;
92  P0_2 : in std_logic;
93  P0_3 : in std_logic;
94  P0_4 : in std_logic;
95  P0_5 : in std_logic;
96  P0_6 : in std_logic;
97  P0_7 : in std_logic;
98  P0_8 : in std_logic;
99  P0_9 : in std_logic;
100  P0_10 : in std_logic;
101  P0_11 : in std_logic;
102  P0_12 : in std_logic;
103  P0_13 : in std_logic;
104  P0_14 : in std_logic;
105  P0_15 : in std_logic;
106  P0_16 : in std_logic;
107  P0_17 : in std_logic;
108  P0_18 : in std_logic;
109  P0_19 : in std_logic;
110  P0_20 : in std_logic;
111  P0_21 : in std_logic;
112  P0_22 : in std_logic;
113  P0_23 : in std_logic;
114  P0_24 : in std_logic;
115  P1_0 : in std_logic;
116  P1_1 : in std_logic;
117  P1_2 : in std_logic;
118  P1_3 : in std_logic;
119  P1_4 : in std_logic;
120  P1_5 : in std_logic;
121  P1_6 : in std_logic;
122  P1_7 : in std_logic;
123  P1_8 : in std_logic;
124  P1_9 : in std_logic;
125  P1_10 : in std_logic;
126  P1_11 : in std_logic;
127  P1_12 : in std_logic;
128  P1_13 : in std_logic;
129  P1_14 : in std_logic;
130  P1_15 : in std_logic;
131  P1_16 : in std_logic;
132  P1_17 : in std_logic;
133  P1_18 : in std_logic;
134  P1_19 : in std_logic;
135  P1_20 : in std_logic;
136  P1_21 : in std_logic;
137  P1_22 : in std_logic;
138  P1_23 : in std_logic;
139  P1_24 : in std_logic;
140  P2_0 : in std_logic;
141  P2_1 : in std_logic;
142  P2_2 : in std_logic;
143  P2_3 : in std_logic;
144  P2_4 : in std_logic;
145  P2_5 : in std_logic;
146  P2_6 : in std_logic;
147  P2_7 : in std_logic;
148  P2_8 : in std_logic;
149  P2_9 : in std_logic;
150  P2_10 : in std_logic;
151  P2_11 : in std_logic;
152  P2_12 : in std_logic;
153  P2_13 : in std_logic;
154  P2_14 : in std_logic;
155  P2_15 : in std_logic;
156  P2_16 : in std_logic;
157  P2_17 : in std_logic;
158  P2_18 : in std_logic;
159  P2_19 : in std_logic;
160  P2_20 : in std_logic;
161  P2_21 : in std_logic;
162  P2_22 : in std_logic;
163  P2_23 : in std_logic;
164  P2_24 : in std_logic;
165  P3_0 : in std_logic;
166  P3_1 : in std_logic;
167  P3_2 : in std_logic;
168  P3_3 : in std_logic;
169  P3_4 : in std_logic;
170  P3_5 : in std_logic;
171  P3_6 : in std_logic;
172  P3_7 : in std_logic;
173  P3_8 : in std_logic;
174  P3_9 : in std_logic;
175  P3_10 : in std_logic;
176  P3_11 : in std_logic;
177  P3_12 : in std_logic;
178  P3_13 : in std_logic;
179  P3_14 : in std_logic;
180  P3_15 : in std_logic;
181  P3_16 : in std_logic;
182  P3_17 : in std_logic;
183  P3_18 : in std_logic;
184  P3_19 : in std_logic;
185  P3_20 : in std_logic;
186  P3_21 : in std_logic;
187  P3_22 : in std_logic;
188  P3_23 : in std_logic;
189  P3_24 : in std_logic;
190  P4_0 : in std_logic;
191  P4_1 : in std_logic;
192  P4_2 : in std_logic;
193  P4_3 : in std_logic;
194  P4_4 : in std_logic;
195  P4_5 : in std_logic;
196  P4_6 : in std_logic;
197  P4_7 : in std_logic;
198  P4_8 : in std_logic;
199  P4_9 : in std_logic;
200  P4_10 : in std_logic;
201  P4_11 : in std_logic;
202  P4_12 : in std_logic;
203  P4_13 : in std_logic;
204  P4_14 : in std_logic;
205  P4_15 : in std_logic;
206  P4_16 : in std_logic;
207  P4_17 : in std_logic;
208  P4_18 : in std_logic;
209  P4_19 : in std_logic;
210  P4_20 : in std_logic;
211  P4_21 : in std_logic;
212  P4_22 : in std_logic;
213  P4_23 : in std_logic;
214  P4_24 : in std_logic;
215  P5_0 : in std_logic;
216  P5_1 : in std_logic;
217  P5_2 : in std_logic;
218  P5_3 : in std_logic;
219  P5_4 : in std_logic;
220  P5_5 : in std_logic;
221  P5_6 : in std_logic;
222  P5_7 : in std_logic;
223  P5_8 : in std_logic;
224  P5_9 : in std_logic;
225  P5_10 : in std_logic;
226  P5_11 : in std_logic;
227  P5_12 : in std_logic;
228  P5_13 : in std_logic;
229  P5_14 : in std_logic;
230  P5_15 : in std_logic;
231  P5_16 : in std_logic;
232  P5_17 : in std_logic;
233  P5_18 : in std_logic;
234  P5_19 : in std_logic;
235  P5_20 : in std_logic;
236  P5_21 : in std_logic;
237  P5_22 : in std_logic;
238  P5_23 : in std_logic;
239  P5_24 : in std_logic;
240  P6_0 : in std_logic;
241  P6_1 : in std_logic;
242  P6_2 : in std_logic;
243  P6_3 : in std_logic;
244  P6_4 : in std_logic;
245  P6_5 : in std_logic;
246  P6_6 : in std_logic;
247  P6_7 : in std_logic;
248  P6_8 : in std_logic;
249  P6_9 : in std_logic;
250  P6_10 : in std_logic;
251  P6_11 : in std_logic;
252  P6_12 : in std_logic;
253  P6_13 : in std_logic;
254  P6_14 : in std_logic;
255  P6_15 : in std_logic;
256  P6_16 : in std_logic;
257  P6_17 : in std_logic;
258  P6_18 : in std_logic;
259  P6_19 : in std_logic;
260  P6_20 : in std_logic;
261  P6_21 : in std_logic;
262  P6_22 : in std_logic;
263  P6_23 : in std_logic;
264  P6_24 : in std_logic;
265  P7_0 : in std_logic;
266  P7_1 : in std_logic;
267  P7_2 : in std_logic;
268  P7_3 : in std_logic;
269  P7_4 : in std_logic;
270  P7_5 : in std_logic;
271  P7_6 : in std_logic;
272  P7_7 : in std_logic;
273  P7_8 : in std_logic;
274  P7_9 : in std_logic;
275  P7_10 : in std_logic;
276  P7_11 : in std_logic;
277  P7_12 : in std_logic;
278  P7_13 : in std_logic;
279  P7_14 : in std_logic;
280  P7_15 : in std_logic;
281  P7_16 : in std_logic;
282  P7_17 : in std_logic;
283  P7_18 : in std_logic;
284  P7_19 : in std_logic;
285  P7_20 : in std_logic;
286  P7_21 : in std_logic;
287  P7_22 : in std_logic;
288  P7_23 : in std_logic;
289  P7_24 : in std_logic;
290  P8_0 : in std_logic;
291  P8_1 : in std_logic;
292  P8_2 : in std_logic;
293  P8_3 : in std_logic;
294  P8_4 : in std_logic;
295  P8_5 : in std_logic;
296  P8_6 : in std_logic;
297  P8_7 : in std_logic;
298  P8_8 : in std_logic;
299  P8_9 : in std_logic;
300  P8_10 : in std_logic;
301  P8_11 : in std_logic;
302  P8_12 : in std_logic;
303  P8_13 : in std_logic;
304  P8_14 : in std_logic;
305  P8_15 : in std_logic;
306  P8_16 : in std_logic;
307  P8_17 : in std_logic;
308  P8_18 : in std_logic;
309  P8_19 : in std_logic;
310  P8_20 : in std_logic;
311  P8_21 : in std_logic;
312  P8_22 : in std_logic;
313  P8_23 : in std_logic;
314  P8_24 : in std_logic;
315  P9_0 : in std_logic;
316  P9_1 : in std_logic;
317  P9_2 : in std_logic;
318  P9_3 : in std_logic;
319  P9_4 : in std_logic;
320  P9_5 : in std_logic;
321  P9_6 : in std_logic;
322  P9_7 : in std_logic;
323  P9_8 : in std_logic;
324  P9_9 : in std_logic;
325  P9_10 : in std_logic;
326  P9_11 : in std_logic;
327  P9_12 : in std_logic;
328  P9_13 : in std_logic;
329  P9_14 : in std_logic;
330  P9_15 : in std_logic;
331  P9_16 : in std_logic;
332  P9_17 : in std_logic;
333  P9_18 : in std_logic;
334  P9_19 : in std_logic;
335  P9_20 : in std_logic;
336  P9_21 : in std_logic;
337  P9_22 : in std_logic;
338  P9_23 : in std_logic;
339  P9_24 : in std_logic;
340  P10_0 : in std_logic;
341  P10_1 : in std_logic;
342  P10_2 : in std_logic;
343  P10_3 : in std_logic;
344  P10_4 : in std_logic;
345  P10_5 : in std_logic;
346  P10_6 : in std_logic;
347  P10_7 : in std_logic;
348  P10_8 : in std_logic;
349  P10_9 : in std_logic;
350  P10_10 : in std_logic;
351  P10_11 : in std_logic;
352  P10_12 : in std_logic;
353  P10_13 : in std_logic;
354  P10_14 : in std_logic;
355  P10_15 : in std_logic;
356  P10_16 : in std_logic;
357  P10_17 : in std_logic;
358  P10_18 : in std_logic;
359  P10_19 : in std_logic;
360  P10_20 : in std_logic;
361  P10_21 : in std_logic;
362  P10_22 : in std_logic;
363  P10_23 : in std_logic;
364  P10_24 : in std_logic;
365  P11_0 : in std_logic;
366  P11_1 : in std_logic;
367  P11_2 : in std_logic;
368  P11_3 : in std_logic;
369  P11_4 : in std_logic;
370  P11_5 : in std_logic;
371  P11_6 : in std_logic;
372  P11_7 : in std_logic;
373  P11_8 : in std_logic;
374  P11_9 : in std_logic;
375  P11_10 : in std_logic;
376  P11_11 : in std_logic;
377  P11_12 : in std_logic;
378  P11_13 : in std_logic;
379  P11_14 : in std_logic;
380  P11_15 : in std_logic;
381  P11_16 : in std_logic;
382  P11_17 : in std_logic;
383  P11_18 : in std_logic;
384  P11_19 : in std_logic;
385  P11_20 : in std_logic;
386  P11_21 : in std_logic;
387  P11_22 : in std_logic;
388  P11_23 : in std_logic;
389  P11_24 : in std_logic;
390  P12_0 : in std_logic;
391  P12_1 : in std_logic;
392  P12_2 : in std_logic;
393  P12_3 : in std_logic;
394  P12_4 : in std_logic;
395  P12_5 : in std_logic;
396  P12_6 : in std_logic;
397  P12_7 : in std_logic;
398  P12_8 : in std_logic;
399  P12_9 : in std_logic;
400  P12_10 : in std_logic;
401  P12_11 : in std_logic;
402  P12_12 : in std_logic;
403  P12_13 : in std_logic;
404  P12_14 : in std_logic;
405  P12_15 : in std_logic;
406  P12_16 : in std_logic;
407  P12_17 : in std_logic;
408  P12_18 : in std_logic;
409  P12_19 : in std_logic;
410  P12_20 : in std_logic;
411  P12_21 : in std_logic;
412  P12_22 : in std_logic;
413  P12_23 : in std_logic;
414  P12_24 : in std_logic;
415  P13_0 : in std_logic;
416  P13_1 : in std_logic;
417  P13_2 : in std_logic;
418  P13_3 : in std_logic;
419  P13_4 : in std_logic;
420  P13_5 : in std_logic;
421  P13_6 : in std_logic;
422  P13_7 : in std_logic;
423  P13_8 : in std_logic;
424  P13_9 : in std_logic;
425  P13_10 : in std_logic;
426  P13_11 : in std_logic;
427  P13_12 : in std_logic;
428  P13_13 : in std_logic;
429  P13_14 : in std_logic;
430  P13_15 : in std_logic;
431  P13_16 : in std_logic;
432  P13_17 : in std_logic;
433  P13_18 : in std_logic;
434  P13_19 : in std_logic;
435  P13_20 : in std_logic;
436  P13_21 : in std_logic;
437  P13_22 : in std_logic;
438  P13_23 : in std_logic;
439  P13_24 : in std_logic;
440  P14_0 : in std_logic;
441  P14_1 : in std_logic;
442  P14_2 : in std_logic;
443  P14_3 : in std_logic;
444  P14_4 : in std_logic;
445  P14_5 : in std_logic;
446  P14_6 : in std_logic;
447  P14_7 : in std_logic;
448  P14_8 : in std_logic;
449  P14_9 : in std_logic;
450  P14_10 : in std_logic;
451  P14_11 : in std_logic;
452  P14_12 : in std_logic;
453  P14_13 : in std_logic;
454  P14_14 : in std_logic;
455  P14_15 : in std_logic;
456  P14_16 : in std_logic;
457  P14_17 : in std_logic;
458  P14_18 : in std_logic;
459  P14_19 : in std_logic;
460  P14_20 : in std_logic;
461  P14_21 : in std_logic;
462  P14_22 : in std_logic;
463  P14_23 : in std_logic;
464  P14_24 : in std_logic;
465  P15_0 : in std_logic;
466  P15_1 : in std_logic;
467  P15_2 : in std_logic;
468  P15_3 : in std_logic;
469  P15_4 : in std_logic;
470  P15_5 : in std_logic;
471  P15_6 : in std_logic;
472  P15_7 : in std_logic;
473  P15_8 : in std_logic;
474  P15_9 : in std_logic;
475  P15_10 : in std_logic;
476  P15_11 : in std_logic;
477  P15_12 : in std_logic;
478  P15_13 : in std_logic;
479  P15_14 : in std_logic;
480  P15_15 : in std_logic;
481  P15_16 : in std_logic;
482  P15_17 : in std_logic;
483  P15_18 : in std_logic;
484  P15_19 : in std_logic;
485  P15_20 : in std_logic;
486  P15_21 : in std_logic;
487  P15_22 : in std_logic;
488  P15_23 : in std_logic;
489  P15_24 : in std_logic;
490 
491 
492  --CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
493  --CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
494 
495  CLK_40MHz08_DSKW_1_BF_LOGIC_DIR : in std_logic;
496  CLK_40MHz08_DSKW_1_BF_LOGIC_CMP : in std_logic;
497 
498  CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
499  CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
500 
501 
502  --CLK_320MHz64_LHC_BF_LOGIC_DIR : in std_logic;
503  --CLK_320MHz64_LHC_BF_LOGIC_CMP : in std_logic;
504 
505  BF_DEBUG_0 : out std_logic;
506  BF_DEBUG_1 : out std_logic;
507  BF_DEBUG_2 : out std_logic;
508  BF_DEBUG_3 : out std_logic;
509  BF_DEBUG_4 : out std_logic;
510  BF_DEBUG_5 : out std_logic;
511  BF_DEBUG_6 : out std_logic;
512  BF_DEBUG_7 : out std_logic;
513  BF_DEBUG_8 : out std_logic;
514  BF_DEBUG_9 : out std_logic;
515 
516 
517  BF_REQ_CTP_1_INPUT : out std_logic;
518  BF_REQ_CTP_2_INPUT : out std_logic;
519  BF_REQ_CABLE_1_INPUT: out std_logic;
520  BF_REQ_CABLE_2_INPUT: out std_logic;
521  BF_REQ_CABLE_3_INPUT: out std_logic;
522  BF_LED_REQ_0 : out std_logic;
523  BF_LED_REQ_1 : out std_logic;
524  BF_LED_REQ_2 : out std_logic;
525  BF_LED_REQ_3 : out std_logic;
526  BF_LED_REQ_4 : out std_logic;
527  BF_TO_FROM_BSPT_0 : in std_logic;
528  BF_TO_FROM_BSPT_1 : in std_logic;
529  BF_TO_FROM_BSPT_2 : out std_logic;
530  BF_TO_FROM_BSPT_3 : out std_logic;
531  BF_TO_FROM_BSPT_4 : out std_logic;
532  BF_TO_FROM_BSPT_5 : out std_logic;
533  BF_TO_FROM_BSPT_6 : out std_logic;
534  BF_TO_FROM_BSPT_7 : out std_logic;
535 
536 
537  BF_DOUT_CTP_00 : out std_logic;
538  BF_DOUT_CTP_01 : out std_logic;
539  BF_DOUT_CTP_02 : out std_logic;
540  BF_DOUT_CTP_03 : out std_logic;
541  BF_DOUT_CTP_04 : out std_logic;
542  BF_DOUT_CTP_05 : out std_logic;
543  BF_DOUT_CTP_06 : out std_logic;
544  BF_DOUT_CTP_07 : out std_logic;
545  BF_DOUT_CTP_08 : out std_logic;
546  BF_DOUT_CTP_09 : out std_logic;
547  BF_DOUT_CTP_10 : out std_logic;
548  BF_DOUT_CTP_11 : out std_logic;
549  BF_DOUT_CTP_12 : out std_logic;
550  BF_DOUT_CTP_13 : out std_logic;
551  BF_DOUT_CTP_14 : out std_logic;
552  BF_DOUT_CTP_15 : out std_logic;
553  BF_DOUT_CTP_16 : out std_logic;
554  BF_DOUT_CTP_17 : out std_logic;
555  BF_DOUT_CTP_18 : out std_logic;
556  BF_DOUT_CTP_19 : out std_logic;
557  BF_DOUT_CTP_20 : out std_logic;
558  BF_DOUT_CTP_21 : out std_logic;
559  BF_DOUT_CTP_22 : out std_logic;
560  BF_DOUT_CTP_23 : out std_logic;
561  BF_DOUT_CTP_24 : out std_logic;
562  BF_DOUT_CTP_25 : out std_logic;
563  BF_DOUT_CTP_26 : out std_logic;
564  BF_DOUT_CTP_27 : out std_logic;
565  BF_DOUT_CTP_28 : out std_logic;
566  BF_DOUT_CTP_29 : out std_logic;
567  BF_DOUT_CTP_30 : out std_logic;
568  BF_DOUT_CTP_31 : out std_logic;
569  BF_DOUT_CTP_64 : out std_logic;
570 
571  BF_DOUT_CTP_32 : out std_logic;
572  BF_DOUT_CTP_33 : out std_logic;
573  BF_DOUT_CTP_34 : out std_logic;
574  BF_DOUT_CTP_35 : out std_logic;
575  BF_DOUT_CTP_36 : out std_logic;
576  BF_DOUT_CTP_37 : out std_logic;
577  BF_DOUT_CTP_38 : out std_logic;
578  BF_DOUT_CTP_39 : out std_logic;
579  BF_DOUT_CTP_40 : out std_logic;
580  BF_DOUT_CTP_41 : out std_logic;
581  BF_DOUT_CTP_42 : out std_logic;
582  BF_DOUT_CTP_43 : out std_logic;
583  BF_DOUT_CTP_44 : out std_logic;
584  BF_DOUT_CTP_45 : out std_logic;
585  BF_DOUT_CTP_46 : out std_logic;
586  BF_DOUT_CTP_47 : out std_logic;
587  BF_DOUT_CTP_48 : out std_logic;
588  BF_DOUT_CTP_49 : out std_logic;
589  BF_DOUT_CTP_50 : out std_logic;
590  BF_DOUT_CTP_51 : out std_logic;
591  BF_DOUT_CTP_52 : out std_logic;
592  BF_DOUT_CTP_53 : out std_logic;
593  BF_DOUT_CTP_54 : out std_logic;
594  BF_DOUT_CTP_55 : out std_logic;
595  BF_DOUT_CTP_56 : out std_logic;
596  BF_DOUT_CTP_57 : out std_logic;
597  BF_DOUT_CTP_58 : out std_logic;
598  BF_DOUT_CTP_59 : out std_logic;
599  BF_DOUT_CTP_60 : out std_logic;
600  BF_DOUT_CTP_61 : out std_logic;
601  BF_DOUT_CTP_62 : out std_logic;
602  BF_DOUT_CTP_63 : out std_logic;
603  BF_DOUT_CTP_65 : out std_logic;
604 
605  D_CBL_00_B : out std_logic;
606  D_CBL_01_B : out std_logic;
607  D_CBL_02_B : out std_logic;
608  D_CBL_03_B : out std_logic;
609  D_CBL_04_B : out std_logic;
610  D_CBL_05_B : out std_logic;
611  D_CBL_06_B : out std_logic;
612  D_CBL_07_B : out std_logic;
613  D_CBL_08_B : out std_logic;
614  D_CBL_09_B : out std_logic;
615  D_CBL_10_B : out std_logic;
616  D_CBL_11_B : out std_logic;
617  D_CBL_12_B : out std_logic;
618  D_CBL_13_B : out std_logic;
619  D_CBL_14_B : out std_logic;
620  D_CBL_15_B : out std_logic;
621  D_CBL_16_B : out std_logic;
622  D_CBL_17_B : out std_logic;
623  D_CBL_18_B : out std_logic;
624  D_CBL_19_B : out std_logic;
625  D_CBL_20_B : out std_logic;
626  D_CBL_21_B : out std_logic;
627  D_CBL_22_B : out std_logic;
628  D_CBL_23_B : out std_logic;
629  D_CBL_24_B : out std_logic;
630  D_CBL_25_B : out std_logic;
631  D_CBL_26_B : out std_logic;
632  D_CBL_81_B : out std_logic;
633 
634  D_CBL_27_B : out std_logic;
635  D_CBL_28_B : out std_logic;
636  D_CBL_29_B : out std_logic;
637  D_CBL_30_B : out std_logic;
638  D_CBL_31_B : out std_logic;
639  D_CBL_32_B : out std_logic;
640  D_CBL_33_B : out std_logic;
641  D_CBL_34_B : out std_logic;
642  D_CBL_35_B : out std_logic;
643  D_CBL_36_B : out std_logic;
644  D_CBL_37_B : out std_logic;
645  D_CBL_38_B : out std_logic;
646  D_CBL_39_B : out std_logic;
647  D_CBL_40_B : out std_logic;
648  D_CBL_41_B : out std_logic;
649  D_CBL_42_B : out std_logic;
650  D_CBL_43_B : out std_logic;
651  D_CBL_44_B : out std_logic;
652  D_CBL_45_B : out std_logic;
653  D_CBL_46_B : out std_logic;
654  D_CBL_47_B : out std_logic;
655  D_CBL_48_B : out std_logic;
656  D_CBL_49_B : out std_logic;
657  D_CBL_50_B : out std_logic;
658  D_CBL_51_B : out std_logic;
659  D_CBL_52_B : out std_logic;
660  D_CBL_53_B : out std_logic;
661  D_CBL_82_B : out std_logic;
662 
663  D_CBL_54_B : out std_logic;
664  D_CBL_55_B : out std_logic;
665  D_CBL_56_B : out std_logic;
666  D_CBL_57_B : out std_logic;
667  D_CBL_58_B : out std_logic;
668  D_CBL_59_B : out std_logic;
669  D_CBL_60_B : out std_logic;
670  D_CBL_61_B : out std_logic;
671  D_CBL_62_B : out std_logic;
672  D_CBL_63_B : out std_logic;
673  D_CBL_64_B : out std_logic;
674  D_CBL_65_B : out std_logic;
675  D_CBL_66_B : out std_logic;
676  D_CBL_67_B : out std_logic;
677  D_CBL_68_B : out std_logic;
678  D_CBL_69_B : out std_logic;
679  D_CBL_70_B : out std_logic;
680  D_CBL_71_B : out std_logic;
681  D_CBL_72_B : out std_logic;
682  D_CBL_73_B : out std_logic;
683  D_CBL_74_B : out std_logic;
684  D_CBL_75_B : out std_logic;
685  D_CBL_76_B : out std_logic;
686  D_CBL_77_B : out std_logic;
687  D_CBL_78_B : out std_logic;
688  D_CBL_79_B : out std_logic;
689  D_CBL_80_B : out std_logic;
690  D_CBL_83_B : out std_logic;
691 
692  BF_TO_TP_DAQ_SLINK_RETURN_DIR : in std_logic;
693  BF_TO_TP_DAQ_SLINK_RETURN_CMP : in std_logic;
694  BF_TO_TP_ROI_SLINK_RETURN_DIR : in std_logic;
695  BF_TO_TP_ROI_SLINK_RETURN_CMP : in std_logic;
696 
697  BUF_TTC_L1_ACCEPT : in std_logic;
698  BUF_TTC_BNCH_CNT_RES : in std_logic;
699 
700  -- sfp
701  CLK_120MHz000_XTAL_1_BF_TRNCV_DIR: in std_logic;
702  CLK_120MHz000_XTAL_1_BF_TRNCV_CMP: in std_logic;
703  BF_DAQ_DATA_OUT_DIR : out std_logic;
704  BF_DAQ_DATA_OUT_CMP : out std_logic;
705  BF_ROI_DATA_OUT_DIR : out std_logic;
706  BF_ROI_DATA_OUT_CMP : out std_logic;
707 
708  MP1_F01_QUAD_110_TRN_0_DIR : out std_logic;
709  MP1_F01_QUAD_110_TRN_0_CMP : out std_logic;
710  MP1_F03_QUAD_110_TRN_1_DIR : out std_logic;
711  MP1_F03_QUAD_110_TRN_1_CMP : out std_logic;
712  MP1_F07_QUAD_110_TRN_2_DIR : out std_logic;
713  MP1_F07_QUAD_110_TRN_2_CMP : out std_logic;
714  MP1_F05_QUAD_110_TRN_3_DIR : out std_logic;
715  MP1_F05_QUAD_110_TRN_3_CMP : out std_logic;
716  MP1_F09_QUAD_111_TRN_0_DIR : out std_logic;
717  MP1_F09_QUAD_111_TRN_0_CMP : out std_logic;
718  MP1_F11_QUAD_111_TRN_1_DIR : out std_logic;
719  MP1_F11_QUAD_111_TRN_1_CMP : out std_logic;
720  MP1_F10_QUAD_111_TRN_2_DIR : out std_logic;
721  MP1_F10_QUAD_111_TRN_2_CMP : out std_logic;
722  MP1_F08_QUAD_111_TRN_3_DIR : out std_logic;
723  MP1_F08_QUAD_111_TRN_3_CMP : out std_logic;
724  MP1_F04_QUAD_112_TRN_0_DIR : out std_logic;
725  MP1_F04_QUAD_112_TRN_0_CMP : out std_logic;
726  MP1_F06_QUAD_112_TRN_1_DIR : out std_logic;
727  MP1_F06_QUAD_112_TRN_1_CMP : out std_logic;
728  MP1_F02_QUAD_112_TRN_2_DIR : out std_logic;
729  MP1_F02_QUAD_112_TRN_2_CMP : out std_logic;
730  MP1_F00_QUAD_112_TRN_3_DIR : out std_logic;
731  MP1_F00_QUAD_112_TRN_3_CMP : out std_logic;
732  MP2_F01_QUAD_113_TRN_0_DIR : out std_logic;
733  MP2_F01_QUAD_113_TRN_0_CMP : out std_logic;
734  MP2_F03_QUAD_113_TRN_1_DIR : out std_logic;
735  MP2_F03_QUAD_113_TRN_1_CMP : out std_logic;
736  MP2_F07_QUAD_113_TRN_2_DIR : out std_logic;
737  MP2_F07_QUAD_113_TRN_2_CMP : out std_logic;
738  MP2_F05_QUAD_113_TRN_3_DIR : out std_logic;
739  MP2_F05_QUAD_113_TRN_3_CMP : out std_logic;
740  MP2_F09_QUAD_114_TRN_0_DIR : out std_logic;
741  MP2_F09_QUAD_114_TRN_0_CMP : out std_logic;
742  MP2_F11_QUAD_114_TRN_1_DIR : out std_logic;
743  MP2_F11_QUAD_114_TRN_1_CMP : out std_logic;
744  MP2_F10_QUAD_114_TRN_2_DIR : out std_logic;
745  MP2_F10_QUAD_114_TRN_2_CMP : out std_logic;
746  MP2_F08_QUAD_114_TRN_3_DIR : out std_logic;
747  MP2_F08_QUAD_114_TRN_3_CMP : out std_logic;
748  MP2_F04_QUAD_115_TRN_0_DIR : out std_logic;
749  MP2_F04_QUAD_115_TRN_0_CMP : out std_logic;
750  MP2_F06_QUAD_115_TRN_1_DIR : out std_logic;
751  MP2_F06_QUAD_115_TRN_1_CMP : out std_logic;
752  MP2_F02_QUAD_115_TRN_2_DIR : out std_logic;
753  MP2_F02_QUAD_115_TRN_2_CMP : out std_logic;
754  MP2_F00_QUAD_115_TRN_3_DIR : out std_logic;
755  MP2_F00_QUAD_115_TRN_3_CMP : out std_logic;
756  CLK_320MHz64_LHC_BF_QUAD_111_DIR : in std_logic;
757  CLK_320MHz64_LHC_BF_QUAD_111_CMP : in std_logic;
758  CLK_320MHz64_LHC_BF_QUAD_114_DIR : in std_logic;
759  CLK_320MHz64_LHC_BF_QUAD_114_CMP : in std_logic;
760  --clk40 : in std_logic;
761  RXN_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
762  RXP_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0)
763 
764 
765  );
766 
767 
768 end CMX_top_Base;
769 
770 architecture Behavioral of CMX_top_Base is
771 
772  attribute keep : string; -- keep signals in synthesis
773  attribute IOB : string;
774 
775 
776  ------------------------------------------------------------------------------
777  -- VME interface component used in BSPT FPGA (Ian's vme_interface)
778  ------------------------------------------------------------------------------
779  component CMX_BASE_VME_BSPT is
780  port (
781  clk40 : IN std_logic; -- 40MHz Clk
782  geoadd_0 : IN std_logic; -- GeoAddr0
783  n_ds0_int : IN std_logic; -- DS strobe
784  n_write : IN std_logic; -- VME Write
785  vme_address : IN std_logic_vector (23 DOWNTO 1); -- Address bus
786  board_ds : OUT std_logic; -- Board ds
787  brdsel_n : OUT std_logic -- Board select
788  );
789  end component;
790  -- signals for CMX_BASE_VME_INTERFACE component
791  signal ds: std_logic; -- board_ds output from VME (Ian model)
792  signal ncs: std_logic; -- brdsel_n output from VME (Ian model)
793 
794  signal vme_address : std_logic_vector(23 downto 1);
795 
796  component vme_outreg
797  generic (
798  ia_vme : integer;
799  width : integer);
800  port (
801  clk : in std_logic;
802  addr_vme : in std_logic_vector (15 downto 0);
803  ncs : in std_logic;
804  rd_nwr : in std_logic;
805  ds : in std_logic;
806  data_to_vme : in std_logic_vector (width-1 downto 0);
807  read_detect : out std_logic;
808  data_vme : out std_logic_vector (15 downto 0));
809  end component;
810 
811  signal read_detect_outreg_test : std_logic;
812  signal data_to_vme_outreg_test : std_logic_vector (15 downto 0);
813 
814 
815  component vme_inreg
816  generic (
817  ia_vme : integer;
818  width : integer);
819  port (
820  clk : in std_logic;
821  ncs : in std_logic;
822  rd_nwr : in std_logic;
823  ds : in std_logic;
824  data_from_vme : out std_logic_vector (width-1 downto 0);
825  data_to_vme : in std_logic_vector (width-1 downto 0);
826  addr_vme : in std_logic_vector (15 downto 0);
827  read_detect : out std_logic;
828  write_detect : out std_logic;
829  data_vme : inout std_logic_vector (15 downto 0));
830  end component;
831 
832  component vme_inreg_async is
833  generic (
834  ia_vme : integer;
835  width : integer);
836  port (
837  ncs : in std_logic;
838  rd_nwr : in std_logic;
839  ds : in std_logic;
840  addr_vme : in std_logic_vector (15 downto 0);
841  data_vme : inout std_logic_vector (15 downto 0);
842  data_from_vme : out std_logic_vector (width-1 downto 0);
843  data_to_vme : in std_logic_vector (width-1 downto 0));
844  end component vme_inreg_async;
845 
846  component vme_local_switch is
847  port (
848  data_vme_up : out std_logic_vector (15 downto 0);
849  data_vme_from_below : in arr_16;
850  bus_drive_up : out std_logic;
851  bus_drive_from_below : in std_logic_vector);
852  end component vme_local_switch;
853 
854  component vme_main_hub is
855  port (
856  data_vme : inout std_logic_vector(15 downto 0);
857  data_vme_from_below : in std_logic_vector (15 downto 0);
858  bus_drive_from_below : in std_logic;
859  data_vme_going_below : out std_logic_vector(15 downto 0));
860  end component vme_main_hub;
861 
862  signal data_vme_from_below_top : arr_16(1762 downto 0);
863  signal bus_drive_from_below_top : std_logic_vector(1762 downto 0);
864  signal bus_drive_up_top : std_logic;
865  signal data_vme_up_top : std_logic_vector(15 downto 0);
866  signal data_vme_going_below : std_logic_vector(15 downto 0);
867 
868  component vme_inreg_notri_async is
869  generic (
870  ia_vme : integer;
871  width : integer);
872  port (
873  ncs : in std_logic;
874  rd_nwr : in std_logic;
875  ds : in std_logic;
876  addr_vme : in std_logic_vector (15 downto 0);
877  data_vme_in : in std_logic_vector (15 downto 0);
878  data_vme_out : out std_logic_vector (15 downto 0);
879  bus_drive : out std_logic;
880  data_from_vme : out std_logic_vector (width-1 downto 0);
881  data_to_vme : in std_logic_vector (width-1 downto 0));
882  end component vme_inreg_notri_async;
883 
884  component vme_outreg_notri_async is
885  generic (
886  ia_vme : integer;
887  width : integer);
888  port (
889  ncs : in std_logic;
890  rd_nwr : in std_logic;
891  ds : in std_logic;
892  addr_vme : in std_logic_vector (15 downto 0);
893  data_vme : out std_logic_vector (15 downto 0);
894  bus_drive : out std_logic;
895  data_to_vme : in std_logic_vector (width-1 downto 0));
896  end component vme_outreg_notri_async;
897 
898  component vme_inreg_notri is
899  generic (
900  ia_vme : integer;
901  width : integer);
902  port (
903  clk : in std_logic;
904  ncs : in std_logic;
905  rd_nwr : in std_logic;
906  ds : in std_logic;
907  addr_vme : in std_logic_vector (15 downto 0);
908  data_vme_in : in std_logic_vector (15 downto 0);
909  data_vme_out : out std_logic_vector (15 downto 0);
910  bus_drive : out std_logic;
911  data_from_vme : out std_logic_vector (width-1 downto 0);
912  data_to_vme : in std_logic_vector (width-1 downto 0);
913  read_detect : out std_logic;
914  write_detect : out std_logic);
915  end component vme_inreg_notri;
916 
917  component vme_outreg_notri is
918  generic (
919  ia_vme : integer;
920  width : integer);
921  port (
922  clk : in std_logic;
923  ncs : in std_logic;
924  rd_nwr : in std_logic;
925  ds : in std_logic;
926  addr_vme : in std_logic_vector (15 downto 0);
927  data_vme : out std_logic_vector (15 downto 0);
928  bus_drive : out std_logic;
929  data_to_vme : in std_logic_vector (width-1 downto 0);
930  read_detect : out std_logic);
931  end component vme_outreg_notri;
932 
933  signal data_from_vme_test_rw : std_logic_vector (15 downto 0);
934  signal data_to_vme_test_rw : std_logic_vector (15 downto 0);
935  signal read_detect_inreg_test : std_logic;
936  signal write_detect_inreg_test : std_logic;
937  signal test_rw_counter : unsigned(15 downto 0);
938  signal data_to_vme_test_r : std_logic_vector (15 downto 0);
939 
940  signal start_playback, start_playback_r1: std_logic; --r1 is the the
941  --BF_TO_FROM_BSPT_0
942  --registered once
943  -- the first variable is
944  -- yet one more register
945  -- (so synchroniser)
946 
947  component CMX_version is
948  port (
949  clk40 : in std_logic;
950  ncs : in std_logic;
951  rd_nwr : in std_logic;
952  ds : in std_logic;
953  addr_vme : in std_logic_vector (15 downto 0);
954  data_vme_out : out std_logic_vector (15 downto 0);
955  bus_drive : out std_logic);
956  end component CMX_version;
957 
958  component sys_monitor is
959  generic (
960  ADDR_REG_RO_SYSMON_DATA_BLOCK : integer);
961  port (
962  clk : in std_logic;
963  BF_SYSMON_01_P : in STD_LOGIC;
964  BF_SYSMON_01_N : in STD_LOGIC;
965  BF_SYSMON_03_P : in STD_LOGIC;
966  BF_SYSMON_03_N : in STD_LOGIC;
967  BF_SYSMON_04_P : in STD_LOGIC;
968  BF_SYSMON_04_N : in STD_LOGIC;
969  BF_SYSMON_07_P : in STD_LOGIC;
970  BF_SYSMON_07_N : in STD_LOGIC;
971  BF_SYSMON_08_P : in STD_LOGIC;
972  BF_SYSMON_08_N : in STD_LOGIC;
973  BF_SYSMON_09_P : in STD_LOGIC;
974  BF_SYSMON_09_N : in STD_LOGIC;
975  BF_SYSMON_10_P : in STD_LOGIC;
976  BF_SYSMON_10_N : in STD_LOGIC;
977  BF_SYSMON_11_P : in STD_LOGIC;
978  BF_SYSMON_11_N : in STD_LOGIC;
979  BF_SYSMON_12_P : in STD_LOGIC;
980  BF_SYSMON_12_N : in STD_LOGIC;
981  BF_SYSMON_13_P : in STD_LOGIC;
982  BF_SYSMON_13_N : in STD_LOGIC;
983  BF_SYSMON_14_P : in STD_LOGIC;
984  BF_SYSMON_14_N : in STD_LOGIC;
985  BF_SYSMON_15_P : in STD_LOGIC;
986  BF_SYSMON_15_N : in STD_LOGIC;
987  ncs : in std_logic;
988  rd_nwr : in std_logic;
989  ds : in std_logic;
990  addr_vme : in std_logic_vector (15 downto 0);
991  data_vme_in : in std_logic_vector (15 downto 0);
992  data_vme_out : out std_logic_vector (15 downto 0);
993  bus_drive : out std_logic);
994  end component sys_monitor;
995 
996 
997  component CMX_input_module
998  port (
999  P : in mat_var (numactchan-1 downto 0);
1000  buf_clk40 : in std_logic;
1001  buf_clk40_m180o : in std_logic;
1002  buf_clk200 : in std_logic;
1003  pll_locked : in std_logic;
1004  ODATA : out arr_4Xword (numactchan-1 downto 0);
1005  ODATA_first_half : out arr_2Xword(numactchan -1 downto 0);
1006  PAR_ERROR_total : out std_logic;--_vector(numactchan-1 downto 0);
1007  counter_enable_out : out std_logic_vector(numactchan-1 downto 0);
1008  counter_values : out std_logic_vector(numactchan-1 downto 0);
1009  del_register : in del_register_type;
1010  upload_delays : in std_logic;
1011  quiet : in std_logic;
1012  start_playback : in std_logic;
1013  spy_write_inhibit : in std_logic;
1014  ncs : in std_logic;
1015  rd_nwr : in std_logic;
1016  ds : in std_logic;
1017  addr_vme : in std_logic_vector (15 downto 0);
1018  data_vme_in : in std_logic_vector (15 downto 0);
1019  data_vme_out : out std_logic_vector (15 downto 0);
1020  bus_drive : out std_logic
1021  );
1022  end component;
1023 
1024  signal counter_values : std_logic_vector(numactchan-1 downto 0);
1025  signal del_register : del_register_type;
1026  signal upload_delays : std_logic;
1027 
1028  --signal PAR_ERROR: std_logic_vector(numactchan-1 downto 0);
1029 
1030  signal quiet : std_logic;
1031  signal force : std_logic;
1032 
1033  signal data_from_vme_REG_RW_QUIET_FORCE : std_logic_vector(15 downto 0);
1034  signal data_to_vme_REG_RW_QUIET_FORCE : std_logic_vector(15 downto 0);
1035 
1036  signal DATA96 : arr_4Xword (numactchan-1 downto 0); --96 bit data at 40MHz
1037  signal ODATA_first_half : arr_2Xword(numactchan-1 downto 0);
1038 
1039  signal P : mat_var (numactchan-1 downto 0);
1040 
1041  signal BF_DEBUG : std_logic_vector(9 downto 0);
1042 
1043  signal counter_enable_inputmod_sig: std_logic_vector(numactchan-1 downto 0);
1044 
1045 
1046  component CMX_Memory_spy_inhibit is
1047  port (
1048  spy_write_inhibit : out std_logic;
1049  buf_clk40 : in std_logic;
1050  ncs : in std_logic;
1051  rd_nwr : in std_logic;
1052  ds : in std_logic;
1053  addr_vme : in std_logic_vector (15 downto 0);
1054  data_vme_in : in std_logic_vector (15 downto 0);
1055  data_vme_out : out std_logic_vector (15 downto 0);
1056  bus_drive : out std_logic);
1057  end component CMX_Memory_spy_inhibit;
1058 
1059  signal spy_write_inhibit : std_logic;
1060 
1061  -- VME signal definitions
1062  signal data_from_vme_REG_RW_MISS_E_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1063  signal data_to_vme_REG_RW_MISS_E_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1064 
1065  signal data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1066  signal data_to_vme_REG_RW_MISS_E_RES_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1067 
1068  signal data_from_vme_REG_RW_SUM_ET_THR_BLOCK : arr_16(num_thresholds-1 downto 0);
1069  signal data_to_vme_REG_RW_SUM_ET_THR_BLOCK : arr_16(num_thresholds-1 downto 0);
1070 
1071  signal data_from_vme_REG_RW_SUM_ET_RES_THR_BLOCK : arr_16(num_thresholds-1 downto 0);
1072  signal data_to_vme_REG_RW_SUM_ET_RES_THR_BLOCK : arr_16(num_thresholds-1 downto 0);
1073 
1074  signal data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1075  signal data_to_vme_REG_RW_XS_T2_A2_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1076 
1077  signal data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1078  signal data_to_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1079 
1080  signal data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1081  signal data_to_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1082 
1083  signal data_from_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1084  signal data_to_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1085 
1086  signal data_from_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1087  signal data_to_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1088 
1089  signal data_from_vme_REG_RW_XS_B2_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1090  signal data_to_vme_REG_RW_XS_B2_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1091 
1092 
1093 
1094  component CMX_Sum_Et is
1095  port (
1096  CLK : in std_logic;
1097  ENERGY_REMOTE : in std_logic_vector(26*4-1 downto 0);
1098  CTP_CABLE_0 : out std_logic_vector(23 downto 0);
1099  CTP_CABLE_1 : out std_logic_vector(23 downto 0);
1100  -- thresholds
1101  MISS_E_THR : in arr_ctr_31bit(num_thresholds-1 downto 0);
1102  MISS_E_RES_THR : in arr_ctr_31bit(num_thresholds-1 downto 0);
1103  SUM_ET_THR : in arr_ctr_15bit(num_thresholds-1 downto 0);
1104  SUM_ET_RES_THR : in arr_ctr_15bit(num_thresholds-1 downto 0);
1105  XS_T2_A2 : in arr_ctr_31bit(num_thresholds-1 downto 0);
1106  -- parameters
1107  T_MISS_E_MIN : in arr_ctr_31bit(num_thresholds-1 downto 0);
1108  T_MISS_E_MAX : in arr_ctr_31bit(num_thresholds-1 downto 0);
1109  T_SUM_E_MIN : in arr_ctr_15bit(num_thresholds-1 downto 0);
1110  T_SUM_E_MAX : in arr_ctr_15bit(num_thresholds-1 downto 0);
1111  XS_B2 : in arr_ctr_15bit(num_thresholds-1 downto 0);
1112  ov_all_out : out std_logic_vector(5 downto 0);
1113  sums_all_out : out arr_ctr_15bit(5 downto 0);
1114  BACKPLANE_DATA_IN : in energy_array;
1115  LOCAL_CABLE_OUT : out std_logic_vector(4*26-1 downto 0);
1116  BCID_in : in std_logic_vector(11 downto 0);
1117  BCID_delayed : out std_logic_vector(11 downto 0);
1118  -- counter signals
1119  counter_reset : in T_SL;
1120  counter_inhibit : in T_SL;
1121  par_err : in std_logic_vector(1 downto 0); -- parity error (input module - 0, RTM - 1)
1122  force : in T_SL; -- force
1123  ncs : in std_logic; --ports forwarded to the vme register instances
1124  rd_nwr : in std_logic;
1125  ds : in std_logic;
1126  addr_vme : in std_logic_vector (15 downto 0);
1127  data_vme_in : in std_logic_vector (15 downto 0);
1128  data_vme_out : out std_logic_vector (15 downto 0);
1129  bus_drive : out std_logic
1130  );
1131  end component CMX_Sum_Et;
1132 
1133  signal par_err : std_logic_vector(1 downto 0);
1134 
1135  signal ENERGY_REMOTE : std_logic_vector(26*4-1 downto 0); --just dummy
1136 
1137  -- thresholds
1138  signal MISS_E_THR : arr_ctr_31bit(num_thresholds-1 downto 0);
1139  signal MISS_E_RES_THR : arr_ctr_31bit(num_thresholds-1 downto 0);
1140  signal SUM_ET_THR : arr_ctr_15bit(num_thresholds-1 downto 0);
1141  signal SUM_ET_RES_THR : arr_ctr_15bit(num_thresholds-1 downto 0);
1142  signal XS_T2_A2 : arr_ctr_31bit(num_thresholds-1 downto 0);
1143  -- parameters
1144  signal T_MISS_E_MIN : arr_ctr_31bit(num_thresholds-1 downto 0);
1145  signal T_MISS_E_MAX : arr_ctr_31bit(num_thresholds-1 downto 0);
1146  signal T_SUM_E_MIN : arr_ctr_15bit(num_thresholds-1 downto 0);
1147  signal T_SUM_E_MAX : arr_ctr_15bit(num_thresholds-1 downto 0);
1148  signal XS_B2 : arr_ctr_15bit(num_thresholds-1 downto 0);
1149 
1150  -- thresholds
1151  signal slv_MISS_E_THR : arr_31(num_thresholds-1 downto 0);
1152  signal slv_MISS_E_RES_THR : arr_31(num_thresholds-1 downto 0);
1153  signal slv_SUM_ET_THR : arr_15(num_thresholds-1 downto 0);
1154  signal slv_SUM_ET_RES_THR : arr_15(num_thresholds-1 downto 0);
1155  signal slv_XS_T2_A2 : arr_31(num_thresholds-1 downto 0);
1156  -- parameters
1157  signal slv_T_MISS_E_MIN : arr_31(num_thresholds-1 downto 0);
1158  signal slv_T_MISS_E_MAX : arr_31(num_thresholds-1 downto 0);
1159  signal slv_T_SUM_E_MIN : arr_15(num_thresholds-1 downto 0);
1160  signal slv_T_SUM_E_MAX : arr_15(num_thresholds-1 downto 0);
1161  signal slv_XS_B2 : arr_15(num_thresholds-1 downto 0);
1162 
1163 
1164 
1165  signal LOCAL_CABLE_OUT : std_logic_vector(26*4-1 downto 0);
1166  signal BACKPLANE_DATA_IN : energy_array;
1167 
1168  signal data_to_RTM1 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1169  signal data_to_RTM2 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1170 
1171 -- signal p_d : nx121_array(numactchan-1 downto 0); --120 bits + parity -
1172 -- --will be connected to
1173 -- --the decoder output
1174 -- --threshold mask 25
1175 -- --threshold times 4
1176 -- --TOBs + 5 bits position/TOB
1177 
1178  --component CMX_cable_clocked_80Mbps_output_module
1179  -- generic (
1180  -- numbits_in_cable_connector : integer);
1181  -- port (
1182  -- data : in std_logic_vector((numbits_in_cable_connector*2)-1 downto 0);
1183  -- ddr_data_out : out std_logic_vector(numbits_in_cable_connector downto 0);
1184  -- buf_clk40 : in std_logic;
1185  -- buf_clk40_center : in std_logic;
1186  -- buf_clk200 : in std_logic;
1187  -- pll_locked : in std_logic;
1188  -- del_array : in cable_del_array_type(numbits_in_cable_connector downto 0);
1189  -- upload_delays : in std_logic);
1190  --end component;
1191 
1192  component CMX_crate_cable_output_module is
1193  port (
1194  data : in std_logic_vector(numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1195  ddr_data_out : out arr_RTM(num_RTM_cables-1 downto 0);
1196  buf_clk40 : in std_logic;
1197  buf_clk40_center : in std_logic;
1198  pll_locked : in std_logic;
1199  start_playback : in std_logic;
1200  spy_write_inhibit : in std_logic;
1201  ncs : in std_logic;
1202  rd_nwr : in std_logic;
1203  ds : in std_logic;
1204  addr_vme : in std_logic_vector (15 downto 0);
1205  data_vme_in : in std_logic_vector (15 downto 0);
1206  data_vme_out : out std_logic_vector (15 downto 0);
1207  bus_drive : out std_logic);
1208  end component CMX_crate_cable_output_module;
1209 
1210  signal data_to_RTM : std_logic_vector( numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1211  signal ddr_data_out_RTM : arr_RTM(num_RTM_cables-1 downto 0);
1212 
1213  --signal sdr_data_out_CTP1 : std_logic_vector(31 downto 0);
1214  --signal sdr_data_out_CTP2 : std_logic_vector(31 downto 0);
1215  --signal sdr_data_out : std_logic_vector(31 downto 0);
1216 
1217  signal ddr_data_out_RTM1 : std_logic_vector(numbits_in_RTM_connector downto 0);
1218  signal ddr_data_out_RTM2 : std_logic_vector(numbits_in_RTM_connector downto 0);
1219  --signal del_array_RTM : cable_del_array_type(numbits_in_RTM_connector downto 0);
1220 
1221  --signal ddr_data_in_RTM1 : std_logic_vector(numbits_in_RTM_connector downto 0);
1222  --signal ddr_data_in_RTM2 : std_logic_vector(numbits_in_RTM_connector downto 0);
1223  --signal sig_arr_RTM: arr_RTM(num_RTM_cables-1 downto 0);
1224  --signal data_from_RTM : std_logic_vector(numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1225 
1226 
1227 
1228 
1229  --signal forwarded_clock_CTP2 : std_logic;
1230  --signal data_CTP2 : std_logic_vector((numbits_in_CTP_connector*2)-1 downto 0);
1231  --signal parity_CTP2 : std_logic;
1232  --signal ddr_data_in_CTP2 : std_logic_vector(numbits_in_CTP_connector downto 0);
1233  --
1234  --signal forwarded_clock_RTM3 : std_logic;
1235  --signal data_RTM3 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1236  --signal parity_RTM3 : std_logic;
1237  --signal ddr_data_in_RTM3 : std_logic_vector(numbits_in_RTM_connector downto 0);
1238 
1239  component BCID_counter
1240  port (
1241  reset : in std_logic;
1242  clk_40 : in std_logic;
1243  BCID_out : out std_logic_vector(11 downto 0);
1244  --VME control:
1245  ncs : in std_logic; --ports forwarded to the vme register instances
1246  rd_nwr : in std_logic;
1247  ds : in std_logic;
1248  addr_vme : in std_logic_vector (15 downto 0);
1249  data_vme_in : in std_logic_vector (15 downto 0);
1250  data_vme_out : out std_logic_vector (15 downto 0);
1251  bus_drive : out std_logic);
1252  end component;
1253  signal BCID_counter_sig : std_logic_vector(11 downto 0);
1254  signal BCID_delayed_decoder : std_logic_vector(11 downto 0);
1255  signal BCID_delayed_daq : std_logic_vector(11 downto 0);
1256 
1257 
1258  component Topo_Data_TX is
1259  port (
1260  MGTREFCLK_PAD_N_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1261  MGTREFCLK_PAD_P_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1262  GTXTXRESET_IN : in std_logic;
1263  GTXRXRESET_IN : in std_logic;
1264  GTX_TX_READY_OUT : out std_logic;
1265  GTX_RX_READY_OUT : out std_logic;
1266  RXN_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1267  RXP_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1268  TXN_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1269  TXP_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1270  clk40 : in std_logic;
1271  clk320 : in std_logic;
1272  pll_locked : in std_logic;
1273  send_align : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1274  BCID : in std_logic_vector(11 downto 0);
1275  indata : in std_logic_vector(TX_indata_length-1 downto 0);
1276  ext_trigger : in std_logic;
1277  ncs : in std_logic;
1278  rd_nwr : in std_logic;
1279  ds : in std_logic;
1280  addr_vme : in std_logic_vector (15 downto 0);
1281  data_vme_in : in std_logic_vector (15 downto 0);
1282  data_vme_out : out std_logic_vector (15 downto 0);
1283  bus_drive : out std_logic);
1284  end component Topo_Data_TX;
1285 
1286  component CMX_SumET_Topo_Encoder is
1287  port (
1288  local_data : in std_logic_vector(4*26-1 downto 0);
1289  send_align_out : out std_logic_vector(num_GTX_groups*num_GTX_per_group - 1 downto 0);
1290  Data_out : out std_logic_vector(TX_indata_length - 1 downto 0);
1291  bcid_in : in std_logic_vector(11 downto 0);
1292  bcid_adj : out std_logic_vector(11 downto 0);
1293  clk :in std_logic);
1294  end component CMX_SumET_Topo_Encoder;
1295 
1296  signal bcid_adj : std_logic_vector(11 downto 0);
1297 
1298  signal TXN_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1299  signal TXP_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1300 
1301  signal MGTREFCLK_PAD_N_IN : std_logic_vector(num_GTX_groups-1 downto 0);
1302  signal MGTREFCLK_PAD_P_IN : std_logic_vector(num_GTX_groups-1 downto 0);
1303 
1304  signal GTX_RX_READY_OUT : std_logic;
1305  signal GTX_TX_READY_OUT : std_logic;
1306 
1307 
1308  signal GTXTXRESET_IN : std_logic;
1309  signal GTXRXRESET_IN : std_logic;
1310 
1311  signal send_align : std_logic_vector(23 downto 0);
1312 
1313  signal indata_Topo_TX : std_logic_vector(TX_indata_length-1 downto 0);
1314 
1315  signal data_to_vme_REG_RW_TOPOTR_GTX_RESET : std_logic_vector(15 downto 0);
1316  signal data_from_vme_REG_RW_TOPOTR_GTX_RESET : std_logic_vector(15 downto 0);
1317 
1318  signal data_to_vme_REG_RO_TOPOTR_GTX_STATUS : std_logic_vector(15 downto 0);
1319 
1320  signal data_from_vme_REG_RW_DAQ_ROI_RESET : std_logic_vector(15 downto 0);
1321  signal data_to_vme_REG_RW_DAQ_ROI_RESET : std_logic_vector(15 downto 0);
1322 
1323  signal data_to_vme_REG_RO_DAQ_ROI_STATUS : std_logic_vector(15 downto 0);
1324 
1325  signal data_from_vme_REG_RW_DAQ_ROI_GTX_RESET: std_logic_vector(15 downto 0);
1326  signal data_to_vme_REG_RW_DAQ_ROI_GTX_RESET: std_logic_vector(15 downto 0);
1327  signal gtx_reset_SFP_DAQ, gtx_reset_SFP_ROI : std_logic;
1328 
1329  signal BUF_TTC_L1_ACCEPT_r: std_logic;
1330  signal l1a_synced: std_logic;
1331 
1332 
1333  signal bc_reset_synced : std_logic;
1334  signal BUF_TTC_BNCH_CNT_RES_r : std_logic;
1335 
1336  component CMX_rate_counter_inhibit is
1337  port (
1338  counter_inhibit : out std_logic;
1339  counter_reset : out std_logic;
1340  buf_clk40 : in std_logic;
1341  ncs : in std_logic;
1342  rd_nwr : in std_logic;
1343  ds : in std_logic;
1344  addr_vme : in std_logic_vector (15 downto 0);
1345  data_vme_in : in std_logic_vector (15 downto 0);
1346  data_vme_out : out std_logic_vector (15 downto 0);
1347  bus_drive : out std_logic);
1348  end component CMX_rate_counter_inhibit;
1349 
1350  signal counter_inhibit : std_logic;
1351  signal counter_reset : std_logic;
1352 
1353  --component chipscope_ila_CMX_top_inputmodclk
1354  -- port (
1355  -- CONTROL : inout std_logic_vector(35 downto 0);
1356  -- CLK : in std_logic;
1357  -- DATA : in std_logic_vector(2375 downto 0);
1358  -- TRIG0 : in std_logic_vector(35 downto 0));
1359  --end component;
1360  --
1361  --signal DATA_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(2375 downto 0);
1362  --signal TRIG0_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(35 downto 0);
1363  --signal TRIG_forward_inputmodclk_outputmodclk : std_logic_vector(0 downto 0);
1364 
1365  --component chipscope_ila_IDELAY
1366  -- port (
1367  -- CONTROL : inout std_logic_vector(35 downto 0);
1368  -- CLK : in std_logic;
1369  -- DATA : in std_logic_vector(2000 downto 0);
1370  -- TRIG0 : in std_logic_vector(0 to 0));
1371  --end component;
1372 
1373  --signal DATA_chipscope_ila_IDELAY : std_logic_vector(2000 downto 0);
1374 
1375 
1376  --component chipscope_ila_CTP2
1377  -- port (
1378  -- CONTROL : inout std_logic_vector(35 downto 0);
1379  -- CLK : in std_logic;
1380  -- DATA : in std_logic_vector(64 downto 0);
1381  -- TRIG0 : in std_logic_vector(0 to 0));
1382  --end component;
1383  --
1384  --component chipscope_ila_RTM
1385  -- port (
1386  -- CONTROL : inout std_logic_vector(35 downto 0);
1387  -- CLK : in std_logic;
1388  -- DATA : in std_logic_vector(52 downto 0);
1389  -- TRIG0 : in std_logic_vector(0 to 0));
1390  --end component;
1391 
1392  --component chipscope_ila_LVDS_TX_CTP_RTM
1393  -- port (
1394  -- CONTROL : inout std_logic_vector(35 downto 0);
1395  -- CLK : in std_logic;
1396  -- DATA : in std_logic_vector(117 downto 0);
1397  -- TRIG0 : in std_logic_vector(1 downto 0));
1398  --end component;
1399 
1400  component CMX_clock_manager is
1401  port (
1402  I_DS1 : in std_logic;
1403  IB_DS1 : in std_logic;
1404  buf_clk40 : out std_logic;
1405  buf_clk40_90o : out std_logic;
1406  buf_clk40_m180o : out std_logic;
1407  buf_clk40_m90o : out std_logic;
1408  buf_clk320 : out std_logic;
1409  buf_clk160 : out std_logic;
1410  buf_clk200 : out std_logic;
1411  pll_locked : out std_logic;
1412  I_DS2 : in std_logic;
1413  IB_DS2 : in std_logic;
1414  buf_clk40_ds2 : out std_logic;
1415  pll_locked_ds2 : out std_logic;
1416  ncs : in std_logic;
1417  rd_nwr : in std_logic;
1418  ds : in std_logic;
1419  addr_vme : in std_logic_vector (15 downto 0);
1420  data_vme_in : in std_logic_vector (15 downto 0);
1421  data_vme_out : out std_logic_vector (15 downto 0);
1422  bus_drive : out std_logic);
1423  end component CMX_clock_manager;
1424 
1425 
1426  signal buf_clk40 : std_logic;
1427  signal buf_clk40_m180o : std_logic;
1428  signal buf_clk40_center : std_logic;
1429  signal buf_clk320 : std_logic;
1430  signal buf_clk160 : std_logic;
1431  signal buf_clk200 : std_logic;
1432  signal pll_locked : std_logic;
1433 
1434  signal buf_clk40_ds2 : std_logic;
1435  signal pll_locked_ds2 : std_logic;
1436 
1437  component CMX_delay_generator
1438  generic (
1439  start_address : integer);
1440  port (
1441  clk40 : in std_logic;
1442  ncs : in std_logic;
1443  rd_nwr : in std_logic;
1444  ds : in std_logic;
1445  addr_vme : in std_logic_vector (15 downto 0);
1446  data_vme_in : in std_logic_vector (15 downto 0);
1447  data_vme_out : out std_logic_vector (15 downto 0);
1448  bus_drive : out std_logic;
1449  del_register : out del_register_type;
1450  upload_delays : out std_logic);
1451  end component;
1452 
1453 
1454 
1455 
1456  component SFP_Data_TXRX
1457  generic (
1458  direction : std_logic;
1459  clock_source : std_logic);
1460  port (
1461  MGTREFCLK : in std_logic;
1462  gtx_reset : in std_logic;
1463  local_pll_lock_out: out std_logic;
1464  GTX_TX_READY_OUT : out std_logic;
1465  GTX_RX_READY_OUT : out std_logic;
1466  PLLLKDET_diag : out std_logic;
1467  local_gtx_reset_diag : out std_logic;
1468  local_mmcm_reset_diag : out std_logic;
1469  GTXTEST_diag : out std_logic;
1470  RXN_IN : in std_logic;
1471  RXP_IN : in std_logic;
1472  TXN_OUT : out std_logic;
1473  TXP_OUT : out std_logic;
1474  clk40_out : out std_logic;
1475  clk120_out : out std_logic;
1476  clk40_in : in std_logic;
1477  clk120_in : in std_logic;
1478  indata : in std_logic_vector(7 downto 0);
1479  odata : out std_logic_vector(7 downto 0);
1480  TXPREEMPHASIS_IN : in std_logic_vector(3 downto 0);
1481  TXPOSTEMPHASIS_IN : in std_logic_vector(4 downto 0);
1482  TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
1483  RXEQMIX_IN : in std_logic_vector(2 downto 0);
1484  DFECLKDLYADJ : in std_logic_vector(5 downto 0);
1485  DFECLKDLYADJMON : out std_logic_vector(5 downto 0);
1486  DFEDLYOVRD : in std_logic;
1487  DFEEYEDACMON : out std_logic_vector(4 downto 0);
1488  DFESENSCAL : out std_logic_vector(2 downto 0);
1489  DFETAP1 : in std_logic_vector(4 downto 0);
1490  DFETAP1MONITOR : out std_logic_vector(4 downto 0);
1491  DFETAP2 : in std_logic_vector(4 downto 0);
1492  DFETAP2MONITOR : out std_logic_vector(4 downto 0);
1493  DFETAP3 : in std_logic_vector(3 downto 0);
1494  DFETAP3MONITOR : out std_logic_vector(3 downto 0);
1495  DFETAP4 : in std_logic_vector(3 downto 0);
1496  DFETAP4MONITOR : out std_logic_vector(3 downto 0);
1497  DFETAPOVRD : in std_logic);
1498  end component;
1499 
1500  signal MGTREFCLK_Q118 : std_logic;
1501 
1502  signal GTXTXRESET_IN_TX_SFP_DAQ : std_logic;
1503  signal GTXRXRESET_IN_TX_SFP_DAQ : std_logic;
1504  signal local_pll_lock_out_SFP_DAQ : std_logic;
1505  signal GTX_TX_READY_OUT_TX_SFP_DAQ : std_logic;
1506  signal GTX_RX_READY_OUT_TX_SFP_DAQ : std_logic;
1507  signal PLLLKDET_diag_TX_SFP_DAQ : std_logic;
1508  signal local_gtx_reset_diag_TX_SFP_DAQ : std_logic;
1509  signal local_mmcm_reset_diag_TX_SFP_DAQ : std_logic;
1510  signal GTXTEST_diag_TX_SFP_DAQ : std_logic;
1511  signal RXN_IN_TX_SFP_DAQ : std_logic;
1512  signal RXP_IN_TX_SFP_DAQ : std_logic;
1513  signal TXN_OUT_TX_SFP_DAQ : std_logic;
1514  signal TXP_OUT_TX_SFP_DAQ : std_logic;
1515  signal clk40_out_TX_SFP_DAQ : std_logic;
1516  signal clk120_out_TX_SFP_DAQ : std_logic;
1517  signal clk40_in_TX_SFP_DAQ : std_logic;
1518  signal clk120_in_TX_SFP_DAQ : std_logic;
1519  signal indata_TX_SFP_DAQ : std_logic_vector(7 downto 0);
1520  signal odata_TX_SFP_DAQ : std_logic_vector(7 downto 0);
1521  signal TXPREEMPHASIS_IN_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1522  signal TXPOSTEMPHASIS_IN_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1523  signal TXDIFFCTRL_IN_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1524  signal RXEQMIX_IN_TX_SFP_DAQ : std_logic_vector(2 downto 0);
1525  signal DFECLKDLYADJ_TX_SFP_DAQ : std_logic_vector(5 downto 0);
1526  signal DFECLKDLYADJMON_TX_SFP_DAQ : std_logic_vector(5 downto 0);
1527  signal DFEDLYOVRD_TX_SFP_DAQ : std_logic;
1528  signal DFEEYEDACMON_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1529  signal DFESENSCAL_TX_SFP_DAQ : std_logic_vector(2 downto 0);
1530  signal DFETAP1_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1531  signal DFETAP1MONITOR_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1532  signal DFETAP2_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1533  signal DFETAP2MONITOR_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1534  signal DFETAP3_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1535  signal DFETAP3MONITOR_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1536  signal DFETAP4_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1537  signal DFETAP4MONITOR_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1538  signal DFETAPOVRD_TX_SFP_DAQ : std_logic;
1539 
1540  signal GTXTXRESET_IN_TX_SFP_ROI : std_logic;
1541  signal GTXRXRESET_IN_TX_SFP_ROI : std_logic;
1542  signal local_pll_lock_out_SFP_ROI : std_logic;
1543  signal GTX_TX_READY_OUT_TX_SFP_ROI : std_logic;
1544  signal GTX_RX_READY_OUT_TX_SFP_ROI : std_logic;
1545  signal PLLLKDET_diag_TX_SFP_ROI : std_logic;
1546  signal local_gtx_reset_diag_TX_SFP_ROI : std_logic;
1547  signal local_mmcm_reset_diag_TX_SFP_ROI : std_logic;
1548  signal GTXTEST_diag_TX_SFP_ROI : std_logic;
1549  signal RXN_IN_TX_SFP_ROI : std_logic;
1550  signal RXP_IN_TX_SFP_ROI : std_logic;
1551  signal TXN_OUT_TX_SFP_ROI : std_logic;
1552  signal TXP_OUT_TX_SFP_ROI : std_logic;
1553  signal clk40_out_TX_SFP_ROI : std_logic;
1554  signal clk120_out_TX_SFP_ROI : std_logic;
1555  signal clk40_in_TX_SFP_ROI : std_logic;
1556  signal clk120_in_TX_SFP_ROI : std_logic;
1557  signal indata_TX_SFP_ROI : std_logic_vector(7 downto 0);
1558  signal odata_TX_SFP_ROI : std_logic_vector(7 downto 0);
1559  signal TXPREEMPHASIS_IN_TX_SFP_ROI : std_logic_vector(3 downto 0);
1560  signal TXPOSTEMPHASIS_IN_TX_SFP_ROI : std_logic_vector(4 downto 0);
1561  signal TXDIFFCTRL_IN_TX_SFP_ROI : std_logic_vector(3 downto 0);
1562  signal RXEQMIX_IN_TX_SFP_ROI : std_logic_vector(2 downto 0);
1563  signal DFECLKDLYADJ_TX_SFP_ROI : std_logic_vector(5 downto 0);
1564  signal DFECLKDLYADJMON_TX_SFP_ROI : std_logic_vector(5 downto 0);
1565  signal DFEDLYOVRD_TX_SFP_ROI : std_logic;
1566  signal DFEEYEDACMON_TX_SFP_ROI : std_logic_vector(4 downto 0);
1567  signal DFESENSCAL_TX_SFP_ROI : std_logic_vector(2 downto 0);
1568  signal DFETAP1_TX_SFP_ROI : std_logic_vector(4 downto 0);
1569  signal DFETAP1MONITOR_TX_SFP_ROI : std_logic_vector(4 downto 0);
1570  signal DFETAP2_TX_SFP_ROI : std_logic_vector(4 downto 0);
1571  signal DFETAP2MONITOR_TX_SFP_ROI : std_logic_vector(4 downto 0);
1572  signal DFETAP3_TX_SFP_ROI : std_logic_vector(3 downto 0);
1573  signal DFETAP3MONITOR_TX_SFP_ROI : std_logic_vector(3 downto 0);
1574  signal DFETAP4_TX_SFP_ROI : std_logic_vector(3 downto 0);
1575  signal DFETAP4MONITOR_TX_SFP_ROI : std_logic_vector(3 downto 0);
1576  signal DFETAPOVRD_TX_SFP_ROI : std_logic;
1577 
1578 
1579 -- glink emulator
1580 
1581  component glink_interface
1582  port (
1583  CLK_40MHz : in std_logic;
1584  CLK_120MHz : in std_logic;
1585  RST : in std_logic;
1586  DAQ_IN : in std_logic_vector (19 DOWNTO 0);
1587  ROI_IN : in std_logic_vector (19 DOWNTO 0);
1588  DAQ_DAV : in std_logic;
1589  ROI_DAV : in std_logic;
1590  DAQ_BYTE : OUT std_logic_vector (7 downto 0);
1591  ROI_BYTE : OUT std_logic_vector (7 downto 0);
1592  DAQ_ENCODED_DIAG : OUT std_logic_vector (23 downto 0);
1593  daq_byte_out : out std_logic_vector (1 downto 0);
1594  byte_pos_out : OUT std_logic_vector (5 downto 0);
1595  word_sel_out : OUT std_logic_vector(1 downto 0);
1596  readout_rst_out : OUT std_logic
1597  );
1598  end component;
1599 
1600  -- Glink emulator signals
1601 
1602  signal daq_in : std_logic_vector (19 DOWNTO 0);
1603  signal roi_in : std_logic_vector (19 DOWNTO 0);
1604  signal daq_dav : std_logic;
1605  signal roi_dav : std_logic;
1606  signal daq_byte : std_logic_vector (7 downto 0);
1607  signal roi_byte : std_logic_vector (7 downto 0);
1608  signal reset_daq : std_logic;
1609  signal daq_encoded_diag : std_logic_vector (23 downto 0);
1610  signal daq_byte_out : std_logic_vector (1 downto 0);
1611 
1612  signal byte_pos_out : std_logic_vector (5 downto 0);
1613  signal word_sel_out : std_logic_vector(1 downto 0);
1614  signal readout_rst_out : std_logic;
1615 
1616 
1617  --component chipscope_icon_u2_c3
1618  -- port (
1619  -- CONTROL0 : inout std_logic_vector(35 downto 0);
1620  -- CONTROL1 : inout std_logic_vector(35 downto 0);
1621  -- CONTROL2 : inout std_logic_vector(35 downto 0)
1622  -- );
1623  --end component;
1624 
1625  --signal CONTROL0 : std_logic_vector(35 downto 0);
1626  --signal CONTROL1 : std_logic_vector(35 downto 0);
1627  --signal CONTROL2 : std_logic_vector(35 downto 0);
1628 
1629  --signal data_ila_daq : std_logic_vector (53 downto 0);
1630  --signal trig_ila_daq : std_logic_vector (33 downto 0);
1631 
1632  --signal data_ila_encoder : std_logic_vector (20 downto 0);
1633  --signal trig_ila_encoder : std_logic_vector (11 downto 0);
1634 
1635  --signal data_ila_gtx_start : std_logic_vector (12 downto 0);
1636  --signal trig_ila_gtx_start : std_logic_vector (2 downto 0);
1637 
1638 
1639  --signal data_ila_1 : std_logic_vector (16 downto 0);
1640 
1641  --component glink_chipscope_analyzer
1642  -- port (
1643  -- CONTROL: inout std_logic_vector(35 downto 0);
1644  -- CLK: in std_logic;
1645  -- DATA: in std_logic_vector(53 downto 0);
1646  -- TRIG0: in std_logic_vector(33 downto 0));
1647  --end component;
1648 
1649  --component glink_chipscope_analyzer_encoder
1650  -- port (
1651  -- CONTROL: inout std_logic_vector(35 downto 0);
1652  -- CLK: in std_logic;
1653  -- DATA: in std_logic_vector(20 downto 0);
1654  -- TRIG0: in std_logic_vector(11 downto 0));
1655  --end component;
1656 
1657  --component glink_chipscope_analyzer_gtx_start is
1658  -- port (
1659  -- CONTROL : inout std_logic_vector(35 downto 0);
1660  -- CLK : in std_logic;
1661  -- DATA : in std_logic_vector(10 downto 0);
1662  -- TRIG0 : in std_logic_vector(0 to 0));
1663  --end component glink_chipscope_analyzer_gtx_start;
1664 
1665 
1666  component daq_glink
1667  port (
1668  data_in : in arr_96(19 downto 0);
1669  bc_counter : in unsigned(11 downto 0);
1670  l1a : in std_logic;
1671  data_out : out std_logic_vector(19 downto 0);
1672  dav : out std_logic;
1673  clk4000 : in std_logic;
1674  clk4008 : in std_logic;
1675  reset : in std_logic;
1676  RAM_global_offset : in unsigned(7 downto 0);
1677  RAM_rel_offsets : in arr_ctr_8bit(18 downto 0);
1678  nslices : in unsigned(7 downto 0));
1679  end component;
1680 
1681 
1682  signal RAM_global_offset : unsigned(7 downto 0);
1683  signal RAM_rel_offsets : arr_ctr_8bit(18 downto 0);
1684  signal nslices : unsigned(7 downto 0);
1685 
1686  signal data_in_daq: arr_96(19 downto 0);
1687 
1688  --control of daq delays
1689  signal data_from_vme_REG_RW_DAQ_SLICE: std_logic_vector(15 downto 0);
1690  signal data_to_vme_REG_RW_DAQ_SLICE: std_logic_vector(15 downto 0);
1691  signal data_from_vme_REG_RW_DAQ_RAM_OFFSET: std_logic_vector(15 downto 0);
1692  signal data_to_vme_REG_RW_DAQ_RAM_OFFSET: std_logic_vector(15 downto 0);
1693 
1694  signal data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1695  signal data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1696 
1697 
1698  attribute keep of start_playback_r1, BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r, send_align: signal is "TRUE";
1699  attribute IOB of BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r : signal is "FORCE";
1700 
1701 
1702  --attribute IOB of BF_DOUT_CTP_00 : signal is "TRUE";
1703  --attribute IOB of BF_DOUT_CTP_01 : signal is "TRUE";
1704  --attribute IOB of BF_DOUT_CTP_02 : signal is "TRUE";
1705  --attribute IOB of BF_DOUT_CTP_03 : signal is "TRUE";
1706  --attribute IOB of BF_DOUT_CTP_04 : signal is "TRUE";
1707  --attribute IOB of BF_DOUT_CTP_05 : signal is "TRUE";
1708  --attribute IOB of BF_DOUT_CTP_06 : signal is "TRUE";
1709  --attribute IOB of BF_DOUT_CTP_07 : signal is "TRUE";
1710  --attribute IOB of BF_DOUT_CTP_08 : signal is "TRUE";
1711  --attribute IOB of BF_DOUT_CTP_09 : signal is "TRUE";
1712  --attribute IOB of BF_DOUT_CTP_10 : signal is "TRUE";
1713  --attribute IOB of BF_DOUT_CTP_11 : signal is "TRUE";
1714  --attribute IOB of BF_DOUT_CTP_12 : signal is "TRUE";
1715  --attribute IOB of BF_DOUT_CTP_13 : signal is "TRUE";
1716  --attribute IOB of BF_DOUT_CTP_14 : signal is "TRUE";
1717  --attribute IOB of BF_DOUT_CTP_15 : signal is "TRUE";
1718  --attribute IOB of BF_DOUT_CTP_16 : signal is "TRUE";
1719  --attribute IOB of BF_DOUT_CTP_17 : signal is "TRUE";
1720  --attribute IOB of BF_DOUT_CTP_18 : signal is "TRUE";
1721  --attribute IOB of BF_DOUT_CTP_19 : signal is "TRUE";
1722  --attribute IOB of BF_DOUT_CTP_20 : signal is "TRUE";
1723  --attribute IOB of BF_DOUT_CTP_21 : signal is "TRUE";
1724  --attribute IOB of BF_DOUT_CTP_22 : signal is "TRUE";
1725  --attribute IOB of BF_DOUT_CTP_23 : signal is "TRUE";
1726  --attribute IOB of BF_DOUT_CTP_24 : signal is "TRUE";
1727  --attribute IOB of BF_DOUT_CTP_25 : signal is "TRUE";
1728  --attribute IOB of BF_DOUT_CTP_26 : signal is "TRUE";
1729  --attribute IOB of BF_DOUT_CTP_27 : signal is "TRUE";
1730  --attribute IOB of BF_DOUT_CTP_28 : signal is "TRUE";
1731  --attribute IOB of BF_DOUT_CTP_29 : signal is "TRUE";
1732  --attribute IOB of BF_DOUT_CTP_64 : signal is "TRUE";
1733  --
1734  --attribute IOB of BF_DOUT_CTP_32 : signal is "TRUE";
1735  --attribute IOB of BF_DOUT_CTP_33 : signal is "TRUE";
1736  --attribute IOB of BF_DOUT_CTP_34 : signal is "TRUE";
1737  --attribute IOB of BF_DOUT_CTP_35 : signal is "TRUE";
1738  --attribute IOB of BF_DOUT_CTP_36 : signal is "TRUE";
1739  --attribute IOB of BF_DOUT_CTP_37 : signal is "TRUE";
1740  --attribute IOB of BF_DOUT_CTP_38 : signal is "TRUE";
1741  --attribute IOB of BF_DOUT_CTP_39 : signal is "TRUE";
1742  --attribute IOB of BF_DOUT_CTP_40 : signal is "TRUE";
1743  --attribute IOB of BF_DOUT_CTP_41 : signal is "TRUE";
1744  --attribute IOB of BF_DOUT_CTP_42 : signal is "TRUE";
1745  --attribute IOB of BF_DOUT_CTP_43 : signal is "TRUE";
1746  --attribute IOB of BF_DOUT_CTP_44 : signal is "TRUE";
1747  --attribute IOB of BF_DOUT_CTP_45 : signal is "TRUE";
1748  --attribute IOB of BF_DOUT_CTP_46 : signal is "TRUE";
1749  --attribute IOB of BF_DOUT_CTP_47 : signal is "TRUE";
1750  --attribute IOB of BF_DOUT_CTP_48 : signal is "TRUE";
1751  --attribute IOB of BF_DOUT_CTP_49 : signal is "TRUE";
1752  --attribute IOB of BF_DOUT_CTP_50 : signal is "TRUE";
1753  --attribute IOB of BF_DOUT_CTP_51 : signal is "TRUE";
1754  --attribute IOB of BF_DOUT_CTP_52 : signal is "TRUE";
1755  --attribute IOB of BF_DOUT_CTP_53 : signal is "TRUE";
1756  --attribute IOB of BF_DOUT_CTP_54 : signal is "TRUE";
1757  --attribute IOB of BF_DOUT_CTP_55 : signal is "TRUE";
1758  --attribute IOB of BF_DOUT_CTP_56 : signal is "TRUE";
1759  --attribute IOB of BF_DOUT_CTP_57 : signal is "TRUE";
1760  --attribute IOB of BF_DOUT_CTP_58 : signal is "TRUE";
1761  --attribute IOB of BF_DOUT_CTP_59 : signal is "TRUE";
1762  --attribute IOB of BF_DOUT_CTP_60 : signal is "TRUE";
1763  --attribute IOB of BF_DOUT_CTP_61 : signal is "TRUE";
1764 
1765 
1766 
1767 
1768 
1769 
1770 
1771 
1772 
1773 Begin
1774 
1775  --safety setup
1776  BF_REQ_CTP_1_INPUT <= '0';
1777  BF_REQ_CTP_2_INPUT <= '0';
1778  BF_REQ_CABLE_1_INPUT<= '0';
1779  BF_REQ_CABLE_2_INPUT<= '0';
1780  BF_REQ_CABLE_3_INPUT<= '0';
1781  BF_LED_REQ_0 <= '0';
1782  BF_LED_REQ_1 <= '0';
1783  BF_LED_REQ_2 <= '0';
1784  BF_LED_REQ_3 <= '0';
1785  BF_LED_REQ_4 <= '0';
1786  --BF_TO_FROM_BSPT_0 <= '0';
1787  --BF_TO_FROM_BSPT_1 <= '0';
1788  BF_TO_FROM_BSPT_2 <= '0';
1789  BF_TO_FROM_BSPT_3 <= '0';
1790  BF_TO_FROM_BSPT_4 <= '0';
1791  BF_TO_FROM_BSPT_5 <= '0';
1792  BF_TO_FROM_BSPT_6 <= '0';
1793  BF_TO_FROM_BSPT_7 <= '0';
1794 
1795  --sdr_data_out_CTP1
1796  BF_DOUT_CTP_00 <= '0';--sdr_data_CTP(0)(0);
1797  BF_DOUT_CTP_01 <= '0';--sdr_data_CTP(0)(1);
1798  BF_DOUT_CTP_02 <= '0';--sdr_data_CTP(0)(2);
1799  BF_DOUT_CTP_03 <= '0';--sdr_data_CTP(0)(3);
1800  BF_DOUT_CTP_04 <= '0';--sdr_data_CTP(0)(4);
1801  BF_DOUT_CTP_05 <= '0';--sdr_data_CTP(0)(5);
1802  BF_DOUT_CTP_06 <= '0';--sdr_data_CTP(0)(6);
1803  BF_DOUT_CTP_07 <= '0';--sdr_data_CTP(0)(7);
1804  BF_DOUT_CTP_08 <= '0';--sdr_data_CTP(0)(8);
1805  BF_DOUT_CTP_09 <= '0';--sdr_data_CTP(0)(9);
1806  BF_DOUT_CTP_10 <= '0';--sdr_data_CTP(0)(10);
1807  BF_DOUT_CTP_11 <= '0';--sdr_data_CTP(0)(11);
1808  BF_DOUT_CTP_12 <= '0';--sdr_data_CTP(0)(12);
1809  BF_DOUT_CTP_13 <= '0';--sdr_data_CTP(0)(13);
1810  BF_DOUT_CTP_14 <= '0';--sdr_data_CTP(0)(14);
1811  BF_DOUT_CTP_15 <= '0';--sdr_data_CTP(0)(15);
1812  BF_DOUT_CTP_16 <= '0';--sdr_data_CTP(0)(16);
1813  BF_DOUT_CTP_17 <= '0';--sdr_data_CTP(0)(17);
1814  BF_DOUT_CTP_18 <= '0';--sdr_data_CTP(0)(18);
1815  BF_DOUT_CTP_19 <= '0';--sdr_data_CTP(0)(19);
1816  BF_DOUT_CTP_20 <= '0';--sdr_data_CTP(0)(20);
1817  BF_DOUT_CTP_21 <= '0';--sdr_data_CTP(0)(21);
1818  BF_DOUT_CTP_22 <= '0';--sdr_data_CTP(0)(22);
1819  BF_DOUT_CTP_23 <= '0';--sdr_data_CTP(0)(23);
1820  BF_DOUT_CTP_24 <= '0';--sdr_data_CTP(0)(24);
1821  BF_DOUT_CTP_25 <= '0';--sdr_data_CTP(0)(25);
1822  BF_DOUT_CTP_26 <= '0';--sdr_data_CTP(0)(26);
1823  BF_DOUT_CTP_27 <= '0';--sdr_data_CTP(0)(27);
1824  BF_DOUT_CTP_28 <= '0';--sdr_data_CTP(0)(28);
1825  BF_DOUT_CTP_29 <= '0';--sdr_data_CTP(0)(29);
1826  BF_DOUT_CTP_30 <= '0';--'0';
1827  BF_DOUT_CTP_64 <= '0';--sdr_data_CTP(0)(30);
1828  BF_DOUT_CTP_31 <= '0';--sdr_data_CTP(0)(31);
1829 
1830 
1831  BF_DOUT_CTP_32 <= '0';--sdr_data_CTP(1)(0);
1832  BF_DOUT_CTP_33 <= '0';--sdr_data_CTP(1)(1);
1833  BF_DOUT_CTP_34 <= '0';--sdr_data_CTP(1)(2);
1834  BF_DOUT_CTP_35 <= '0';--sdr_data_CTP(1)(3);
1835  BF_DOUT_CTP_36 <= '0';--sdr_data_CTP(1)(4);
1836  BF_DOUT_CTP_37 <= '0';--sdr_data_CTP(1)(5);
1837  BF_DOUT_CTP_38 <= '0';--sdr_data_CTP(1)(6);
1838  BF_DOUT_CTP_39 <= '0';--sdr_data_CTP(1)(7);
1839  BF_DOUT_CTP_40 <= '0';--sdr_data_CTP(1)(8);
1840  BF_DOUT_CTP_41 <= '0';--sdr_data_CTP(1)(9);
1841  BF_DOUT_CTP_42 <= '0';--sdr_data_CTP(1)(10);
1842  BF_DOUT_CTP_43 <= '0';--sdr_data_CTP(1)(11);
1843  BF_DOUT_CTP_44 <= '0';--sdr_data_CTP(1)(12);
1844  BF_DOUT_CTP_45 <= '0';--sdr_data_CTP(1)(13);
1845  BF_DOUT_CTP_46 <= '0';--sdr_data_CTP(1)(14);
1846  BF_DOUT_CTP_47 <= '0';--sdr_data_CTP(1)(15);
1847  BF_DOUT_CTP_48 <= '0';--sdr_data_CTP(1)(16);
1848  BF_DOUT_CTP_49 <= '0';--sdr_data_CTP(1)(17);
1849  BF_DOUT_CTP_50 <= '0';--sdr_data_CTP(1)(18);
1850  BF_DOUT_CTP_51 <= '0';--sdr_data_CTP(1)(19);
1851  BF_DOUT_CTP_52 <= '0';--sdr_data_CTP(1)(20);
1852  BF_DOUT_CTP_53 <= '0';--sdr_data_CTP(1)(21);
1853  BF_DOUT_CTP_54 <= '0';--sdr_data_CTP(1)(22);
1854  BF_DOUT_CTP_55 <= '0';--sdr_data_CTP(1)(23);
1855  BF_DOUT_CTP_56 <= '0';--sdr_data_CTP(1)(24);
1856  BF_DOUT_CTP_57 <= '0';--sdr_data_CTP(1)(25);
1857  BF_DOUT_CTP_58 <= '0';--sdr_data_CTP(1)(26);
1858  BF_DOUT_CTP_59 <= '0';--sdr_data_CTP(1)(27);
1859  BF_DOUT_CTP_60 <= '0';--sdr_data_CTP(1)(28);
1860  BF_DOUT_CTP_61 <= '0';--sdr_data_CTP(1)(29);
1861  BF_DOUT_CTP_62 <= '0';--'0';
1862  BF_DOUT_CTP_65 <= '0';--sdr_data_CTP(1)(30);
1863  BF_DOUT_CTP_63 <= '0';--sdr_data_CTP(1)(31);
1864 
1865 
1866 
1867 
1868 
1869 
1870 
1871 
1872  --ddr_data_in_CTP2(0) <=BF_DOUT_CTP_32;
1873  --ddr_data_in_CTP2(1) <=BF_DOUT_CTP_33;
1874  --ddr_data_in_CTP2(2) <=BF_DOUT_CTP_34;
1875  --ddr_data_in_CTP2(3) <=BF_DOUT_CTP_35;
1876  --ddr_data_in_CTP2(4) <=BF_DOUT_CTP_36;
1877  --ddr_data_in_CTP2(5) <=BF_DOUT_CTP_37;
1878  --ddr_data_in_CTP2(6) <=BF_DOUT_CTP_38;
1879  --ddr_data_in_CTP2(7) <=BF_DOUT_CTP_39;
1880  --ddr_data_in_CTP2(8) <=BF_DOUT_CTP_40;
1881  --ddr_data_in_CTP2(9) <=BF_DOUT_CTP_41;
1882  --ddr_data_in_CTP2(10) <=BF_DOUT_CTP_42;
1883  --ddr_data_in_CTP2(11) <=BF_DOUT_CTP_43;
1884  --ddr_data_in_CTP2(12) <=BF_DOUT_CTP_44;
1885  --ddr_data_in_CTP2(13) <=BF_DOUT_CTP_45;
1886  --ddr_data_in_CTP2(14) <=BF_DOUT_CTP_46;
1887  --ddr_data_in_CTP2(15) <=BF_DOUT_CTP_47;
1888  --ddr_data_in_CTP2(16) <=BF_DOUT_CTP_48;
1889  --ddr_data_in_CTP2(17) <=BF_DOUT_CTP_49;
1890  --ddr_data_in_CTP2(18) <=BF_DOUT_CTP_50;
1891  --ddr_data_in_CTP2(19) <=BF_DOUT_CTP_51;
1892  --ddr_data_in_CTP2(20) <=BF_DOUT_CTP_52;
1893  --ddr_data_in_CTP2(21) <=BF_DOUT_CTP_53;
1894  --ddr_data_in_CTP2(22) <=BF_DOUT_CTP_54;
1895  --ddr_data_in_CTP2(23) <=BF_DOUT_CTP_55;
1896  --ddr_data_in_CTP2(24) <=BF_DOUT_CTP_56;
1897  --ddr_data_in_CTP2(25) <=BF_DOUT_CTP_57;
1898  --ddr_data_in_CTP2(26) <=BF_DOUT_CTP_58;
1899  --ddr_data_in_CTP2(27) <=BF_DOUT_CTP_59;
1900  --ddr_data_in_CTP2(28) <=BF_DOUT_CTP_60;
1901  --ddr_data_in_CTP2(29) <=BF_DOUT_CTP_61;
1902  --ddr_data_in_CTP2(30) <=BF_DOUT_CTP_62;
1903  --ddr_data_in_CTP2(31) <=BF_DOUT_CTP_65;
1904  --ddr_data_in_CTP2(32) <=BF_DOUT_CTP_63;
1905 
1906 
1907  D_CBL_00_B <= ddr_data_out_RTM1(0);
1908  D_CBL_01_B <= ddr_data_out_RTM1(1);
1909  D_CBL_02_B <= ddr_data_out_RTM1(2);
1910  D_CBL_03_B <= ddr_data_out_RTM1(3);
1911  D_CBL_04_B <= ddr_data_out_RTM1(4);
1912  D_CBL_05_B <= ddr_data_out_RTM1(5);
1913  D_CBL_06_B <= ddr_data_out_RTM1(6);
1914  D_CBL_07_B <= ddr_data_out_RTM1(7);
1915  D_CBL_08_B <= ddr_data_out_RTM1(8);
1916  D_CBL_09_B <= ddr_data_out_RTM1(9);
1917  D_CBL_10_B <= ddr_data_out_RTM1(10);
1918  D_CBL_11_B <= ddr_data_out_RTM1(11);
1919  D_CBL_12_B <= ddr_data_out_RTM1(12);
1920  D_CBL_13_B <= ddr_data_out_RTM1(13);
1921  D_CBL_14_B <= ddr_data_out_RTM1(14);
1922  D_CBL_15_B <= ddr_data_out_RTM1(15);
1923  D_CBL_16_B <= ddr_data_out_RTM1(16);
1924  D_CBL_17_B <= ddr_data_out_RTM1(17);
1925  D_CBL_18_B <= ddr_data_out_RTM1(18);
1926  D_CBL_19_B <= ddr_data_out_RTM1(19);
1927  D_CBL_20_B <= ddr_data_out_RTM1(20);
1928  D_CBL_21_B <= ddr_data_out_RTM1(21);
1929  D_CBL_22_B <= ddr_data_out_RTM1(22);
1930  D_CBL_23_B <= ddr_data_out_RTM1(23);
1931  D_CBL_24_B <= ddr_data_out_RTM1(24);
1932  D_CBL_25_B <= ddr_data_out_RTM1(26);
1933  D_CBL_26_B <= ddr_data_out_RTM1(25);
1934  D_CBL_81_B <= '0';
1935 
1936  D_CBL_27_B <= ddr_data_out_RTM2(0);
1937  D_CBL_28_B <= ddr_data_out_RTM2(1);
1938  D_CBL_29_B <= ddr_data_out_RTM2(2);
1939  D_CBL_30_B <= ddr_data_out_RTM2(3);
1940  D_CBL_31_B <= ddr_data_out_RTM2(4);
1941  D_CBL_32_B <= ddr_data_out_RTM2(5);
1942  D_CBL_33_B <= ddr_data_out_RTM2(6);
1943  D_CBL_34_B <= ddr_data_out_RTM2(7);
1944  D_CBL_35_B <= ddr_data_out_RTM2(8);
1945  D_CBL_36_B <= ddr_data_out_RTM2(9);
1946  D_CBL_37_B <= ddr_data_out_RTM2(10);
1947  D_CBL_38_B <= ddr_data_out_RTM2(11);
1948  D_CBL_39_B <= ddr_data_out_RTM2(12);
1949  D_CBL_40_B <= ddr_data_out_RTM2(13);
1950  D_CBL_41_B <= ddr_data_out_RTM2(14);
1951  D_CBL_42_B <= ddr_data_out_RTM2(15);
1952  D_CBL_43_B <= ddr_data_out_RTM2(16);
1953  D_CBL_44_B <= ddr_data_out_RTM2(17);
1954  D_CBL_45_B <= ddr_data_out_RTM2(18);
1955  D_CBL_46_B <= ddr_data_out_RTM2(19);
1956  D_CBL_47_B <= ddr_data_out_RTM2(20);
1957  D_CBL_50_B <= ddr_data_out_RTM2(21);
1958  D_CBL_51_B <= ddr_data_out_RTM2(22);
1959  D_CBL_52_B <= ddr_data_out_RTM2(23);
1960  D_CBL_53_B <= ddr_data_out_RTM2(24);
1961  D_CBL_48_B <= ddr_data_out_RTM2(26);
1962  D_CBL_49_B <= ddr_data_out_RTM2(25);
1963  D_CBL_82_B <= '0';
1964 
1965  D_CBL_54_B <= '0';
1966  D_CBL_55_B <= '0';
1967  D_CBL_56_B <= '0';
1968  D_CBL_57_B <= '0';
1969  D_CBL_58_B <= '0';
1970  D_CBL_59_B <= '0';
1971  D_CBL_60_B <= '0';
1972  D_CBL_61_B <= '0';
1973  D_CBL_62_B <= '0';
1974  D_CBL_63_B <= '0';
1975  D_CBL_64_B <= '0';
1976  D_CBL_65_B <= '0';
1977  D_CBL_66_B <= '0';
1978  D_CBL_67_B <= '0';
1979  D_CBL_68_B <= '0';
1980  D_CBL_69_B <= '0';
1981  D_CBL_70_B <= '0';
1982  D_CBL_71_B <= '0';
1983  D_CBL_72_B <= '0';
1984  D_CBL_73_B <= '0';
1985  D_CBL_74_B <= '0';
1986  D_CBL_75_B <= '0';
1987  D_CBL_76_B <= '0';
1988  D_CBL_77_B <= '0';
1989  D_CBL_80_B <= '0';
1990  D_CBL_79_B <= '0';
1991  D_CBL_78_B <= '0';
1992  D_CBL_83_B <= '0';
1993 
1994 
1995  --backplane bus assignment
1996  P(0)(0) <= P0_0;
1997  P(0)(1) <= P0_1;
1998  P(0)(2) <= P0_2;
1999  P(0)(3) <= P0_3;
2000  P(0)(4) <= P0_4;
2001  P(0)(5) <= P0_5;
2002  P(0)(6) <= P0_6;
2003  P(0)(7) <= P0_7;
2004  P(0)(8) <= P0_8;
2005  P(0)(9) <= P0_9;
2006  P(0)(10) <= P0_10;
2007  P(0)(11) <= P0_11;
2008  P(0)(12) <= P0_12;
2009  P(0)(13) <= P0_13;
2010  P(0)(14) <= P0_14;
2011  P(0)(15) <= P0_15;
2012  P(0)(16) <= P0_16;
2013  P(0)(17) <= P0_17;
2014  P(0)(18) <= P0_18;
2015  P(0)(19) <= P0_19;
2016  P(0)(20) <= P0_20;
2017  P(0)(21) <= P0_21;
2018  P(0)(22) <= P0_22;
2019  P(0)(23) <= P0_23;
2020  P(0)(24) <= P0_24;
2021  P(1)(0) <= P1_0;
2022  P(1)(1) <= P1_1;
2023  P(1)(2) <= P1_2;
2024  P(1)(3) <= P1_3;
2025  P(1)(4) <= P1_4;
2026  P(1)(5) <= P1_5;
2027  P(1)(6) <= P1_6;
2028  P(1)(7) <= P1_7;
2029  P(1)(8) <= P1_8;
2030  P(1)(9) <= P1_9;
2031  P(1)(10) <= P1_10;
2032  P(1)(11) <= P1_11;
2033  P(1)(12) <= P1_12;
2034  P(1)(13) <= P1_13;
2035  P(1)(14) <= P1_14;
2036  P(1)(15) <= P1_15;
2037  P(1)(16) <= P1_16;
2038  P(1)(17) <= P1_17;
2039  P(1)(18) <= P1_18;
2040  P(1)(19) <= P1_19;
2041  P(1)(20) <= P1_20;
2042  P(1)(21) <= P1_21;
2043  P(1)(22) <= P1_22;
2044  P(1)(23) <= P1_23;
2045  P(1)(24) <= P1_24;
2046  P(2)(0) <= P2_0;
2047  P(2)(1) <= P2_1;
2048  P(2)(2) <= P2_2;
2049  P(2)(3) <= P2_3;
2050  P(2)(4) <= P2_4;
2051  P(2)(5) <= P2_5;
2052  P(2)(6) <= P2_6;
2053  P(2)(7) <= P2_7;
2054  P(2)(8) <= P2_8;
2055  P(2)(9) <= P2_9;
2056  P(2)(10) <= P2_10;
2057  P(2)(11) <= P2_11;
2058  P(2)(12) <= P2_12;
2059  P(2)(13) <= P2_13;
2060  P(2)(14) <= P2_14;
2061  P(2)(15) <= P2_15;
2062  P(2)(16) <= P2_16;
2063  P(2)(17) <= P2_17;
2064  P(2)(18) <= P2_18;
2065  P(2)(19) <= P2_19;
2066  P(2)(20) <= P2_20;
2067  P(2)(21) <= P2_21;
2068  P(2)(22) <= P2_22;
2069  P(2)(23) <= P2_23;
2070  P(2)(24) <= P2_24;
2071  P(3)(0) <= P3_0;
2072  P(3)(1) <= P3_1;
2073  P(3)(2) <= P3_2;
2074  P(3)(3) <= P3_3;
2075  P(3)(4) <= P3_4;
2076  P(3)(5) <= P3_5;
2077  P(3)(6) <= P3_6;
2078  P(3)(7) <= P3_7;
2079  P(3)(8) <= P3_8;
2080  P(3)(9) <= P3_9;
2081  P(3)(10) <= P3_10;
2082  P(3)(11) <= P3_11;
2083  P(3)(12) <= P3_12;
2084  P(3)(13) <= P3_13;
2085  P(3)(14) <= P3_14;
2086  P(3)(15) <= P3_15;
2087  P(3)(16) <= P3_16;
2088  P(3)(17) <= P3_17;
2089  P(3)(18) <= P3_18;
2090  P(3)(19) <= P3_19;
2091  P(3)(20) <= P3_20;
2092  P(3)(21) <= P3_21;
2093  P(3)(22) <= P3_22;
2094  P(3)(23) <= P3_23;
2095  P(3)(24) <= P3_24;
2096  P(4)(0) <= P4_0;
2097  P(4)(1) <= P4_1;
2098  P(4)(2) <= P4_2;
2099  P(4)(3) <= P4_3;
2100  P(4)(4) <= P4_4;
2101  P(4)(5) <= P4_5;
2102  P(4)(6) <= P4_6;
2103  P(4)(7) <= P4_7;
2104  P(4)(8) <= P4_8;
2105  P(4)(9) <= P4_9;
2106  P(4)(10) <= P4_10;
2107  P(4)(11) <= P4_11;
2108  P(4)(12) <= P4_12;
2109  P(4)(13) <= P4_13;
2110  P(4)(14) <= P4_14;
2111  P(4)(15) <= P4_15;
2112  P(4)(16) <= P4_16;
2113  P(4)(17) <= P4_17;
2114  P(4)(18) <= P4_18;
2115  P(4)(19) <= P4_19;
2116  P(4)(20) <= P4_20;
2117  P(4)(21) <= P4_21;
2118  P(4)(22) <= P4_22;
2119  P(4)(23) <= P4_23;
2120  P(4)(24) <= P4_24;
2121  P(5)(0) <= P5_0;
2122  P(5)(1) <= P5_1;
2123  P(5)(2) <= P5_2;
2124  P(5)(3) <= P5_3;
2125  P(5)(4) <= P5_4;
2126  P(5)(5) <= P5_5;
2127  P(5)(6) <= P5_6;
2128  P(5)(7) <= P5_7;
2129  P(5)(8) <= P5_8;
2130  P(5)(9) <= P5_9;
2131  P(5)(10) <= P5_10;
2132  P(5)(11) <= P5_11;
2133  P(5)(12) <= P5_12;
2134  P(5)(13) <= P5_13;
2135  P(5)(14) <= P5_14;
2136  P(5)(15) <= P5_15;
2137  P(5)(16) <= P5_16;
2138  P(5)(17) <= P5_17;
2139  P(5)(18) <= P5_18;
2140  P(5)(19) <= P5_19;
2141  P(5)(20) <= P5_20;
2142  P(5)(21) <= P5_21;
2143  P(5)(22) <= P5_22;
2144  P(5)(23) <= P5_23;
2145  P(5)(24) <= P5_24;
2146  P(6)(0) <= P6_0;
2147  P(6)(1) <= P6_1;
2148  P(6)(2) <= P6_2;
2149  P(6)(3) <= P6_3;
2150  P(6)(4) <= P6_4;
2151  P(6)(5) <= P6_5;
2152  P(6)(6) <= P6_6;
2153  P(6)(7) <= P6_7;
2154  P(6)(8) <= P6_8;
2155  P(6)(9) <= P6_9;
2156  P(6)(10) <= P6_10;
2157  P(6)(11) <= P6_11;
2158  P(6)(12) <= P6_12;
2159  P(6)(13) <= P6_13;
2160  P(6)(14) <= P6_14;
2161  P(6)(15) <= P6_15;
2162  P(6)(16) <= P6_16;
2163  P(6)(17) <= P6_17;
2164  P(6)(18) <= P6_18;
2165  P(6)(19) <= P6_19;
2166  P(6)(20) <= P6_20;
2167  P(6)(21) <= P6_21;
2168  P(6)(22) <= P6_22;
2169  P(6)(23) <= P6_23;
2170  P(6)(24) <= P6_24;
2171  P(7)(0) <= P7_0;
2172  P(7)(1) <= P7_1;
2173  P(7)(2) <= P7_2;
2174  P(7)(3) <= P7_3;
2175  P(7)(4) <= P7_4;
2176  P(7)(5) <= P7_5;
2177  P(7)(6) <= P7_6;
2178  P(7)(7) <= P7_7;
2179  P(7)(8) <= P7_8;
2180  P(7)(9) <= P7_9;
2181  P(7)(10) <= P7_10;
2182  P(7)(11) <= P7_11;
2183  P(7)(12) <= P7_12;
2184  P(7)(13) <= P7_13;
2185  P(7)(14) <= P7_14;
2186  P(7)(15) <= P7_15;
2187  P(7)(16) <= P7_16;
2188  P(7)(17) <= P7_17;
2189  P(7)(18) <= P7_18;
2190  P(7)(19) <= P7_19;
2191  P(7)(20) <= P7_20;
2192  P(7)(21) <= P7_21;
2193  P(7)(22) <= P7_22;
2194  P(7)(23) <= P7_23;
2195  P(7)(24) <= P7_24;
2196  P(8)(0) <= P8_0;
2197  P(8)(1) <= P8_1;
2198  P(8)(2) <= P8_2;
2199  P(8)(3) <= P8_3;
2200  P(8)(4) <= P8_4;
2201  P(8)(5) <= P8_5;
2202  P(8)(6) <= P8_6;
2203  P(8)(7) <= P8_7;
2204  P(8)(8) <= P8_8;
2205  P(8)(9) <= P8_9;
2206  P(8)(10) <= P8_10;
2207  P(8)(11) <= P8_11;
2208  P(8)(12) <= P8_12;
2209  P(8)(13) <= P8_13;
2210  P(8)(14) <= P8_14;
2211  P(8)(15) <= P8_15;
2212  P(8)(16) <= P8_16;
2213  P(8)(17) <= P8_17;
2214  P(8)(18) <= P8_18;
2215  P(8)(19) <= P8_19;
2216  P(8)(20) <= P8_20;
2217  P(8)(21) <= P8_21;
2218  P(8)(22) <= P8_22;
2219  P(8)(23) <= P8_23;
2220  P(8)(24) <= P8_24;
2221  P(9)(0) <= P9_0;
2222  P(9)(1) <= P9_1;
2223  P(9)(2) <= P9_2;
2224  P(9)(3) <= P9_3;
2225  P(9)(4) <= P9_4;
2226  P(9)(5) <= P9_5;
2227  P(9)(6) <= P9_6;
2228  P(9)(7) <= P9_7;
2229  P(9)(8) <= P9_8;
2230  P(9)(9) <= P9_9;
2231  P(9)(10) <= P9_10;
2232  P(9)(11) <= P9_11;
2233  P(9)(12) <= P9_12;
2234  P(9)(13) <= P9_13;
2235  P(9)(14) <= P9_14;
2236  P(9)(15) <= P9_15;
2237  P(9)(16) <= P9_16;
2238  P(9)(17) <= P9_17;
2239  P(9)(18) <= P9_18;
2240  P(9)(19) <= P9_19;
2241  P(9)(20) <= P9_20;
2242  P(9)(21) <= P9_21;
2243  P(9)(22) <= P9_22;
2244  P(9)(23) <= P9_23;
2245  P(9)(24) <= P9_24;
2246  P(10)(0) <= P10_0;
2247  P(10)(1) <= P10_1;
2248  P(10)(2) <= P10_2;
2249  P(10)(3) <= P10_3;
2250  P(10)(4) <= P10_4;
2251  P(10)(5) <= P10_5;
2252  P(10)(6) <= P10_6;
2253  P(10)(7) <= P10_7;
2254  P(10)(8) <= P10_8;
2255  P(10)(9) <= P10_9;
2256  P(10)(10) <= P10_10;
2257  P(10)(11) <= P10_11;
2258  P(10)(12) <= P10_12;
2259  P(10)(13) <= P10_13;
2260  P(10)(14) <= P10_14;
2261  P(10)(15) <= P10_15;
2262  P(10)(16) <= P10_16;
2263  P(10)(17) <= P10_17;
2264  P(10)(18) <= P10_18;
2265  P(10)(19) <= P10_19;
2266  P(10)(20) <= P10_20;
2267  P(10)(21) <= P10_21;
2268  P(10)(22) <= P10_22;
2269  P(10)(23) <= P10_23;
2270  P(10)(24) <= P10_24;
2271  P(11)(0) <= P11_0;
2272  P(11)(1) <= P11_1;
2273  P(11)(2) <= P11_2;
2274  P(11)(3) <= P11_3;
2275  P(11)(4) <= P11_4;
2276  P(11)(5) <= P11_5;
2277  P(11)(6) <= P11_6;
2278  P(11)(7) <= P11_7;
2279  P(11)(8) <= P11_8;
2280  P(11)(9) <= P11_9;
2281  P(11)(10) <= P11_10;
2282  P(11)(11) <= P11_11;
2283  P(11)(12) <= P11_12;
2284  P(11)(13) <= P11_13;
2285  P(11)(14) <= P11_14;
2286  P(11)(15) <= P11_15;
2287  P(11)(16) <= P11_16;
2288  P(11)(17) <= P11_17;
2289  P(11)(18) <= P11_18;
2290  P(11)(19) <= P11_19;
2291  P(11)(20) <= P11_20;
2292  P(11)(21) <= P11_21;
2293  P(11)(22) <= P11_22;
2294  P(11)(23) <= P11_23;
2295  P(11)(24) <= P11_24;
2296  P(12)(0) <= P12_0;
2297  P(12)(1) <= P12_1;
2298  P(12)(2) <= P12_2;
2299  P(12)(3) <= P12_3;
2300  P(12)(4) <= P12_4;
2301  P(12)(5) <= P12_5;
2302  P(12)(6) <= P12_6;
2303  P(12)(7) <= P12_7;
2304  P(12)(8) <= P12_8;
2305  P(12)(9) <= P12_9;
2306  P(12)(10) <= P12_10;
2307  P(12)(11) <= P12_11;
2308  P(12)(12) <= P12_12;
2309  P(12)(13) <= P12_13;
2310  P(12)(14) <= P12_14;
2311  P(12)(15) <= P12_15;
2312  P(12)(16) <= P12_16;
2313  P(12)(17) <= P12_17;
2314  P(12)(18) <= P12_18;
2315  P(12)(19) <= P12_19;
2316  P(12)(20) <= P12_20;
2317  P(12)(21) <= P12_21;
2318  P(12)(22) <= P12_22;
2319  P(12)(23) <= P12_23;
2320  P(12)(24) <= P12_24;
2321  P(13)(0) <= P13_0;
2322  P(13)(1) <= P13_1;
2323  P(13)(2) <= P13_2;
2324  P(13)(3) <= P13_3;
2325  P(13)(4) <= P13_4;
2326  P(13)(5) <= P13_5;
2327  P(13)(6) <= P13_6;
2328  P(13)(7) <= P13_7;
2329  P(13)(8) <= P13_8;
2330  P(13)(9) <= P13_9;
2331  P(13)(10) <= P13_10;
2332  P(13)(11) <= P13_11;
2333  P(13)(12) <= P13_12;
2334  P(13)(13) <= P13_13;
2335  P(13)(14) <= P13_14;
2336  P(13)(15) <= P13_15;
2337  P(13)(16) <= P13_16;
2338  P(13)(17) <= P13_17;
2339  P(13)(18) <= P13_18;
2340  P(13)(19) <= P13_19;
2341  P(13)(20) <= P13_20;
2342  P(13)(21) <= P13_21;
2343  P(13)(22) <= P13_22;
2344  P(13)(23) <= P13_23;
2345  P(13)(24) <= P13_24;
2346  P(14)(0) <= P14_0;
2347  P(14)(1) <= P14_1;
2348  P(14)(2) <= P14_2;
2349  P(14)(3) <= P14_3;
2350  P(14)(4) <= P14_4;
2351  P(14)(5) <= P14_5;
2352  P(14)(6) <= P14_6;
2353  P(14)(7) <= P14_7;
2354  P(14)(8) <= P14_8;
2355  P(14)(9) <= P14_9;
2356  P(14)(10) <= P14_10;
2357  P(14)(11) <= P14_11;
2358  P(14)(12) <= P14_12;
2359  P(14)(13) <= P14_13;
2360  P(14)(14) <= P14_14;
2361  P(14)(15) <= P14_15;
2362  P(14)(16) <= P14_16;
2363  P(14)(17) <= P14_17;
2364  P(14)(18) <= P14_18;
2365  P(14)(19) <= P14_19;
2366  P(14)(20) <= P14_20;
2367  P(14)(21) <= P14_21;
2368  P(14)(22) <= P14_22;
2369  P(14)(23) <= P14_23;
2370  P(14)(24) <= P14_24;
2371  P(15)(0) <= P15_0;
2372  P(15)(1) <= P15_1;
2373  P(15)(2) <= P15_2;
2374  P(15)(3) <= P15_3;
2375  P(15)(4) <= P15_4;
2376  P(15)(5) <= P15_5;
2377  P(15)(6) <= P15_6;
2378  P(15)(7) <= P15_7;
2379  P(15)(8) <= P15_8;
2380  P(15)(9) <= P15_9;
2381  P(15)(10) <= P15_10;
2382  P(15)(11) <= P15_11;
2383  P(15)(12) <= P15_12;
2384  P(15)(13) <= P15_13;
2385  P(15)(14) <= P15_14;
2386  P(15)(15) <= P15_15;
2387  P(15)(16) <= P15_16;
2388  P(15)(17) <= P15_17;
2389  P(15)(18) <= P15_18;
2390  P(15)(19) <= P15_19;
2391  P(15)(20) <= P15_20;
2392  P(15)(21) <= P15_21;
2393  P(15)(22) <= P15_22;
2394  P(15)(23) <= P15_23;
2395  P(15)(24) <= P15_24;
2396 
2397 
2398 
2399  MP1_F01_QUAD_110_TRN_0_DIR <= TXP_OUT(0) ;
2400  MP1_F01_QUAD_110_TRN_0_CMP <= TXN_OUT(0) ;
2401  MP1_F03_QUAD_110_TRN_1_DIR <= TXP_OUT(1) ;
2402  MP1_F03_QUAD_110_TRN_1_CMP <= TXN_OUT(1) ;
2403  MP1_F07_QUAD_110_TRN_2_DIR <= TXP_OUT(2) ;
2404  MP1_F07_QUAD_110_TRN_2_CMP <= TXN_OUT(2) ;
2405  MP1_F05_QUAD_110_TRN_3_DIR <= TXP_OUT(3) ;
2406  MP1_F05_QUAD_110_TRN_3_CMP <= TXN_OUT(3) ;
2407  MP1_F09_QUAD_111_TRN_0_DIR <= TXP_OUT(4) ;
2408  MP1_F09_QUAD_111_TRN_0_CMP <= TXN_OUT(4) ;
2409  MP1_F11_QUAD_111_TRN_1_DIR <= TXP_OUT(5) ;
2410  MP1_F11_QUAD_111_TRN_1_CMP <= TXN_OUT(5) ;
2411  MP1_F10_QUAD_111_TRN_2_DIR <= TXP_OUT(6) ;
2412  MP1_F10_QUAD_111_TRN_2_CMP <= TXN_OUT(6) ;
2413  MP1_F08_QUAD_111_TRN_3_DIR <= TXP_OUT(7) ;
2414  MP1_F08_QUAD_111_TRN_3_CMP <= TXN_OUT(7) ;
2415  MP1_F04_QUAD_112_TRN_0_DIR <= TXP_OUT(8) ;
2416  MP1_F04_QUAD_112_TRN_0_CMP <= TXN_OUT(8) ;
2417  MP1_F06_QUAD_112_TRN_1_DIR <= TXP_OUT(9) ;
2418  MP1_F06_QUAD_112_TRN_1_CMP <= TXN_OUT(9) ;
2419  MP1_F02_QUAD_112_TRN_2_DIR <= TXP_OUT(10) ;
2420  MP1_F02_QUAD_112_TRN_2_CMP <= TXN_OUT(10) ;
2421  MP1_F00_QUAD_112_TRN_3_DIR <= TXP_OUT(11) ;
2422  MP1_F00_QUAD_112_TRN_3_CMP <= TXN_OUT(11) ;
2423  MP2_F01_QUAD_113_TRN_0_DIR <= TXP_OUT(12) ;
2424  MP2_F01_QUAD_113_TRN_0_CMP <= TXN_OUT(12) ;
2425  MP2_F03_QUAD_113_TRN_1_DIR <= TXP_OUT(13) ;
2426  MP2_F03_QUAD_113_TRN_1_CMP <= TXN_OUT(13) ;
2427  MP2_F07_QUAD_113_TRN_2_DIR <= TXP_OUT(14) ;
2428  MP2_F07_QUAD_113_TRN_2_CMP <= TXN_OUT(14) ;
2429  MP2_F05_QUAD_113_TRN_3_DIR <= TXP_OUT(15) ;
2430  MP2_F05_QUAD_113_TRN_3_CMP <= TXN_OUT(15) ;
2431  MP2_F09_QUAD_114_TRN_0_DIR <= TXP_OUT(16) ;
2432  MP2_F09_QUAD_114_TRN_0_CMP <= TXN_OUT(16) ;
2433  MP2_F11_QUAD_114_TRN_1_DIR <= TXP_OUT(17) ;
2434  MP2_F11_QUAD_114_TRN_1_CMP <= TXN_OUT(17) ;
2435  MP2_F10_QUAD_114_TRN_2_DIR <= TXP_OUT(18) ;
2436  MP2_F10_QUAD_114_TRN_2_CMP <= TXN_OUT(18) ;
2437  MP2_F08_QUAD_114_TRN_3_DIR <= TXP_OUT(19) ;
2438  MP2_F08_QUAD_114_TRN_3_CMP <= TXN_OUT(19) ;
2439  MP2_F04_QUAD_115_TRN_0_DIR <= TXP_OUT(20) ;
2440  MP2_F04_QUAD_115_TRN_0_CMP <= TXN_OUT(20) ;
2441  MP2_F06_QUAD_115_TRN_1_DIR <= TXP_OUT(21) ;
2442  MP2_F06_QUAD_115_TRN_1_CMP <= TXN_OUT(21) ;
2443  MP2_F02_QUAD_115_TRN_2_DIR <= TXP_OUT(22) ;
2444  MP2_F02_QUAD_115_TRN_2_CMP <= TXN_OUT(22) ;
2445  MP2_F00_QUAD_115_TRN_3_DIR <= TXP_OUT(23) ;
2446  MP2_F00_QUAD_115_TRN_3_CMP <= TXN_OUT(23) ;
2447 
2448  MGTREFCLK_PAD_P_IN(0) <= CLK_320MHz64_LHC_BF_QUAD_111_DIR;
2449  MGTREFCLK_PAD_N_IN(0) <= CLK_320MHz64_LHC_BF_QUAD_111_CMP;
2450  MGTREFCLK_PAD_P_IN(1) <= CLK_320MHz64_LHC_BF_QUAD_114_DIR;
2451  MGTREFCLK_PAD_N_IN(1) <= CLK_320MHz64_LHC_BF_QUAD_114_CMP;
2452 
2453 
2454 
2455  --debug pins bus assignment
2456  BF_DEBUG_0 <= BF_DEBUG(0);
2457  BF_DEBUG_1 <= BF_DEBUG(1);
2458  BF_DEBUG_2 <= BF_DEBUG(2);
2459  BF_DEBUG_3 <= BF_DEBUG(3);
2460  BF_DEBUG_4 <= BF_DEBUG(4);
2461  BF_DEBUG_5 <= BF_DEBUG(5);
2462  BF_DEBUG_6 <= BF_DEBUG(6);
2463  BF_DEBUG_7 <= BF_DEBUG(7);
2464  BF_DEBUG_8 <= BF_DEBUG(8);
2465  BF_DEBUG_9 <= BF_DEBUG(9);
2466 
2467  --BF_DEBUG(8) <= buf_clk40;
2468 
2469  ODDR_inst_buf_clk_40 : ODDR
2470  generic map(
2471  DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
2472  INIT => '0', -- Initial value for Q port ('1' or '0')
2473  SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
2474  port map (
2475  Q => BF_DEBUG(8), -- 1-bit DDR output
2476  C => buf_clk40, -- 1-bit clock input
2477  CE => '1', -- 1-bit clock enable input
2478  D1 => '1', -- 1-bit data input (positive edge)
2479  D2 => '0', -- 1-bit data input (negative edge)
2480  R => (not pll_locked), -- 1-bit reset input
2481  S => '0' -- 1-bit set input
2482  );
2483 
2484  BF_DEBUG(9) <= DATA96(5)(0);--start_playback;--BF_TO_TP_DAQ_SLINK_RETURN_DIR;--send_align(0);-- BUF_TTC_BNCH_CNT_RES; --bunch counter reset
2485 
2486  BF_DEBUG(7 downto 0)<=(others=>'0');
2487 
2488  vme_address(1) <= OCB_A01;
2489  vme_address(2) <= OCB_A02;
2490  vme_address(3) <= OCB_A03;
2491  vme_address(4) <= OCB_A04;
2492  vme_address(5) <= OCB_A05;
2493  vme_address(6) <= OCB_A06;
2494  vme_address(7) <= OCB_A07;
2495  vme_address(8) <= OCB_A08;
2496  vme_address(9) <= OCB_A09;
2497  vme_address(10) <= OCB_A10;
2498  vme_address(11) <= OCB_A11;
2499  vme_address(12) <= OCB_A12;
2500  vme_address(13) <= OCB_A13;
2501  vme_address(14) <= OCB_A14;
2502  vme_address(15) <= OCB_A15;
2503  vme_address(16) <= OCB_A16;
2504  vme_address(17) <= OCB_A17;
2505  vme_address(18) <= OCB_A18;
2506  vme_address(19) <= OCB_A19;
2507  vme_address(20) <= OCB_A20;
2508  vme_address(21) <= OCB_A21;
2509  vme_address(22) <= OCB_A22;
2510  vme_address(23) <= OCB_A23;
2511 
2512  ------------------------------------------------------------------------------
2513  -- VME interface component used in BSPT FPGA (Ian's vme_interface)
2514  ------------------------------------------------------------------------------
2515  CMX_BASE_VMEIF_BSPT : CMX_BASE_VME_BSPT
2516  port map (
2517  ----------------------------------------------------------------------------
2518  -- inputs
2519  ----------------------------------------------------------------------------
2520  clk40 => buf_clk40 ,
2521  geoadd_0 => OCB_GEO_ADRS_0 ,
2522  n_ds0_int => OCB_DS_B,
2523  n_write => OCB_WRITE_B ,
2524  -- vme_address
2525  vme_address => vme_address,
2526  ----------------------------------------------------------------------------
2527  -- outputs
2528  ----------------------------------------------------------------------------
2529  board_ds => ds, -- board_ds output from VME (Ian model)
2530  brdsel_n => ncs -- brdsel_n output from VME (Ian model)
2531  );
2532 
2533 
2534  vme_main_hub_inst: entity work.vme_main_hub
2535  port map (
2536  data_vme => OCB_D,
2537  data_vme_from_below => data_vme_up_top,
2538  bus_drive_from_below => bus_drive_up_top ,
2539  data_vme_going_below => data_vme_going_below );
2540 
2541 
2542  vme_local_switch_inst: entity work.vme_local_switch
2543  port map (
2544  data_vme_up => data_vme_up_top,
2545  data_vme_from_below => data_vme_from_below_top ,
2546  bus_drive_up => bus_drive_up_top ,
2547  bus_drive_from_below => bus_drive_from_below_top );
2548 
2549  CMX_version_inst: entity work.CMX_version
2550  port map (
2551  clk40 => buf_clk40 ,
2552  ncs => ncs,
2553  rd_nwr => OCB_WRITE_B ,
2554  ds => ds,
2555  addr_vme => vme_address(16 downto 1),
2556  data_vme_out => data_vme_from_below_top(1605),
2557  bus_drive => bus_drive_from_below_top (1605));
2558 
2559 
2560  sys_monitor_inst: entity work.sys_monitor
2561  generic map (
2562  ADDR_REG_RO_SYSMON_DATA_BLOCK => ADDR_REG_RO_SYSMON_DATA_BLOCK)
2563  port map (
2564  clk => buf_clk40 ,
2565  BF_SYSMON_01_P => BF_SYSMON_01_P,
2566  BF_SYSMON_01_N => BF_SYSMON_01_N,
2567  BF_SYSMON_03_P => BF_SYSMON_03_P,
2568  BF_SYSMON_03_N => BF_SYSMON_03_N,
2569  BF_SYSMON_04_P => BF_SYSMON_04_P,
2570  BF_SYSMON_04_N => BF_SYSMON_04_N,
2571  BF_SYSMON_07_P => BF_SYSMON_07_P,
2572  BF_SYSMON_07_N => BF_SYSMON_07_N,
2573  BF_SYSMON_08_P => BF_SYSMON_08_P,
2574  BF_SYSMON_08_N => BF_SYSMON_08_N,
2575  BF_SYSMON_09_P => BF_SYSMON_09_P,
2576  BF_SYSMON_09_N => BF_SYSMON_09_N,
2577  BF_SYSMON_10_P => BF_SYSMON_10_P,
2578  BF_SYSMON_10_N => BF_SYSMON_10_N,
2579  BF_SYSMON_11_P => BF_SYSMON_11_P,
2580  BF_SYSMON_11_N => BF_SYSMON_11_N,
2581  BF_SYSMON_12_P => BF_SYSMON_12_P,
2582  BF_SYSMON_12_N => BF_SYSMON_12_N,
2583  BF_SYSMON_13_P => BF_SYSMON_13_P,
2584  BF_SYSMON_13_N => BF_SYSMON_13_N,
2585  BF_SYSMON_14_P => BF_SYSMON_14_P,
2586  BF_SYSMON_14_N => BF_SYSMON_14_N,
2587  BF_SYSMON_15_P => BF_SYSMON_15_P,
2588  BF_SYSMON_15_N => BF_SYSMON_15_N,
2589  ncs => ncs,
2590  rd_nwr => OCB_WRITE_B ,
2591  ds => ds,
2592  addr_vme => vme_address(16 downto 1),
2593  data_vme_in => data_vme_going_below ,
2594  data_vme_out => data_vme_from_below_top (1760),
2595  bus_drive => bus_drive_from_below_top (1760));
2596 
2597 
2598  process(buf_clk40)
2599  begin
2600  if rising_edge(buf_clk40) then
2601  if (read_detect_inreg_test='1' or write_detect_inreg_test='1') and read_detect_outreg_test='0' then
2602  test_rw_counter<=test_rw_counter+1;
2603  elsif read_detect_outreg_test='1' then
2604  test_rw_counter<=test_rw_counter-1;
2605  end if;
2606  end if;
2607  end process;
2608 
2609  data_to_vme_test_r<=std_logic_vector(test_rw_counter);
2610 
2611 
2612  vme_outreg_notri_test: entity work.vme_outreg_notri
2613  generic map (
2614  ia_vme => ADDR_REG_RO_test ,
2615  width => 16)
2616  port map (
2617  clk => buf_clk40 ,
2618  ncs => ncs,
2619  rd_nwr => OCB_WRITE_B ,
2620  ds => ds,
2621  addr_vme => vme_address(16 downto 1),
2622  data_vme => data_vme_from_below_top(1600),
2623  bus_drive => bus_drive_from_below_top (1600),
2624  data_to_vme => data_to_vme_test_r ,
2625  read_detect => read_detect_outreg_test);
2626 
2627  --vme_outreg_test: vme_outreg
2628  -- generic map (
2629  -- ia_vme => ADDR_REG_RO_test,
2630  -- width => 16)
2631  -- port map (
2632  -- clk => buf_clk40,
2633  -- addr_vme => vme_address(16 downto 1),
2634  -- ncs => ncs,
2635  -- rd_nwr => OCB_WRITE_B,
2636  -- ds => ds,
2637  -- data_to_vme => data_to_vme_test_r,
2638  -- read_detect => read_detect_outreg_test,
2639  -- data_vme => OCB_D);
2640 
2641 
2642  vme_inreg_notri_test: entity work.vme_inreg_notri
2643  generic map (
2644  ia_vme => ADDR_REG_RW_test ,
2645  width => 16)
2646  port map (
2647  clk => buf_clk40 ,
2648  ncs => ncs,
2649  rd_nwr => OCB_WRITE_B ,
2650  ds => ds,
2651  addr_vme => vme_address(16 downto 1),
2652  data_vme_in => data_vme_going_below ,
2653  data_vme_out => data_vme_from_below_top (1601),
2654  bus_drive => bus_drive_from_below_top (1601),
2655  data_from_vme => data_from_vme_test_rw ,
2656  data_to_vme => data_to_vme_test_rw ,
2657  read_detect => read_detect_inreg_test,
2658  write_detect => write_detect_inreg_test );
2659 
2660  --vme_inreg_test: vme_inreg
2661  -- generic map (
2662  -- ia_vme => ADDR_REG_RW_test,
2663  -- width => 16)
2664  -- port map (
2665  -- clk => buf_clk40,
2666  -- ncs => ncs,
2667  -- rd_nwr => OCB_WRITE_B,
2668  -- ds => ds,
2669  -- data_from_vme => data_from_vme_test_rw,
2670  -- data_to_vme => data_to_vme_test_rw,
2671  -- addr_vme => vme_address(16 downto 1),
2672  -- read_detect => read_detect_inreg_test,
2673  -- write_detect => write_detect_inreg_test,
2674  -- data_vme => OCB_D);
2675  --
2676  data_to_vme_test_rw<=(data_from_vme_test_rw or data_to_vme_test_r);
2677 
2678 
2679  --chipscope_ila_CMX_top_inputmodclk_inst: chipscope_ila_CMX_top_inputmodclk
2680  -- port map (
2681  -- CONTROL => CONTROL0,
2682  -- CLK => buf_clk40,
2683  -- DATA => DATA_chipscope_ila_CMX_top_inputmodclk,
2684  -- TRIG0 => TRIG0_chipscope_ila_CMX_top_inputmodclk);
2685  --
2686  --
2687  --TRIG0_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2688  --TRIG0_chipscope_ila_CMX_top_inputmodclk(33)<=start_playback;
2689  --TRIG0_chipscope_ila_CMX_top_inputmodclk(34)<='0';
2690  --TRIG0_chipscope_ila_CMX_top_inputmodclk(35)<=data_to_RTM(0);
2691  --
2692  --
2693  --DATA_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2694  --
2695  --gen_data_chipscope_ila: for ichannel in numactchan-1 downto 0 generate
2696  --
2697  -- TRIG0_chipscope_ila_CMX_top_inputmodclk(1+ichannel*2)<=PAR_ERROR(ichannel);
2698  -- TRIG0_chipscope_ila_CMX_top_inputmodclk(2+ichannel*2)<=counter_enable_inputmod_sig(ichannel);
2699  --
2700  -- DATA_chipscope_ila_CMX_top_inputmodclk(1+ichannel*98)<=PAR_ERROR(ichannel);
2701  -- DATA_chipscope_ila_CMX_top_inputmodclk(2+ichannel*98)<=counter_enable_inputmod_sig(ichannel);
2702  -- DATA_chipscope_ila_CMX_top_inputmodclk(95+3+ichannel*98 downto 3+ichannel*98)<=DATA96(ichannel);
2703  --
2704  --end generate gen_data_chipscope_ila;
2705  --
2706  --DATA_chipscope_ila_CMX_top_inputmodclk(1630 downto 1569)<=(others=>'0');
2707  --DATA_chipscope_ila_CMX_top_inputmodclk(1734 downto 1631)<=data_to_RTM;
2708  --DATA_chipscope_ila_CMX_top_inputmodclk(1735)<=start_playback;
2709  --DATA_chipscope_ila_CMX_top_inputmodclk(2375 downto 1736)<=(others=>'0');
2710 
2711 
2712 
2713  CMX_delay_generator_inst: CMX_delay_generator
2714  generic map (
2715  start_address => ADDR_REG_RW_IDELAY_BACKPLANE )
2716  port map (
2717  clk40 => buf_clk40 ,
2718  ncs => ncs,
2719  rd_nwr => OCB_WRITE_B ,
2720  ds => ds,
2721  addr_vme => vme_address(16 downto 1),
2722  data_vme_in => data_vme_going_below ,
2723  data_vme_out => data_vme_from_below_top (1602),
2724  bus_drive => bus_drive_from_below_top (1602),
2725  del_register => del_register,
2726  upload_delays => upload_delays);
2727 
2728  --upload_delays<='0';
2729  --del_register<=(others=>(others=>(others=>'0')));
2730 
2731  BCID_counter_inst: BCID_counter
2732  port map (
2733  reset => bc_reset_synced ,
2734  clk_40 => buf_clk40,
2735  BCID_out => BCID_counter_sig ,
2736  ncs => ncs,
2737  rd_nwr => OCB_WRITE_B ,
2738  ds => ds,
2739  addr_vme => vme_address(16 downto 1),
2740  data_vme_in => data_vme_going_below ,
2741  data_vme_out => data_vme_from_below_top (1639),
2742  bus_drive => bus_drive_from_below_top (1639));
2743 
2744 
2745 
2746  process(buf_clk40)
2747  begin
2748  if rising_edge(buf_clk40) then
2749  start_playback<=start_playback_r1;
2750  start_playback_r1<=BF_TO_FROM_BSPT_0;
2751  end if;
2752  end process;
2753 
2754  CMX_input_inst: CMX_input_module
2755  port map (
2756  P => P,
2757  buf_clk40 => buf_clk40,
2758  buf_clk40_m180o => buf_clk40_m180o,
2759  buf_clk200 => buf_clk200,
2760  pll_locked => pll_locked,
2761  ODATA => DATA96,
2762  ODATA_first_half => ODATA_first_half ,
2763  --ODATA_WORD0 => open,
2764  PAR_ERROR_total => par_err(0),
2765  counter_enable_out => counter_enable_inputmod_sig ,
2766  counter_values => counter_values ,
2767  del_register => del_register,
2768  upload_delays => upload_delays,
2769  quiet => quiet,
2770  start_playback => start_playback ,
2771  spy_write_inhibit => spy_write_inhibit ,
2772  ncs => ncs,
2773  rd_nwr => OCB_WRITE_B,
2774  ds => ds,
2775  addr_vme => vme_address(16 downto 1),
2776  data_vme_in => data_vme_going_below ,
2777  data_vme_out => data_vme_from_below_top (1603),
2778  bus_drive => bus_drive_from_below_top (1603));
2779 
2780  par_err(1)<='0';
2781 
2782  vme_inreg_async_REG_RW_QUIET_FORCE : vme_inreg_notri_async
2783  generic map (
2784  ia_vme => ADDR_REG_RW_QUIET_FORCE ,
2785  width => 16)
2786  port map (
2787  ncs => ncs,
2788  rd_nwr => OCB_WRITE_B,
2789  ds => ds,
2790  addr_vme => vme_address(16 downto 1),
2791  data_vme_in => data_vme_going_below,
2792  data_vme_out => data_vme_from_below_top(1630),
2793  bus_drive => bus_drive_from_below_top (1630),
2794  data_from_vme => data_from_vme_REG_RW_QUIET_FORCE,
2795  data_to_vme => data_to_vme_REG_RW_QUIET_FORCE);
2796 
2797  data_to_vme_REG_RW_QUIET_FORCE<=data_from_vme_REG_RW_QUIET_FORCE;
2798  quiet<=data_from_vme_REG_RW_QUIET_FORCE(1);
2799  force<=data_from_vme_REG_RW_QUIET_FORCE(0);
2800 
2801  CMX_Memory_spy_inhibit_inst: entity work.CMX_Memory_spy_inhibit
2802  port map (
2803  spy_write_inhibit => spy_write_inhibit ,
2804  buf_clk40 => buf_clk40,
2805  ncs => ncs,
2806  rd_nwr => OCB_WRITE_B,
2807  ds => ds,
2808  addr_vme => vme_address(16 downto 1),
2809  data_vme_in => data_vme_going_below,
2810  data_vme_out => data_vme_from_below_top(1761),
2811  bus_drive => bus_drive_from_below_top (1761));
2812 
2813 
2814  --no decoder in the sense of jet/cp sense
2815  --zero out the bus slot that is not used in this flavor
2816  data_vme_from_below_top(1638)<=(others=>'0');
2817  bus_drive_from_below_top(1638)<='0';
2818  gen_data_vme_bus_drive_zeros: for i in 0 to 1599 generate
2819  data_vme_from_below_top(i)<=(others=>'0');
2820  bus_drive_from_below_top(i)<='0';
2821  end generate gen_data_vme_bus_drive_zeros;
2822 
2823  CMX_Sum_Et_inst: entity work.CMX_Sum_Et
2824  port map (
2825  CLK => buf_clk40,
2826  ENERGY_REMOTE => ENERGY_REMOTE,
2827  CTP_CABLE_0 => open,
2828  CTP_CABLE_1 => open,
2829  -- thresholds
2830  MISS_E_THR => MISS_E_THR,
2831  MISS_E_RES_THR => MISS_E_RES_THR,
2832  SUM_ET_THR => SUM_ET_THR,
2833  SUM_ET_RES_THR => SUM_ET_RES_THR,
2834  XS_T2_A2 => XS_T2_A2,
2835  -- parameters
2836  T_MISS_E_MIN => T_MISS_E_MIN,
2837  T_MISS_E_MAX => T_MISS_E_MAX,
2838  T_SUM_E_MIN => T_SUM_E_MIN,
2839  T_SUM_E_MAX => T_SUM_E_MAX,
2840  XS_B2 => XS_B2,
2841  ov_all_out => open,
2842  sums_all_out => open,
2843  BACKPLANE_DATA_IN => BACKPLANE_DATA_IN ,
2844  LOCAL_CABLE_OUT => LOCAL_CABLE_OUT,
2845  BCID_in => BCID_counter_sig ,
2846  BCID_delayed => BCID_delayed_decoder ,
2847  counter_inhibit => counter_inhibit,
2848  counter_reset => counter_reset,
2849  par_err => par_err ,
2850  force => force,
2851  ncs => ncs,
2852  rd_nwr => OCB_WRITE_B ,
2853  ds => ds,
2854  addr_vme => vme_address(16 downto 1),
2855  data_vme_in => data_vme_going_below ,
2856  data_vme_out => data_vme_from_below_top (1606),
2857  bus_drive => bus_drive_from_below_top (1606));
2858 
2859 
2860 -- ===========================================================================================
2861 --
2862 -- MISS_E_THR
2863 --
2864 -- ===========================================================================================
2865 
2866  gen_REG_RW_MISS_E_THR_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
2867 
2868  vme_inreg_notri_async_REG_RW_MISS_E_THR_BLOCK: entity work.vme_inreg_notri_async
2869  generic map (
2870  ia_vme => ADDR_REG_RW_MISS_E_THR_BLOCK+2*i_thr,
2871  width => 16)
2872  port map (
2873  ncs => ncs,
2874  rd_nwr => OCB_WRITE_B,
2875  ds => ds,
2876  addr_vme => vme_address(16 downto 1),
2877  data_vme_in => data_vme_going_below,
2878  data_vme_out => data_vme_from_below_top (1640+i_thr),
2879  bus_drive => bus_drive_from_below_top (1640+i_thr),
2880  data_from_vme => data_from_vme_REG_RW_MISS_E_THR_BLOCK(i_thr),
2881  data_to_vme => data_to_vme_REG_RW_MISS_E_THR_BLOCK(i_thr));
2882 
2883  data_to_vme_REG_RW_MISS_E_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_MISS_E_THR_BLOCK(i_thr);
2884 
2885  end generate gen_REG_RW_MISS_E_THR_BLOCK;
2886 
2887  gen_MISS_E_THR: for i_thr in 0 to num_thresholds-1 generate
2888  MISS_E_THR(i_thr)<= unsigned(slv_MISS_E_THR(i_thr));
2889  slv_MISS_E_THR(i_thr)(15 downto 0) <= data_from_vme_REG_RW_MISS_E_THR_BLOCK(2*i_thr)(15 downto 0);
2890  slv_MISS_E_THR(i_thr)(30 downto 16) <= data_from_vme_REG_RW_MISS_E_THR_BLOCK(2*i_thr+1)(14 downto 0);
2891  end generate gen_MISS_E_THR;
2892 
2893 
2894 -- ===========================================================================================
2895 --
2896 -- MISS_E_RES_THR
2897 --
2898 -- ===========================================================================================
2899 
2900  gen_REG_RW_MISS_E_RES_THR_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
2901 
2902  vme_inreg_notri_async_REG_RW_MISS_E_RES_THR_BLOCK: entity work.vme_inreg_notri_async
2903  generic map (
2904  ia_vme => ADDR_REG_RW_MISS_E_RES_THR_BLOCK+2*i_thr,
2905  width => 16)
2906  port map (
2907  ncs => ncs,
2908  rd_nwr => OCB_WRITE_B,
2909  ds => ds,
2910  addr_vme => vme_address(16 downto 1),
2911  data_vme_in => data_vme_going_below,
2912  data_vme_out => data_vme_from_below_top (1640+i_thr+16),
2913  bus_drive => bus_drive_from_below_top (1640+i_thr+16),
2914  data_from_vme => data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK(i_thr),
2915  data_to_vme => data_to_vme_REG_RW_MISS_E_RES_THR_BLOCK(i_thr));
2916 
2917  data_to_vme_REG_RW_MISS_E_RES_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK(i_thr);
2918 
2919  end generate gen_REG_RW_MISS_E_RES_THR_BLOCK;
2920 
2921  gen_MISS_E_RES_THR: for i_thr in 0 to num_thresholds-1 generate
2922  MISS_E_RES_THR(i_thr)<=unsigned(slv_MISS_E_RES_THR(i_thr));
2923  slv_MISS_E_RES_THR(i_thr)(15 downto 0) <= data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK(2*i_thr)(15 downto 0);
2924  slv_MISS_E_RES_THR(i_thr)(30 downto 16) <= data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK(2*i_thr+1)(14 downto 0);
2925  end generate gen_MISS_E_RES_THR;
2926 
2927 -- ===========================================================================================
2928 --
2929 -- SUM_ET_THR
2930 --
2931 -- ===========================================================================================
2932 
2933  gen_REG_RW_SUM_ET_THR_BLOCK: for i_thr in 0 to num_thresholds-1 generate
2934 
2935  vme_inreg_notri_async_REG_RW_SUM_ET_THR_BLOCK: entity work.vme_inreg_notri_async
2936  generic map (
2937  ia_vme => ADDR_REG_RW_SUM_ET_THR_BLOCK+2*i_thr,
2938  width => 16)
2939  port map (
2940  ncs => ncs,
2941  rd_nwr => OCB_WRITE_B,
2942  ds => ds,
2943  addr_vme => vme_address(16 downto 1),
2944  data_vme_in => data_vme_going_below,
2945  data_vme_out => data_vme_from_below_top (1640+i_thr+16+16),
2946  bus_drive => bus_drive_from_below_top (1640+i_thr+16+16),
2947  data_from_vme => data_from_vme_REG_RW_SUM_ET_THR_BLOCK(i_thr),
2948  data_to_vme => data_to_vme_REG_RW_SUM_ET_THR_BLOCK(i_thr));
2949 
2950  data_to_vme_REG_RW_SUM_ET_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_SUM_ET_THR_BLOCK(i_thr);
2951  SUM_ET_THR(i_thr)<=unsigned(slv_SUM_ET_THR(i_thr));
2952  slv_SUM_ET_THR(i_thr) <= data_from_vme_REG_RW_SUM_ET_THR_BLOCK(i_thr)(14 downto 0);
2953 
2954  end generate gen_REG_RW_SUM_ET_THR_BLOCK;
2955 
2956 -- ===========================================================================================
2957 --
2958 -- SUM_ET_RES_THR
2959 --
2960 -- ===========================================================================================
2961 
2962 
2963  gen_REG_RW_SUM_ET_RES_THR_BLOCK: for i_thr in 0 to num_thresholds-1 generate
2964 
2965  vme_inreg_notri_async_REG_RW_SUM_ET_RES_THR_BLOCK: entity work.vme_inreg_notri_async
2966  generic map (
2967  ia_vme => ADDR_REG_RW_SUM_ET_RES_THR_BLOCK+2*i_thr,
2968  width => 16)
2969  port map (
2970  ncs => ncs,
2971  rd_nwr => OCB_WRITE_B,
2972  ds => ds,
2973  addr_vme => vme_address(16 downto 1),
2974  data_vme_in => data_vme_going_below,
2975  data_vme_out => data_vme_from_below_top (1640+i_thr+16+16+8),
2976  bus_drive => bus_drive_from_below_top (1640+i_thr+16+16+8),
2977  data_from_vme => data_from_vme_REG_RW_SUM_ET_RES_THR_BLOCK(i_thr),
2978  data_to_vme => data_to_vme_REG_RW_SUM_ET_RES_THR_BLOCK(i_thr));
2979 
2980  data_to_vme_REG_RW_SUM_ET_RES_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_SUM_ET_RES_THR_BLOCK(i_thr);
2981  SUM_ET_RES_THR(i_thr)<=unsigned(slv_SUM_ET_RES_THR(i_thr));
2982  slv_SUM_ET_RES_THR(i_thr) <= data_from_vme_REG_RW_SUM_ET_RES_THR_BLOCK(i_thr)(14 downto 0);
2983 
2984  end generate gen_REG_RW_SUM_ET_RES_THR_BLOCK;
2985 
2986 -- ===========================================================================================
2987 --
2988 -- XS_T2_A2
2989 --
2990 -- ===========================================================================================
2991 
2992  gen_REG_RW_XS_T2_A2_THR_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
2993 
2994  vme_inreg_notri_async_REG_RW_XS_T2_A2_THR_BLOCK: entity work.vme_inreg_notri_async
2995  generic map (
2996  ia_vme => ADDR_REG_RW_XS_T2_A2_THR_BLOCK+2*i_thr,
2997  width => 16)
2998  port map (
2999  ncs => ncs,
3000  rd_nwr => OCB_WRITE_B,
3001  ds => ds,
3002  addr_vme => vme_address(16 downto 1),
3003  data_vme_in => data_vme_going_below,
3004  data_vme_out => data_vme_from_below_top (1640+i_thr+16+16+8+8),
3005  bus_drive => bus_drive_from_below_top (1640+i_thr+16+16+8+8),
3006  data_from_vme => data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK(i_thr),
3007  data_to_vme => data_to_vme_REG_RW_XS_T2_A2_THR_BLOCK(i_thr));
3008 
3009  data_to_vme_REG_RW_XS_T2_A2_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK(i_thr);
3010 
3011  end generate gen_REG_RW_XS_T2_A2_THR_BLOCK;
3012 
3013  gen_XS_T2_A2_THR: for i_thr in 0 to num_thresholds-1 generate
3014  XS_T2_A2(i_thr)<=unsigned(slv_XS_T2_A2(i_thr));
3015  slv_XS_T2_A2(i_thr)(15 downto 0) <= data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK(2*i_thr)(15 downto 0);
3016  slv_XS_T2_A2(i_thr)(30 downto 16) <= data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK(2*i_thr+1)(14 downto 0);
3017  end generate gen_XS_T2_A2_THR;
3018 
3019 -- ===========================================================================================
3020 --
3021 -- T_MISS_E_MIN
3022 --
3023 -- ===========================================================================================
3024 
3025  gen_REG_RW_T_MISS_E_MIN_PARAM_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
3026 
3027  vme_inreg_notri_async_REG_RW_T_MISS_E_MIN_PARAM_BLOCK: entity work.vme_inreg_notri_async
3028  generic map (
3029  ia_vme => ADDR_REG_RW_T_MISS_E_MIN_PARAM_BLOCK+2*i_thr,
3030  width => 16)
3031  port map (
3032  ncs => ncs,
3033  rd_nwr => OCB_WRITE_B,
3034  ds => ds,
3035  addr_vme => vme_address(16 downto 1),
3036  data_vme_in => data_vme_going_below,
3037  data_vme_out => data_vme_from_below_top (1640+i_thr+16+16+8+8+16),
3038  bus_drive => bus_drive_from_below_top (1640+i_thr+16+16+8+8+16),
3039  data_from_vme => data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(i_thr),
3040  data_to_vme => data_to_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(i_thr));
3041 
3042  data_to_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(i_thr);
3043 
3044  end generate gen_REG_RW_T_MISS_E_MIN_PARAM_BLOCK;
3045 
3046  gen_T_MISS_E_MIN_PARAM: for i_thr in 0 to num_thresholds-1 generate
3047  T_MISS_E_MIN(i_thr)<=unsigned(slv_T_MISS_E_MIN(i_thr));
3048  slv_T_MISS_E_MIN(i_thr)(15 downto 0) <= data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(2*i_thr)(15 downto 0);
3049  slv_T_MISS_E_MIN(i_thr)(30 downto 16) <= data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(2*i_thr+1)(14 downto 0);
3050  end generate gen_T_MISS_E_MIN_PARAM;
3051 
3052 -- ===========================================================================================
3053 --
3054 -- T_MISS_E_MAX
3055 --
3056 -- ===========================================================================================
3057 
3058 
3059  gen_REG_RW_T_MISS_E_MAX_PARAM_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
3060 
3061  vme_inreg_notri_async_REG_RW_T_MISS_E_MAX_PARAM_BLOCK: entity work.vme_inreg_notri_async
3062  generic map (
3063  ia_vme => ADDR_REG_RW_T_MISS_E_MAX_PARAM_BLOCK+2*i_thr,
3064  width => 16)
3065  port map (
3066  ncs => ncs,
3067  rd_nwr => OCB_WRITE_B,
3068  ds => ds,
3069  addr_vme => vme_address(16 downto 1),
3070  data_vme_in => data_vme_going_below,
3071  data_vme_out => data_vme_from_below_top (1640+i_thr+16+16+8+8+16+16),
3072  bus_drive => bus_drive_from_below_top (1640+i_thr+16+16+8+8+16+16),
3073  data_from_vme => data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(i_thr),
3074  data_to_vme => data_to_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(i_thr));
3075 
3076  data_to_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(i_thr);
3077 
3078  end generate gen_REG_RW_T_MISS_E_MAX_PARAM_BLOCK;
3079 
3080  gen_T_MISS_E_MAX_PARAM: for i_thr in 0 to num_thresholds-1 generate
3081  T_MISS_E_MAX(i_thr)<=unsigned(slv_T_MISS_E_MAX(i_thr));
3082  slv_T_MISS_E_MAX(i_thr)(15 downto 0) <= data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(2*i_thr)(15 downto 0);
3083  slv_T_MISS_E_MAX(i_thr)(30 downto 16) <= data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(2*i_thr+1)(14 downto 0);
3084  end generate gen_T_MISS_E_MAX_PARAM;
3085 
3086 -- ===========================================================================================
3087 --
3088 -- T_SUM_E_MIN
3089 --
3090 -- ===========================================================================================
3091 
3092 
3093  gen_REG_RW_T_SUM_E_MIN_PARAM_BLOCK: for i_thr in 0 to num_thresholds-1 generate
3094 
3095  vme_inreg_notri_async_REG_RW_T_SUM_E_MIN_PARAM_BLOCK: entity work.vme_inreg_notri_async
3096  generic map (
3097  ia_vme => ADDR_REG_RW_T_SUM_E_MIN_PARAM_BLOCK+2*i_thr,
3098  width => 16)
3099  port map (
3100  ncs => ncs,
3101  rd_nwr => OCB_WRITE_B,
3102  ds => ds,
3103  addr_vme => vme_address(16 downto 1),
3104  data_vme_in => data_vme_going_below,
3105  data_vme_out => data_vme_from_below_top (1640+i_thr+16+16+8+8+16+16+16),
3106  bus_drive => bus_drive_from_below_top (1640+i_thr+16+16+8+8+16+16+16),
3107  data_from_vme => data_from_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK(i_thr),
3108  data_to_vme => data_to_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK(i_thr));
3109 
3110  data_to_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK(i_thr);
3111 
3112  T_SUM_E_MIN(i_thr)<=unsigned(slv_T_SUM_E_MIN(i_thr));
3113  slv_T_SUM_E_MIN(i_thr) <= data_from_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK(i_thr)(14 downto 0);
3114 
3115  end generate gen_REG_RW_T_SUM_E_MIN_PARAM_BLOCK;
3116 
3117 -- ===========================================================================================
3118 --
3119 -- T_SUM_E_MAX
3120 --
3121 -- ===========================================================================================
3122 
3123 
3124  gen_REG_RW_T_SUM_E_MAX_PARAM_BLOCK: for i_thr in 0 to num_thresholds-1 generate
3125 
3126  vme_inreg_notri_async_REG_RW_T_SUM_E_MAX_PARAM_BLOCK: entity work.vme_inreg_notri_async
3127  generic map (
3128  ia_vme => ADDR_REG_RW_T_SUM_E_MAX_PARAM_BLOCK+2*i_thr,
3129  width => 16)
3130  port map (
3131  ncs => ncs,
3132  rd_nwr => OCB_WRITE_B,
3133  ds => ds,
3134  addr_vme => vme_address(16 downto 1),
3135  data_vme_in => data_vme_going_below,
3136  data_vme_out => data_vme_from_below_top (1640+i_thr+16+16+8+8+16+16+16+8),
3137  bus_drive => bus_drive_from_below_top (1640+i_thr+16+16+8+8+16+16+16+8),
3138  data_from_vme => data_from_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK(i_thr),
3139  data_to_vme => data_to_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK(i_thr));
3140 
3141  data_to_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK(i_thr);
3142  T_SUM_E_MAX(i_thr)<=unsigned(slv_T_SUM_E_MAX(i_thr));
3143  slv_T_SUM_E_MAX(i_thr) <= data_from_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK(i_thr)(14 downto 0);
3144 
3145  end generate gen_REG_RW_T_SUM_E_MAX_PARAM_BLOCK;
3146 
3147 -- ===========================================================================================
3148 --
3149 -- XS_B2
3150 --
3151 -- ===========================================================================================
3152 
3153 
3154  gen_REG_RW_XS_B2_PARAM_BLOCK: for i_thr in 0 to num_thresholds-1 generate
3155 
3156  vme_inreg_notri_async_REG_RW_XS_B2_PARAM_BLOCK: entity work.vme_inreg_notri_async
3157  generic map (
3158  ia_vme => ADDR_REG_RW_XS_B2_PARAM_BLOCK+2*i_thr,
3159  width => 16)
3160  port map (
3161  ncs => ncs,
3162  rd_nwr => OCB_WRITE_B,
3163  ds => ds,
3164  addr_vme => vme_address(16 downto 1),
3165  data_vme_in => data_vme_going_below,
3166  data_vme_out => data_vme_from_below_top (1640+i_thr+16+16+8+8+16+16+16+8+8),
3167  bus_drive => bus_drive_from_below_top (1640+i_thr+16+16+8+8+16+16+16+8+8),
3168  data_from_vme => data_from_vme_REG_RW_XS_B2_PARAM_BLOCK(i_thr),
3169  data_to_vme => data_to_vme_REG_RW_XS_B2_PARAM_BLOCK(i_thr));
3170 
3171  data_to_vme_REG_RW_XS_B2_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_XS_B2_PARAM_BLOCK(i_thr);
3172  XS_B2(i_thr)<=unsigned(slv_XS_B2(i_thr));
3173  slv_XS_B2(i_thr) <= data_from_vme_REG_RW_XS_B2_PARAM_BLOCK(i_thr)(14 downto 0);
3174 
3175  end generate gen_REG_RW_XS_B2_PARAM_BLOCK;
3176 
3177 -- ===========================================================================================
3178 --
3179 -- MARKER LINE
3180 --
3181 -- ===========================================================================================
3182 
3183 
3184  gen_ET_data : for ch in numactchan-1 downto 0 generate
3185  BACKPLANE_DATA_IN(ch)(13 downto 0)<=DATA96(ch)(13 downto 0);
3186  BACKPLANE_DATA_IN(ch)(27 downto 14)<=DATA96(ch)(37 downto 24);
3187  BACKPLANE_DATA_IN(ch)(41 downto 28)<=DATA96(ch)(61 downto 48);
3188  end generate gen_ET_data;
3189 
3190  ENERGY_REMOTE<=(25=>'1', 51=>'1', 77=>'1',103=>'1', others=>'0');
3191 
3192 
3193  data_to_RTM<=LOCAL_CABLE_OUT;
3194 
3195  ddr_data_out_RTM1<=ddr_data_out_RTM(0);
3196  ddr_data_out_RTM2<=ddr_data_out_RTM(1);
3197 
3198 
3199  CMX_crate_cable_output_module_inst: entity work.CMX_crate_cable_output_module
3200  port map (
3201  data => data_to_RTM,
3202  ddr_data_out => ddr_data_out_RTM ,
3203  buf_clk40 => buf_clk40,
3204  buf_clk40_center => buf_clk40_center ,
3205  pll_locked => pll_locked,
3206  start_playback => start_playback,
3207  spy_write_inhibit => spy_write_inhibit ,
3208  ncs => ncs,
3209  rd_nwr => OCB_WRITE_B,
3210  ds => ds,
3211  addr_vme => vme_address(16 downto 1),
3212  data_vme_in => data_vme_going_below,
3213  data_vme_out => data_vme_from_below_top (1631),
3214  bus_drive => bus_drive_from_below_top(1631));
3215 
3216  --no RTM cable input - zero the local bus that would be connected to that module
3217  data_vme_from_below_top(1636)<=(others=>'0');
3218  bus_drive_from_below_top(1636)<='0';
3219 
3220 
3221  --CMX_cable_clocked_80Mbps_output_module_RTM1: CMX_cable_clocked_80Mbps_output_module
3222  -- generic map (
3223  -- numbits_in_cable_connector => numbits_in_RTM_connector)
3224  -- port map (
3225  -- data => data_to_RTM1,
3226  -- ddr_data_out => ddr_data_out_RTM1,
3227  -- buf_clk40 => buf_clk40,
3228  -- buf_clk40_center => buf_clk40_center,
3229  -- buf_clk200 => buf_clk200,
3230  -- pll_locked => pll_locked,
3231  -- del_array => del_array_RTM,
3232  -- upload_delays => '0');
3233  --
3234  --CMX_cable_clocked_80Mbps_output_module_RTM2: CMX_cable_clocked_80Mbps_output_module
3235  -- generic map (
3236  -- numbits_in_cable_connector => numbits_in_RTM_connector)
3237  -- port map (
3238  -- data => data_to_RTM2,
3239  -- ddr_data_out => ddr_data_out_RTM2,
3240  -- buf_clk40 => buf_clk40,
3241  -- buf_clk40_center => buf_clk40_center,
3242  -- buf_clk200 => buf_clk200,
3243  -- pll_locked => pll_locked,
3244  -- del_array => del_array_RTM,
3245  -- upload_delays => '0');
3246 
3247  --del_array_RTM<=(others=>(others=>'0'));
3248 
3249 
3250  --CMX_system_cable_input_module_inst: entity work.CMX_system_cable_input_module
3251  -- port map (
3252  -- data => data_from_RTM,
3253  -- parity_error => open,
3254  -- ddr_data_in => sig_arr_RTM,
3255  -- buf_clk40 => buf_clk40,
3256  -- buf_clk40_ds2 => buf_clk40_ds2,
3257  -- pll_locked => pll_locked,
3258  -- pll_locked_ds2 => pll_locked_ds2,
3259  -- start_playback => start_playback,
3260  -- spy_write_inhibit => spy_write_inhibit,
3261  -- ncs => ncs,
3262  -- rd_nwr => OCB_WRITE_B,
3263  -- ds => ds,
3264  -- addr_vme => vme_address(16 downto 1),
3265  -- data_vme => OCB_D);
3266 
3267  --chipscope_ila_LVDS_TX_CTP_RTM_inst: chipscope_ila_LVDS_TX_CTP_RTM
3268  -- port map (
3269  -- CONTROL => CONTROL1,
3270  -- CLK => buf_clk40,
3271  -- DATA(31 downto 0) => sdr_data_out,
3272  -- DATA(63 downto 32) => (others=>'0'),
3273  -- DATA(115 downto 64) => data_RTM,
3274  -- DATA(116) => '0',
3275  -- DATA(117) => '0',
3276  -- TRIG0(0) => '0',
3277  -- TRIG0(1) => '0'
3278  -- );
3279 
3280 
3281 
3282 
3283  CMX_clock_manager_inst: CMX_clock_manager
3284  port map (
3285  I_DS1 => CLK_40MHz08_DSKW_1_BF_LOGIC_DIR,
3286  IB_DS1 => CLK_40MHz08_DSKW_1_BF_LOGIC_CMP,
3287  buf_clk40 => buf_clk40,
3288  buf_clk40_90o => buf_clk40_center,
3289  buf_clk40_m180o => buf_clk40_m180o,
3290  buf_clk40_m90o => open,
3291  buf_clk320 => buf_clk320,
3292  buf_clk160 => buf_clk160,
3293  buf_clk200 => buf_clk200,
3294  pll_locked => pll_locked,
3295  I_DS2 => CLK_40MHz08_DSKW_2_BF_LOGIC_DIR,
3296  IB_DS2 => CLK_40MHz08_DSKW_2_BF_LOGIC_CMP,
3297  buf_clk40_ds2 => buf_clk40_ds2,
3298  pll_locked_ds2 => pll_locked_ds2,
3299  ncs => ncs,
3300  rd_nwr => OCB_WRITE_B ,
3301  ds => ds,
3302  addr_vme => vme_address(16 downto 1),
3303  data_vme_in => data_vme_going_below ,
3304  data_vme_out => data_vme_from_below_top (1762),
3305  bus_drive => bus_drive_from_below_top (1762));
3306 
3307 
3308 
3309  Topo_Data_TX_inst: Topo_Data_TX
3310  port map (
3311  MGTREFCLK_PAD_N_IN => MGTREFCLK_PAD_N_IN,
3312  MGTREFCLK_PAD_P_IN => MGTREFCLK_PAD_P_IN,
3313  GTXTXRESET_IN => GTXTXRESET_IN,
3314  GTXRXRESET_IN => GTXRXRESET_IN,
3315  GTX_TX_READY_OUT => GTX_TX_READY_OUT ,
3316  GTX_RX_READY_OUT => GTX_RX_READY_OUT ,
3317  RXN_IN => RXN_IN,
3318  RXP_IN => RXP_IN,
3319  TXN_OUT => TXN_OUT,
3320  TXP_OUT => TXP_OUT,
3321  clk40 => buf_clk40,
3322  clk320 => buf_clk320,
3323  pll_locked => pll_locked,
3324  send_align => send_align,
3325  BCID => bcid_adj,
3326  indata => indata_Topo_TX,
3327  ext_trigger => '0',
3328  ncs => ncs,
3329  rd_nwr => OCB_WRITE_B,
3330  ds => ds,
3331  addr_vme => vme_address(16 downto 1),
3332  data_vme_in => data_vme_going_below,
3333  data_vme_out => data_vme_from_below_top(1604),
3334  bus_drive => bus_drive_from_below_top (1604)
3335  );
3336 
3337 
3338  CMX_SumET_Topo_Encoder_inst: entity work.CMX_SumET_Topo_Encoder
3339  port map (
3340  local_data => LOCAL_CABLE_OUT ,
3341  send_align_out => send_align,
3342  Data_out => indata_Topo_TX ,
3343  bcid_in => BCID_delayed_decoder ,
3344  bcid_adj => bcid_adj,
3345  clk => buf_clk40
3346  );
3347 
3348  vme_inreg_REG_RW_TOPOTR_GTX_RESET: vme_inreg_notri_async
3349  generic map (
3350  ia_vme => ADDR_REG_RW_TOPOTR_GTX_RESET ,
3351  width => 16)
3352  port map (
3353  ncs => ncs,
3354  rd_nwr => OCB_WRITE_B,
3355  ds => ds,
3356  addr_vme => vme_address(16 downto 1),
3357  data_vme_in => data_vme_going_below,
3358  data_vme_out => data_vme_from_below_top(1634),
3359  bus_drive => bus_drive_from_below_top (1634),
3360  data_from_vme => data_from_vme_REG_RW_TOPOTR_GTX_RESET,
3361  data_to_vme => data_to_vme_REG_RW_TOPOTR_GTX_RESET
3362  );
3363 
3364  GTXTXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(1);
3365  GTXRXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(0);
3366 
3367  data_to_vme_REG_RW_TOPOTR_GTX_RESET<=data_from_vme_REG_RW_TOPOTR_GTX_RESET;
3368 
3369 
3370  vme_outreg_async_REG_RO_TOPOTR_GTX_STATUS : vme_outreg_notri_async
3371  generic map (
3372  ia_vme => ADDR_REG_RO_TOPOTR_GTX_STATUS ,
3373  width => 16)
3374  port map (
3375  ncs => ncs,
3376  rd_nwr => OCB_WRITE_B,
3377  ds => ds,
3378  addr_vme => vme_address(16 downto 1),
3379  data_vme => data_vme_from_below_top(1635),
3380  bus_drive => bus_drive_from_below_top (1635),
3381  data_to_vme => data_to_vme_REG_RO_TOPOTR_GTX_STATUS );
3382 
3383  data_to_vme_REG_RO_TOPOTR_GTX_STATUS(1)<=GTX_TX_READY_OUT;
3384  data_to_vme_REG_RO_TOPOTR_GTX_STATUS(0)<=GTX_RX_READY_OUT;
3385 
3386  data_to_vme_REG_RO_TOPOTR_GTX_STATUS(15 downto 2)<=(others=>'0');
3387 
3388  -- sfp
3389 
3390 
3391  SFP_Data_TXRX_TX_SFP_DAQ: SFP_Data_TXRX
3392  generic map(
3393  direction => '1',
3394  clock_source => '1')
3395  port map (
3396  MGTREFCLK => MGTREFCLK_Q118 ,
3397  gtx_reset => gtx_reset_SFP_DAQ ,
3398  local_pll_lock_out => local_pll_lock_out_SFP_DAQ ,
3399  GTX_TX_READY_OUT => GTX_TX_READY_OUT_TX_SFP_DAQ ,
3400  GTX_RX_READY_OUT => GTX_RX_READY_OUT_TX_SFP_DAQ ,
3401  PLLLKDET_diag => PLLLKDET_diag_TX_SFP_DAQ ,
3402  local_gtx_reset_diag => local_gtx_reset_diag_TX_SFP_DAQ ,
3403  local_mmcm_reset_diag => local_mmcm_reset_diag_TX_SFP_DAQ ,
3404  GTXTEST_diag => GTXTEST_diag_TX_SFP_DAQ ,
3405  RXN_IN => RXN_IN_TX_SFP_DAQ ,
3406  RXP_IN => RXP_IN_TX_SFP_DAQ ,
3407  TXN_OUT => TXN_OUT_TX_SFP_DAQ,
3408  TXP_OUT => TXP_OUT_TX_SFP_DAQ,
3409  clk40_out => clk40_out_TX_SFP_DAQ,
3410  clk120_out => clk120_out_TX_SFP_DAQ,
3411  clk40_in => clk40_in_TX_SFP_DAQ,
3412  clk120_in => clk120_in_TX_SFP_DAQ,
3413  indata => indata_TX_SFP_DAQ ,
3414  odata => odata_TX_SFP_DAQ ,
3415  TXPREEMPHASIS_IN => TXPREEMPHASIS_IN_TX_SFP_DAQ ,
3416  TXPOSTEMPHASIS_IN => TXPOSTEMPHASIS_IN_TX_SFP_DAQ ,
3417  TXDIFFCTRL_IN => TXDIFFCTRL_IN_TX_SFP_DAQ ,
3418  RXEQMIX_IN => RXEQMIX_IN_TX_SFP_DAQ,
3419  DFECLKDLYADJ => DFECLKDLYADJ_TX_SFP_DAQ ,
3420  DFECLKDLYADJMON => DFECLKDLYADJMON_TX_SFP_DAQ ,
3421  DFEDLYOVRD => DFEDLYOVRD_TX_SFP_DAQ,
3422  DFEEYEDACMON => DFEEYEDACMON_TX_SFP_DAQ ,
3423  DFESENSCAL => DFESENSCAL_TX_SFP_DAQ,
3424  DFETAP1 => DFETAP1_TX_SFP_DAQ,
3425  DFETAP1MONITOR => DFETAP1MONITOR_TX_SFP_DAQ ,
3426  DFETAP2 => DFETAP2_TX_SFP_DAQ,
3427  DFETAP2MONITOR => DFETAP2MONITOR_TX_SFP_DAQ ,
3428  DFETAP3 => DFETAP3_TX_SFP_DAQ,
3429  DFETAP3MONITOR => DFETAP3MONITOR_TX_SFP_DAQ ,
3430  DFETAP4 => DFETAP4_TX_SFP_DAQ,
3431  DFETAP4MONITOR => DFETAP4MONITOR_TX_SFP_DAQ ,
3432  DFETAPOVRD => DFETAPOVRD_TX_SFP_DAQ);
3433 
3434 
3435  SFP_Data_TXRX_TX_SFP_ROI: SFP_Data_TXRX
3436  generic map(
3437  direction => '1',
3438  clock_source => '0')
3439  port map (
3440  MGTREFCLK => MGTREFCLK_Q118 ,
3441  gtx_reset => gtx_reset_SFP_ROI ,
3442  local_pll_lock_out => local_pll_lock_out_SFP_ROI ,
3443  GTX_TX_READY_OUT => GTX_TX_READY_OUT_TX_SFP_ROI ,
3444  GTX_RX_READY_OUT => GTX_RX_READY_OUT_TX_SFP_ROI ,
3445  PLLLKDET_diag => PLLLKDET_diag_TX_SFP_ROI ,
3446  local_gtx_reset_diag => local_gtx_reset_diag_TX_SFP_ROI ,
3447  local_mmcm_reset_diag => local_mmcm_reset_diag_TX_SFP_ROI ,
3448  GTXTEST_diag => GTXTEST_diag_TX_SFP_ROI ,
3449  RXN_IN => RXN_IN_TX_SFP_ROI ,
3450  RXP_IN => RXP_IN_TX_SFP_ROI ,
3451  TXN_OUT => TXN_OUT_TX_SFP_ROI,
3452  TXP_OUT => TXP_OUT_TX_SFP_ROI,
3453  clk40_out => clk40_out_TX_SFP_ROI,
3454  clk120_out => clk120_out_TX_SFP_ROI,
3455  clk40_in => clk40_in_TX_SFP_ROI,
3456  clk120_in => clk120_in_TX_SFP_ROI,
3457  indata => indata_TX_SFP_ROI ,
3458  odata => odata_TX_SFP_ROI ,
3459  TXPREEMPHASIS_IN => TXPREEMPHASIS_IN_TX_SFP_ROI ,
3460  TXPOSTEMPHASIS_IN => TXPOSTEMPHASIS_IN_TX_SFP_ROI ,
3461  TXDIFFCTRL_IN => TXDIFFCTRL_IN_TX_SFP_ROI ,
3462  RXEQMIX_IN => RXEQMIX_IN_TX_SFP_ROI,
3463  DFECLKDLYADJ => DFECLKDLYADJ_TX_SFP_ROI ,
3464  DFECLKDLYADJMON => DFECLKDLYADJMON_TX_SFP_ROI ,
3465  DFEDLYOVRD => DFEDLYOVRD_TX_SFP_ROI,
3466  DFEEYEDACMON => DFEEYEDACMON_TX_SFP_ROI ,
3467  DFESENSCAL => DFESENSCAL_TX_SFP_ROI,
3468  DFETAP1 => DFETAP1_TX_SFP_ROI,
3469  DFETAP1MONITOR => DFETAP1MONITOR_TX_SFP_ROI ,
3470  DFETAP2 => DFETAP2_TX_SFP_ROI,
3471  DFETAP2MONITOR => DFETAP2MONITOR_TX_SFP_ROI ,
3472  DFETAP3 => DFETAP3_TX_SFP_ROI,
3473  DFETAP3MONITOR => DFETAP3MONITOR_TX_SFP_ROI ,
3474  DFETAP4 => DFETAP4_TX_SFP_ROI,
3475  DFETAP4MONITOR => DFETAP4MONITOR_TX_SFP_ROI ,
3476  DFETAPOVRD => DFETAPOVRD_TX_SFP_ROI);
3477 
3478 -- glink interface
3479 
3480 
3481  glink: glink_interface
3482  port map (
3483  CLK_40MHz => clk40_in_TX_SFP_ROI, -- clk40MHz
3484  CLK_120MHz => clk120_in_TX_SFP_ROI , -- clk120MHz
3485  RST => reset_daq , --not pll_locked, --reset(0), -- reset
3486  DAQ_IN => daq_in, -- Input data (DAQ)
3487  ROI_IN => roi_in, -- Input data (ROI)
3488  DAQ_DAV => daq_dav, -- Control (DAQ)
3489  ROI_DAV => roi_dav, -- Control (ROI)
3490  DAQ_BYTE => daq_byte, -- Output Byte (DAQ)
3491  ROI_BYTE => roi_byte, -- Output Byte (ROI)
3492  DAQ_ENCODED_DIAG => daq_encoded_diag,
3493  daq_byte_out => daq_byte_out,
3494  byte_pos_out => byte_pos_out,
3495  word_sel_out => word_sel_out,
3496  readout_rst_out => readout_rst_out
3497 
3498 
3499 
3500  ); -- daq_encoded_DIAG
3501 
3502  MGT_118_clk0_ibufds_i : IBUFDS_GTXE1
3503  port map
3504  (
3505  O => MGTREFCLK_Q118,
3506  ODIV2 => open,
3507  CEB => '0',
3508  I => CLK_120MHz000_XTAL_1_BF_TRNCV_DIR,
3509  IB => CLK_120MHz000_XTAL_1_BF_TRNCV_CMP
3510  );
3511 
3512  BF_DAQ_DATA_OUT_DIR<=TXP_OUT_TX_SFP_DAQ;
3513  BF_DAQ_DATA_OUT_CMP<=TXN_OUT_TX_SFP_DAQ;
3514 
3515  BF_ROI_DATA_OUT_DIR<=TXP_OUT_TX_SFP_ROI;
3516  BF_ROI_DATA_OUT_CMP<=TXN_OUT_TX_SFP_ROI;
3517 
3518  clk40_in_TX_SFP_ROI<=clk40_out_TX_SFP_DAQ;
3519  clk120_in_TX_SFP_ROI<=clk120_out_TX_SFP_DAQ;
3520 
3521  indata_TX_SFP_DAQ<=daq_byte; -- from GLINK emulator
3522  indata_TX_SFP_ROI<=roi_byte; -- from GLINK emulator;
3523 
3524 -- Reset control
3525 
3526  --vio_data_i : diagn_module_vio
3527  -- port map(
3528  -- CONTROL => control1,
3529  -- ASYNC_OUT => reset);
3530 
3531 
3532  vme_inreg_async_REG_RW_DAQ_ROI_RESET : vme_inreg_notri_async
3533  generic map (
3534  ia_vme => ADDR_REG_RW_DAQ_ROI_RESET ,
3535  width => 16)
3536  port map (
3537  ncs => ncs,
3538  rd_nwr => OCB_WRITE_B,
3539  ds => ds,
3540  addr_vme => vme_address(16 downto 1),
3541  data_vme_in => data_vme_going_below,
3542  data_vme_out => data_vme_from_below_top(1629),
3543  bus_drive => bus_drive_from_below_top (1629),
3544  data_from_vme => data_from_vme_REG_RW_DAQ_ROI_RESET,
3545  data_to_vme => data_to_vme_REG_RW_DAQ_ROI_RESET);
3546 
3547  reset_daq<=data_from_vme_REG_RW_DAQ_ROI_RESET(0);
3548  data_to_vme_REG_RW_DAQ_ROI_RESET<=data_from_vme_REG_RW_DAQ_ROI_RESET;
3549 
3550  vme_inreg_async_REG_RW_DAQ_ROI_GTX_RESET : vme_inreg_notri_async
3551  generic map (
3552  ia_vme => ADDR_REG_RW_DAQ_ROI_GTX_RESET ,
3553  width => 16)
3554  port map (
3555  ncs => ncs,
3556  rd_nwr => OCB_WRITE_B,
3557  ds => ds,
3558  addr_vme => vme_address(16 downto 1),
3559  data_vme_in => data_vme_going_below,
3560  data_vme_out => data_vme_from_below_top(1633),
3561  bus_drive => bus_drive_from_below_top (1633),
3562  data_from_vme => data_from_vme_REG_RW_DAQ_ROI_GTX_RESET,
3563  data_to_vme => data_to_vme_REG_RW_DAQ_ROI_GTX_RESET);
3564 
3565  gtx_reset_SFP_DAQ<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(0);
3566  gtx_reset_SFP_ROI<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(1);
3567  data_to_vme_REG_RW_DAQ_ROI_GTX_RESET<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET;
3568 
3569 
3570  vme_outreg_async_REG_RO_DAQ_ROI_STATUS : vme_outreg_notri_async
3571  generic map (
3572  ia_vme => ADDR_REG_RO_DAQ_ROI_STATUS ,
3573  width => 16)
3574  port map (
3575  ncs => ncs,
3576  rd_nwr => OCB_WRITE_B,
3577  ds => ds,
3578  addr_vme => vme_address(16 downto 1),
3579  data_vme => data_vme_from_below_top(1632),
3580  bus_drive => bus_drive_from_below_top (1632),
3581  data_to_vme => data_to_vme_REG_RO_DAQ_ROI_STATUS );
3582 
3583  data_to_vme_REG_RO_DAQ_ROI_STATUS(0)<=local_pll_lock_out_SFP_DAQ;
3584  data_to_vme_REG_RO_DAQ_ROI_STATUS(1)<=GTX_TX_READY_OUT_TX_SFP_DAQ;
3585  data_to_vme_REG_RO_DAQ_ROI_STATUS(2)<=GTX_RX_READY_OUT_TX_SFP_DAQ;
3586  data_to_vme_REG_RO_DAQ_ROI_STATUS(3)<=PLLLKDET_diag_TX_SFP_DAQ;
3587  data_to_vme_REG_RO_DAQ_ROI_STATUS(4)<=local_pll_lock_out_SFP_ROI;
3588  data_to_vme_REG_RO_DAQ_ROI_STATUS(5)<=GTX_TX_READY_OUT_TX_SFP_ROI;
3589  data_to_vme_REG_RO_DAQ_ROI_STATUS(6)<=GTX_RX_READY_OUT_TX_SFP_ROI;
3590  data_to_vme_REG_RO_DAQ_ROI_STATUS(7)<=PLLLKDET_diag_TX_SFP_ROI;
3591  data_to_vme_REG_RO_DAQ_ROI_STATUS(8)<=readout_rst_out;
3592 
3593  data_to_vme_REG_RO_DAQ_ROI_STATUS(15 downto 9) <= (others=>'0');
3594 
3595 
3596  -- Chipscope analyzer
3597  --chipscope_icon_u2_c3_inst: chipscope_icon_u2_c3
3598  -- port map (
3599  -- CONTROL0 => CONTROL0,
3600  -- CONTROL1 => CONTROL1,
3601  -- CONTROL2 => CONTROL2
3602  -- );
3603 
3604  --ila_daq_glink : glink_chipscope_analyzer
3605  -- port map (
3606  -- CONTROL => control0,
3607  -- CLK => clk40_in_TX_SFP_ROI,
3608  -- DATA => data_ila_daq,
3609  -- TRIG0 => trig_ila_daq);
3610 
3611  --ila_glink_encoder : glink_chipscope_analyzer_encoder
3612  -- port map (
3613  -- CONTROL => control1,
3614  -- CLK => clk120_in_TX_SFP_ROI,
3615  -- DATA => data_ila_encoder,
3616  -- TRIG0 => trig_ila_encoder);
3617 
3618  --ila_gtx_start: entity work.glink_chipscope_analyzer_gtx_start
3619  -- port map (
3620  -- CONTROL => CONTROL2,
3621  -- CLK => MGTREFCLK_Q118,
3622  -- DATA => data_ila_gtx_start,
3623  -- TRIG0 => trig_ila_gtx_start);
3624 
3625  --data_ila_daq <= daq_in &
3626  -- daq_encoded_diag &
3627  -- pll_locked &
3628  -- local_pll_lock_out_SFP_DAQ &
3629  -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3630  -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3631  -- local_pll_lock_out_SFP_ROI &
3632  -- GTX_TX_READY_OUT_TX_SFP_ROI &
3633  -- GTX_RX_READY_OUT_TX_SFP_ROI &
3634  -- reset_daq &
3635  -- l1a_synced &
3636  -- daq_dav ;
3637 
3638 
3639  --trig_ila_daq <= daq_encoded_diag &
3640  -- pll_locked &
3641  -- local_pll_lock_out_SFP_DAQ &
3642  -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3643  -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3644  -- local_pll_lock_out_SFP_ROI &
3645  -- GTX_TX_READY_OUT_TX_SFP_ROI &
3646  -- GTX_RX_READY_OUT_TX_SFP_ROI &
3647  -- reset_daq &
3648  -- l1a_synced &
3649  -- daq_dav ;
3650 
3651 
3652 
3653  --trig_ila_encoder <= GTX_TX_READY_OUT_TX_SFP_DAQ &
3654  -- reset_daq &
3655  -- l1a_synced &
3656  -- daq_byte &
3657  -- pll_locked;
3658 
3659  --data_ila_encoder <= byte_pos_out &
3660  -- word_sel_out &
3661  -- readout_rst_out &
3662  -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3663  -- reset_daq &
3664  -- l1a_synced &
3665  -- daq_byte&
3666  -- pll_locked;
3667 
3668  --trig_ila_gtx_start(0)<=pll_locked;
3669  --trig_ila_gtx_start(1)<=gtx_reset_SFP_DAQ;
3670  --trig_ila_gtx_start(2)<=gtx_reset_SFP_ROI;
3671 
3672 
3673 
3674  --data_ila_gtx_start(0)<= pll_locked;
3675  --data_ila_gtx_start(1)<= gtx_reset_SFP_DAQ;
3676  --data_ila_gtx_start(2)<= gtx_reset_SFP_ROI;
3677  --data_ila_gtx_start(3)<= GTX_TX_READY_OUT_TX_SFP_DAQ;
3678  --data_ila_gtx_start(4)<= PLLLKDET_diag_TX_SFP_DAQ;
3679  --data_ila_gtx_start(5)<= local_gtx_reset_diag_TX_SFP_DAQ;
3680  --data_ila_gtx_start(6)<= local_mmcm_reset_diag_TX_SFP_DAQ;
3681  --data_ila_gtx_start(7)<= GTXTEST_diag_TX_SFP_DAQ;
3682  --data_ila_gtx_start(8)<= GTX_TX_READY_OUT_TX_SFP_ROI;
3683  --data_ila_gtx_start(9)<= PLLLKDET_diag_TX_SFP_ROI;
3684  --data_ila_gtx_start(10)<= local_gtx_reset_diag_TX_SFP_ROI;
3685  --data_ila_gtx_start(11)<= local_mmcm_reset_diag_TX_SFP_ROI;
3686  --data_ila_gtx_start(12)<= GTXTEST_diag_TX_SFP_ROI;
3687 
3688 
3689 
3690  process(buf_clk40)
3691  begin
3692  if rising_edge(buf_clk40) then
3693  l1a_synced<=BUF_TTC_L1_ACCEPT_r;
3694  BUF_TTC_L1_ACCEPT_r<=BUF_TTC_L1_ACCEPT;
3695 
3696  bc_reset_synced<=BUF_TTC_BNCH_CNT_RES_r;
3697  BUF_TTC_BNCH_CNT_RES_r<=BUF_TTC_BNCH_CNT_RES;
3698  end if;
3699  end process;
3700 
3701 
3702 
3703 
3704  daq_collector_i: entity work.daq_collector
3705  port map (
3706  clk => buf_clk40 ,
3707  datai => DATA96,
3708  energy_remote => ENERGY_REMOTE,
3709  energy_local => LOCAL_CABLE_OUT,
3710  energy_total => (others=>(others =>'0')),
3711  energy_ovflw => (others =>'0'),
3712  energy_extra0 => (others =>'0'),
3713  energy_extra1 => (others =>'0'),
3714  data_in_daq => data_in_daq,
3715  BCID_in => BCID_counter_sig ,
3716  BCID_delayed => BCID_delayed_daq );
3717 
3718 
3719  CMX_rate_counter_inhibit_inst: entity work.CMX_rate_counter_inhibit
3720  port map (
3721  counter_inhibit => counter_inhibit,
3722  counter_reset => counter_reset,
3723  buf_clk40 => buf_clk40,
3724  ncs => ncs,
3725  rd_nwr => OCB_WRITE_B ,
3726  ds => ds,
3727  addr_vme => vme_address(16 downto 1),
3728  data_vme_in => data_vme_going_below,
3729  data_vme_out => data_vme_from_below_top(1637),
3730  bus_drive => bus_drive_from_below_top (1637));
3731 
3732  daq_readout: entity work.daq_glink
3733  port map (
3734  data_in => data_in_daq ,
3735  bc_counter => unsigned(BCID_delayed_daq),
3736  l1a => l1a_synced ,
3737  data_out => daq_in,
3738  dav => daq_dav ,
3739  clk4000 => clk40_out_TX_SFP_DAQ ,
3740  clk4008 => buf_clk40,
3741  reset => reset_daq ,--not pll_locked,
3742  RAM_global_offset => RAM_global_offset ,
3743  RAM_rel_offsets => RAM_rel_offsets,
3744  nslices => nslices
3745  );
3746 
3747  daq_roi: entity work.daq_glink
3748  port map (
3749  data_in => data_in_daq ,
3750  bc_counter => unsigned(BCID_delayed_daq),
3751  l1a => l1a_synced ,
3752  data_out => roi_in,
3753  dav => roi_dav ,
3754  clk4000 => clk40_out_TX_SFP_DAQ ,
3755  clk4008 => buf_clk40,
3756  reset => reset_daq ,--not pll_locked,
3757  RAM_global_offset => RAM_global_offset ,
3758  RAM_rel_offsets => RAM_rel_offsets,
3759  nslices => to_unsigned(0,8)
3760  );
3761 
3762 
3763  --readout control registers
3764  vme_inreg_async_REG_RW_DAQ_SLICE: entity work.vme_inreg_notri_async
3765  generic map (
3766  ia_vme => ADDR_REG_RW_DAQ_SLICE,
3767  width => 16)
3768  port map (
3769  ncs => ncs,
3770  rd_nwr => OCB_WRITE_B ,
3771  ds => ds,
3772  addr_vme => vme_address(16 downto 1),
3773  data_vme_in => data_vme_going_below ,
3774  data_vme_out => data_vme_from_below_top(1607),
3775  bus_drive => bus_drive_from_below_top (1607),
3776  data_from_vme => data_from_vme_REG_RW_DAQ_SLICE,
3777  data_to_vme => data_to_vme_REG_RW_DAQ_SLICE );
3778 
3779  nslices(1 downto 0) <= unsigned(data_to_vme_REG_RW_DAQ_SLICE(1 downto 0));
3780  nslices(7 downto 2) <= (others=>'0');
3781 
3782  data_to_vme_REG_RW_DAQ_SLICE<=data_from_vme_REG_RW_DAQ_SLICE;
3783 
3784 
3785  vme_inreg_async_REG_DAQ_RAM_OFFSET: entity work.vme_inreg_notri_async
3786  generic map (
3787  ia_vme => ADDR_REG_RW_DAQ_RAM_OFFSET ,
3788  width => 16)
3789  port map (
3790  ncs => ncs,
3791  rd_nwr => OCB_WRITE_B ,
3792  ds => ds,
3793  addr_vme => vme_address(16 downto 1),
3794  data_vme_in => data_vme_going_below ,
3795  data_vme_out => data_vme_from_below_top(1608),
3796  bus_drive => bus_drive_from_below_top (1608),
3797  data_from_vme => data_from_vme_REG_RW_DAQ_RAM_OFFSET,
3798  data_to_vme => data_to_vme_REG_RW_DAQ_RAM_OFFSET);
3799 
3800  data_to_vme_REG_RW_DAQ_RAM_OFFSET<=data_from_vme_REG_RW_DAQ_RAM_OFFSET;
3801  RAM_global_offset <= unsigned(data_from_vme_REG_RW_DAQ_RAM_OFFSET(7 downto 0));
3802 
3803 
3804  rel_offset_gen: for i_row in 1 to 19 generate
3805  vme_inreg_async_REG_DAQ_RAM_OFFSET: entity work.vme_inreg_notri_async
3806  generic map (
3807  ia_vme => (ADDR_REG_RW_DAQ_RAM_RELATIVE_OFFSET+2*(i_row-1)),
3808  width => 16)
3809  port map (
3810  ncs => ncs,
3811  rd_nwr => OCB_WRITE_B ,
3812  ds => ds,
3813  data_vme_in => data_vme_going_below ,
3814  addr_vme => vme_address(16 downto 1),
3815  data_vme_out => data_vme_from_below_top(1609+i_row),
3816  bus_drive => bus_drive_from_below_top (1609+i_row),
3817  data_from_vme => data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1),
3818  data_to_vme => data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1));
3819 
3820  data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)<=data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1);
3821  RAM_rel_offsets(i_row-1)<=unsigned(data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)(7 downto 0));
3822  end generate rel_offset_gen;
3823 
3824 
3825 
3826 end Behavioral;
3827 
CMX_top_Base.P6_5
in P6_5std_logic
Definition: CMX_top_Base.vhd:246
CMX_top_Base.BF_DOUT_CTP_41
out BF_DOUT_CTP_41std_logic
Definition: CMX_top_Base.vhd:581
CMX_top_Base.P3_21
in P3_21std_logic
Definition: CMX_top_Base.vhd:187
CMX_top_Base.P9_17
in P9_17std_logic
Definition: CMX_top_Base.vhd:333
CMX_top_Base.BF_SYSMON_13_N
in BF_SYSMON_13_NSTD_LOGIC
Definition: CMX_top_Base.vhd:84
CMX_top_Base.P1_7
in P1_7std_logic
Definition: CMX_top_Base.vhd:123
Topo_Data_TX.TXN_OUT
out TXN_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:36
CMX_top_Base.BF_SYSMON_14_P
in BF_SYSMON_14_PSTD_LOGIC
Definition: CMX_top_Base.vhd:85
CMX_top_Base.P12_4
in P12_4std_logic
Definition: CMX_top_Base.vhd:395
CMX_top_Base.P3_6
in P3_6std_logic
Definition: CMX_top_Base.vhd:172
CMX_top_Base.Behavioral.ncs
std_logic ncs
Definition: CMX_top_Base.vhd:793
CMX_top_Base.P11_20
in P11_20std_logic
Definition: CMX_top_Base.vhd:386
CMX_top_Base.D_CBL_48_B
out D_CBL_48_Bstd_logic
Definition: CMX_top_Base.vhd:656
CMX_top_Base.P6_24
in P6_24std_logic
Definition: CMX_top_Base.vhd:265
CMX_top_Base.BF_DOUT_CTP_01
out BF_DOUT_CTP_01std_logic
Definition: CMX_top_Base.vhd:539
CMX_top_Base.P13_17
in P13_17std_logic
Definition: CMX_top_Base.vhd:433
CMX_top_Base.P10_16
in P10_16std_logic
Definition: CMX_top_Base.vhd:357
CMX_top_Base.P14_21
in P14_21std_logic
Definition: CMX_top_Base.vhd:462
CMX_top_Base.P11_18
in P11_18std_logic
Definition: CMX_top_Base.vhd:384
CMX_top_Base.BF_TO_FROM_BSPT_2
out BF_TO_FROM_BSPT_2std_logic
Definition: CMX_top_Base.vhd:530
vme_inreg.read_detect
out read_detectstd_logic
Definition: vme_inreg_rtl.vhd:38
CMX_top_Base.BF_DAQ_DATA_OUT_CMP
out BF_DAQ_DATA_OUT_CMPstd_logic
Definition: CMX_top_Base.vhd:705
CMX_Sum_Et.counter_inhibit
in counter_inhibitT_SL
Definition: CMX_SumEt.vhd:47
CMX_top_Base.OCB_A10
in OCB_A10std_logic
Definition: CMX_top_Base.vhd:41
CMX_top_Base.CLK_120MHz000_XTAL_1_BF_TRNCV_DIR
in CLK_120MHz000_XTAL_1_BF_TRNCV_DIRstd_logic
Definition: CMX_top_Base.vhd:702
CMX_top_Base.P11_7
in P11_7std_logic
Definition: CMX_top_Base.vhd:373
CMX_top_Base.P14_13
in P14_13std_logic
Definition: CMX_top_Base.vhd:454
CMX_top_Base.D_CBL_74_B
out D_CBL_74_Bstd_logic
Definition: CMX_top_Base.vhd:684
CMX_top_Base.P1_21
in P1_21std_logic
Definition: CMX_top_Base.vhd:137
sys_monitor.BF_SYSMON_09_P
in BF_SYSMON_09_PSTD_LOGIC
Definition: sys_monitor.vhd:38
CMX_top_Base.P7_20
in P7_20std_logic
Definition: CMX_top_Base.vhd:286
CMX_top_Base.D_CBL_32_B
out D_CBL_32_Bstd_logic
Definition: CMX_top_Base.vhd:640
CMX_delay_generator.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_delay_generator.vhd:39
CMX_top_Base.BF_TO_TP_ROI_SLINK_RETURN_CMP
in BF_TO_TP_ROI_SLINK_RETURN_CMPstd_logic
Definition: CMX_top_Base.vhd:696
vme_outreg_notri.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl_notri.vhd:16
CMX_top_Base.BF_TO_FROM_BSPT_3
out BF_TO_FROM_BSPT_3std_logic
Definition: CMX_top_Base.vhd:531
CMX_top_Base.MP1_F11_QUAD_111_TRN_1_CMP
out MP1_F11_QUAD_111_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:720
CMX_top_Base.P5_10
in P5_10std_logic
Definition: CMX_top_Base.vhd:226
CMX_crate_cable_output_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_crate_cable_output_module.vhd:39
CMX_top_Base.P7_10
in P7_10std_logic
Definition: CMX_top_Base.vhd:276
CMX_top_Base.P2_14
in P2_14std_logic
Definition: CMX_top_Base.vhd:155
CMX_top_Base.P1_2
in P1_2std_logic
Definition: CMX_top_Base.vhd:118
CMX_top_Base.P9_3
in P9_3std_logic
Definition: CMX_top_Base.vhd:319
CMX_input_module.ODATA
out ODATAarr_4Xword (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:33
CMX_top_Base.P1_10
in P1_10std_logic
Definition: CMX_top_Base.vhd:126
CMX_top_Base.D_CBL_42_B
out D_CBL_42_Bstd_logic
Definition: CMX_top_Base.vhd:650
CMX_top_Base.P1_19
in P1_19std_logic
Definition: CMX_top_Base.vhd:135
CMX_SumET_Topo_Encoder.bcid_adj
out bcid_adjstd_logic_vector (11 downto 0)
Definition: CMX_SumET_Topo_Encoder.vhd:35
CMX_top_Base.P4_12
in P4_12std_logic
Definition: CMX_top_Base.vhd:203
CMX_top_Base.P7_5
in P7_5std_logic
Definition: CMX_top_Base.vhd:271
vme_inreg.write_detect
out write_detectstd_logic
Definition: vme_inreg_rtl.vhd:39
CMX_top_Base.P12_6
in P12_6std_logic
Definition: CMX_top_Base.vhd:397
CMX_input_module.ds
in dsstd_logic
Definition: CMX_input_module.vhd:59
CMX_top_Base.Behavioral.read_detect_inreg_test
std_logic read_detect_inreg_test
Definition: CMX_top_Base.vhd:936
vme_outreg.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl.vhd:24
CMX_top_Base.BF_LED_REQ_4
out BF_LED_REQ_4std_logic
Definition: CMX_top_Base.vhd:527
CMX_top_Base.P8_24
in P8_24std_logic
Definition: CMX_top_Base.vhd:315
CMX_top_Base.OCB_A19
in OCB_A19std_logic
Definition: CMX_top_Base.vhd:50
CMX_crate_cable_output_module.start_playback
in start_playbackstd_logic
Definition: CMX_crate_cable_output_module.vhd:34
vme_outreg.clk
in clkstd_logic
Definition: vme_outreg_rtl.vhd:21
CMX_BASE_VME_BSPT.n_write
in n_writestd_logic
Definition: cmx_base_vme_bspt.vhd:29
CMX_top_Base.BF_TO_FROM_BSPT_0
in BF_TO_FROM_BSPT_0std_logic
Definition: CMX_top_Base.vhd:528
CMX_clock_manager
Definition: CMX_clock_manager.vhd:27
CMX_top_Base.D_CBL_17_B
out D_CBL_17_Bstd_logic
Definition: CMX_top_Base.vhd:623
CMX_top_Base.P7_18
in P7_18std_logic
Definition: CMX_top_Base.vhd:284
vme_inreg_notri.read_detect
out read_detectstd_logic
Definition: vme_inreg_rtl_notri.vhd:39
CMX_top_Base.P6_15
in P6_15std_logic
Definition: CMX_top_Base.vhd:256
CMX_top_Base.BF_DOUT_CTP_61
out BF_DOUT_CTP_61std_logic
Definition: CMX_top_Base.vhd:601
vme_outreg_notri_async.ncs
in ncsstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:22
CMX_top_Base.P3_14
in P3_14std_logic
Definition: CMX_top_Base.vhd:180
CMX_input_module.PAR_ERROR_total
out PAR_ERROR_totalstd_logic
Definition: CMX_input_module.vhd:39
CMX_Memory_spy_inhibit
Definition: CMX_Memory_spy_inhibit.vhd:37
CMX_top_Base.P4_21
in P4_21std_logic
Definition: CMX_top_Base.vhd:212
daq_collector.data_in_daq
out data_in_daqarr_96 (19 downto 0)
Definition: daq_collector.vhd:32
CMX_top_Base.OCB_A21
in OCB_A21std_logic
Definition: CMX_top_Base.vhd:52
CMX_top_Base.P1_11
in P1_11std_logic
Definition: CMX_top_Base.vhd:127
CMX_top_Base.D_CBL_64_B
out D_CBL_64_Bstd_logic
Definition: CMX_top_Base.vhd:674
CMX_top_Base.P5_13
in P5_13std_logic
Definition: CMX_top_Base.vhd:229
CMX_top_Base.P6_19
in P6_19std_logic
Definition: CMX_top_Base.vhd:260
CMX_Sum_Et.sums_all_out
out sums_all_outarr_ctr_15bit (5 downto 0)
Definition: CMX_SumEt.vhd:39
vme_inreg_notri_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:29
sys_monitor.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: sys_monitor.vhd:58
CMX_top_Base.BF_DOUT_CTP_34
out BF_DOUT_CTP_34std_logic
Definition: CMX_top_Base.vhd:574
Topo_Data_TX.MGTREFCLK_PAD_N_IN
in MGTREFCLK_PAD_N_INstd_logic_vector (num_GTX_groups - 1 downto 0)
Definition: Topo_Data_TX.vhd:27
CMX_top_Base.P15_5
in P15_5std_logic
Definition: CMX_top_Base.vhd:471
CMX_top_Base.P5_6
in P5_6std_logic
Definition: CMX_top_Base.vhd:222
CMX_top_Base.P9_10
in P9_10std_logic
Definition: CMX_top_Base.vhd:326
CMX_top_Base.MP1_F04_QUAD_112_TRN_0_DIR
out MP1_F04_QUAD_112_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:725
vme_inreg.data_vme
inout data_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl.vhd:32
CMX_top_Base.BF_DOUT_CTP_32
out BF_DOUT_CTP_32std_logic
Definition: CMX_top_Base.vhd:572
daq_glink.data_in
in data_inarr_96 (19 downto 0)
Definition: daq_glink.vhd:24
CMX_crate_cable_output_module.ncs
in ncsstd_logic
Definition: CMX_crate_cable_output_module.vhd:38
CMX_top_Base.D_CBL_81_B
out D_CBL_81_Bstd_logic
Definition: CMX_top_Base.vhd:633
CMX_crate_cable_output_module.buf_clk40_center
in buf_clk40_centerstd_logic
Definition: CMX_crate_cable_output_module.vhd:32
CMX_top_Base.P11_3
in P11_3std_logic
Definition: CMX_top_Base.vhd:369
CMX_version.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_version.vhd:26
CMX_top_Base.P6_4
in P6_4std_logic
Definition: CMX_top_Base.vhd:245
CMX_top_Base.P9_7
in P9_7std_logic
Definition: CMX_top_Base.vhd:323
CMX_top_Base.P9_12
in P9_12std_logic
Definition: CMX_top_Base.vhd:328
CMX_top_Base.P13_18
in P13_18std_logic
Definition: CMX_top_Base.vhd:434
CMX_top_Base.D_CBL_67_B
out D_CBL_67_Bstd_logic
Definition: CMX_top_Base.vhd:677
CMX_top_Base.P7_9
in P7_9std_logic
Definition: CMX_top_Base.vhd:275
CMX_top_Base.MP1_F07_QUAD_110_TRN_2_DIR
out MP1_F07_QUAD_110_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:713
CMX_top_Base.P0_6
in P0_6std_logic
Definition: CMX_top_Base.vhd:97
CMX_top_Base.P6_1
in P6_1std_logic
Definition: CMX_top_Base.vhd:242
CMX_top_Base.P10_5
in P10_5std_logic
Definition: CMX_top_Base.vhd:346
CMX_top_Base.P1_4
in P1_4std_logic
Definition: CMX_top_Base.vhd:120
sys_monitor.rd_nwr
in rd_nwrstd_logic
Definition: sys_monitor.vhd:54
vme_outreg_notri_async.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:27
CMX_top_Base.P13_20
in P13_20std_logic
Definition: CMX_top_Base.vhd:436
CMX_top_Base.D_CBL_24_B
in D_CBL_24_Bstd_logic
Definition: CMX_top_Base.vhd:630
CMX_top_Base.D_CBL_28_B
out D_CBL_28_Bstd_logic
Definition: CMX_top_Base.vhd:636
CMX_top_Base.BF_TO_FROM_BSPT_6
out BF_TO_FROM_BSPT_6std_logic
Definition: CMX_top_Base.vhd:534
vme_inreg_notri.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:33
SFP_Data_TXRX.local_gtx_reset_diag
out local_gtx_reset_diagstd_logic
Definition: SFP_TXRX.vhd:39
CMX_top_Base.P8_19
in P8_19std_logic
Definition: CMX_top_Base.vhd:310
SFP_Data_TXRX.DFETAP2MONITOR
out DFETAP2MONITORstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:64
CMX_top_Base.P6_16
in P6_16std_logic
Definition: CMX_top_Base.vhd:257
CMX_top_Base.BF_LED_REQ_1
out BF_LED_REQ_1std_logic
Definition: CMX_top_Base.vhd:524
CMX_top_Base.MP2_F01_QUAD_113_TRN_0_CMP
out MP2_F01_QUAD_113_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:734
vme_outreg.ds
in dsstd_logic
Definition: vme_outreg_rtl.vhd:25
CMX_top_Base.P11_0
in P11_0std_logic
Definition: CMX_top_Base.vhd:366
CMX_top_Base.P5_21
in P5_21std_logic
Definition: CMX_top_Base.vhd:237
CMX_Memory_spy_inhibit.bus_drive
out bus_drivestd_logic
Definition: CMX_Memory_spy_inhibit.vhd:48
Topo_Data_TX.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:56
CMX_top_Base.BF_DEBUG_2
out BF_DEBUG_2std_logic
Definition: CMX_top_Base.vhd:508
CMX_top_Base.P5_8
in P5_8std_logic
Definition: CMX_top_Base.vhd:224
CMX_top_Base.BF_DOUT_CTP_21
out BF_DOUT_CTP_21std_logic
Definition: CMX_top_Base.vhd:559
CMX_top_Base.P7_21
in P7_21std_logic
Definition: CMX_top_Base.vhd:287
CMX_clock_manager.buf_clk160
out buf_clk160std_logic
Definition: CMX_clock_manager.vhd:37
SFP_Data_TXRX
Definition: SFP_TXRX.vhd:21
CMX_Sum_Et.BACKPLANE_DATA_IN
in BACKPLANE_DATA_INenergy_array
Definition: CMX_SumEt.vhd:41
CMX_top_Base.MP1_F10_QUAD_111_TRN_2_DIR
out MP1_F10_QUAD_111_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:721
CMX_top_Base.D_CBL_79_B
out D_CBL_79_Bstd_logic
Definition: CMX_top_Base.vhd:689
CMX_Sum_Et.T_SUM_E_MAX
in T_SUM_E_MAXarr_ctr_15bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:36
CMX_top_Base.P1_8
in P1_8std_logic
Definition: CMX_top_Base.vhd:124
vme_outreg.read_detect
out read_detectstd_logic
Definition: vme_outreg_rtl.vhd:31
CMX_top_Base.D_CBL_59_B
out D_CBL_59_Bstd_logic
Definition: CMX_top_Base.vhd:669
CMX_top_Base.P6_0
in P6_0std_logic
Definition: CMX_top_Base.vhd:241
CMX_top_Base.Behavioral.data_to_vme_test_rw
std_logic_vector (15 downto 0) data_to_vme_test_rw
Definition: CMX_top_Base.vhd:935
CMX_top_Base.BF_DOUT_CTP_46
out BF_DOUT_CTP_46std_logic
Definition: CMX_top_Base.vhd:586
daq_collector.clk
in clkT_SL
Definition: daq_collector.vhd:24
CMX_Memory_spy_inhibit.rd_nwr
in rd_nwrstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:43
CMX_top_Base.P2_18
in P2_18std_logic
Definition: CMX_top_Base.vhd:159
CMX_top_Base.P10_23
in P10_23std_logic
Definition: CMX_top_Base.vhd:364
CMX_top_Base.D_CBL_38_B
out D_CBL_38_Bstd_logic
Definition: CMX_top_Base.vhd:646
CMX_delay_generator.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_delay_generator.vhd:37
SFP_Data_TXRX.DFETAP4
in DFETAP4std_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:67
sys_monitor.BF_SYSMON_03_N
in BF_SYSMON_03_NSTD_LOGIC
Definition: sys_monitor.vhd:31
CMX_top_Base.P11_8
in P11_8std_logic
Definition: CMX_top_Base.vhd:374
CMX_top_Base.BF_DOUT_CTP_04
out BF_DOUT_CTP_04std_logic
Definition: CMX_top_Base.vhd:542
CMX_top_Base.P2_15
in P2_15std_logic
Definition: CMX_top_Base.vhd:156
CMX_top_Base.OCB_A09
in OCB_A09std_logic
Definition: CMX_top_Base.vhd:40
CMX_Sum_Et.counter_reset
in counter_resetT_SL
Definition: CMX_SumEt.vhd:46
SFP_Data_TXRX.TXN_OUT
out TXN_OUTstd_logic
Definition: SFP_TXRX.vhd:44
CMX_input_module.counter_enable_out
out counter_enable_outstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:41
CMX_top_Base.P8_9
in P8_9std_logic
Definition: CMX_top_Base.vhd:300
sys_monitor.BF_SYSMON_10_P
in BF_SYSMON_10_PSTD_LOGIC
Definition: sys_monitor.vhd:40
CMX_top_Base.BF_DOUT_CTP_65
out BF_DOUT_CTP_65std_logic
Definition: CMX_top_Base.vhd:604
CMX_top_Base.P3_11
in P3_11std_logic
Definition: CMX_top_Base.vhd:177
CMX_top_Base.P11_1
in P11_1std_logic
Definition: CMX_top_Base.vhd:367
CMX_top_Base.BF_DOUT_CTP_55
out BF_DOUT_CTP_55std_logic
Definition: CMX_top_Base.vhd:595
sys_monitor.BF_SYSMON_13_N
in BF_SYSMON_13_NSTD_LOGIC
Definition: sys_monitor.vhd:47
CMX_top_Base.P11_23
in P11_23std_logic
Definition: CMX_top_Base.vhd:389
CMX_input_module.upload_delays
in upload_delaysstd_logic
Definition: CMX_input_module.vhd:45
CMX_top_Base.Behavioral.data_vme_up_top
std_logic_vector (15 downto 0) data_vme_up_top
Definition: CMX_top_Base.vhd:866
CMX_top_Base.P0_8
in P0_8std_logic
Definition: CMX_top_Base.vhd:99
CMX_top_Base.P9_6
in P9_6std_logic
Definition: CMX_top_Base.vhd:322
CMX_top_Base.P4_20
in P4_20std_logic
Definition: CMX_top_Base.vhd:211
vme_inreg_notri.ncs
in ncsstd_logic
Definition: vme_inreg_rtl_notri.vhd:27
CMX_top_Base.P12_12
in P12_12std_logic
Definition: CMX_top_Base.vhd:403
CMX_top_Base.BF_SYSMON_13_P
in BF_SYSMON_13_PSTD_LOGIC
Definition: CMX_top_Base.vhd:83
CMX_top_Base.BF_DOUT_CTP_19
out BF_DOUT_CTP_19std_logic
Definition: CMX_top_Base.vhd:557
sys_monitor.BF_SYSMON_12_P
in BF_SYSMON_12_PSTD_LOGIC
Definition: sys_monitor.vhd:44
CMX_top_Base.P1_16
in P1_16std_logic
Definition: CMX_top_Base.vhd:132
SFP_Data_TXRX.TXDIFFCTRL_IN
in TXDIFFCTRL_INstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:54
CMX_top_Base.OCB_A14
in OCB_A14std_logic
Definition: CMX_top_Base.vhd:45
CMX_top_Base.P3_23
in P3_23std_logic
Definition: CMX_top_Base.vhd:189
CMX_top_Base.OCB_DS_B
in OCB_DS_Bstd_logic
Definition: CMX_top_Base.vhd:56
CMX_top_Base.OCB_A11
in OCB_A11std_logic
Definition: CMX_top_Base.vhd:42
CMX_top_Base.P6_21
in P6_21std_logic
Definition: CMX_top_Base.vhd:262
CMX_input_module.buf_clk40_m180o
in buf_clk40_m180ostd_logic
Definition: CMX_input_module.vhd:29
CMX_top_Base.BF_DOUT_CTP_14
out BF_DOUT_CTP_14std_logic
Definition: CMX_top_Base.vhd:552
CMX_crate_cable_output_module.ds
in dsstd_logic
Definition: CMX_crate_cable_output_module.vhd:40
CMX_top_Base.BF_DOUT_CTP_47
out BF_DOUT_CTP_47std_logic
Definition: CMX_top_Base.vhd:587
CMX_top_Base.D_CBL_39_B
in D_CBL_39_Bstd_logic
Definition: CMX_top_Base.vhd:647
CMX_SumET_Topo_Encoder.send_align_out
out send_align_outstd_logic_vector (num_GTX_groups * num_GTX_per_group - 1 downto 0)
Definition: CMX_SumET_Topo_Encoder.vhd:31
CMX_rate_counter_inhibit.buf_clk40
in buf_clk40std_logic
Definition: CMX_rate_counter_inhibit.vhd:33
CMX_input_module
Definition: CMX_input_module.vhd:25
CMX_top_Base.P4_18
in P4_18std_logic
Definition: CMX_top_Base.vhd:209
CMX_top_Base.P9_2
in P9_2std_logic
Definition: CMX_top_Base.vhd:318
CMX_top_Base.BF_SYSMON_01_N
in BF_SYSMON_01_NSTD_LOGIC
Definition: CMX_top_Base.vhd:66
vme_outreg_notri_async.width
widthinteger :=16
Definition: vme_outreg_rtl_notri_async.vhd:19
vme_main_hub.data_vme
inout data_vmestd_logic_vector (15 downto 0)
the tri-stated port
Definition: vme_main_hub.vhd:23
CMX_top_Base.P4_14
in P4_14std_logic
Definition: CMX_top_Base.vhd:205
CMX_top_Base.D_CBL_27_B
out D_CBL_27_Bstd_logic
Definition: CMX_top_Base.vhd:635
CMX_top_Base.P10_18
in P10_18std_logic
Definition: CMX_top_Base.vhd:359
CMX_input_module.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:61
CMX_top_Base.P9_21
in P9_21std_logic
Definition: CMX_top_Base.vhd:337
CMX_top_Base.BF_SYSMON_10_N
in BF_SYSMON_10_NSTD_LOGIC
Definition: CMX_top_Base.vhd:78
CMX_top_Base.P15_18
in P15_18std_logic
Definition: CMX_top_Base.vhd:484
CMX_top_Base.OCB_A15
in OCB_A15std_logic
Definition: CMX_top_Base.vhd:46
vme_inreg_async.ds
in dsstd_logic
Definition: vme_inreg_async_rtl.vhd:27
CMX_top_Base.P8_21
in P8_21std_logic
Definition: CMX_top_Base.vhd:312
CMX_top_Base.P2_1
in P2_1std_logic
Definition: CMX_top_Base.vhd:142
CMX_top_Base.D_CBL_06_B
out D_CBL_06_Bstd_logic
Definition: CMX_top_Base.vhd:612
CMX_top_Base.P14_17
in P14_17std_logic
Definition: CMX_top_Base.vhd:458
CMX_top_Base.work
_library_ workwork
Definition: CMX_top_Base.vhd:15
CMX_top_Base.BF_LED_REQ_2
out BF_LED_REQ_2std_logic
Definition: CMX_top_Base.vhd:525
glink_interface.RST
in RSTstd_logic
Definition: glink_interface.vhd:21
CMX_top_Base.P7_6
in P7_6std_logic
Definition: CMX_top_Base.vhd:272
CMX_top_Base.P9_13
in P9_13std_logic
Definition: CMX_top_Base.vhd:329
CMX_top_Base.BF_TO_TP_DAQ_SLINK_RETURN_DIR
in BF_TO_TP_DAQ_SLINK_RETURN_DIRstd_logic
Definition: CMX_top_Base.vhd:693
CMX_top_Base.P9_18
in P9_18std_logic
Definition: CMX_top_Base.vhd:334
vme_inreg_notri.width
widthinteger :=16
Definition: vme_inreg_rtl_notri.vhd:22
CMX_SumET_Topo_Encoder
Definition: CMX_SumET_Topo_Encoder.vhd:25
CMX_top_Base.D_CBL_76_B
out D_CBL_76_Bstd_logic
Definition: CMX_top_Base.vhd:686
CMX_top_Base.P10_11
in P10_11std_logic
Definition: CMX_top_Base.vhd:352
vme_outreg.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl.vhd:17
CMX_top_Base.MP2_F11_QUAD_114_TRN_1_DIR
out MP2_F11_QUAD_114_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:743
CMX_top_Base.D_CBL_01_B
out D_CBL_01_Bstd_logic
Definition: CMX_top_Base.vhd:607
Topo_Data_TX.rd_nwr
in rd_nwrstd_logic
Definition: Topo_Data_TX.vhd:53
vme_inreg_notri_async.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:34
CMX_top_Base.P14_9
in P14_9std_logic
Definition: CMX_top_Base.vhd:450
vme_inreg.width
widthinteger :=16
Definition: vme_inreg_rtl.vhd:22
daq_glink.RAM_rel_offsets
in RAM_rel_offsetsarr_ctr_8bit (18 downto 0)
Definition: daq_glink.vhd:35
CMX_top_Base.P3_16
in P3_16std_logic
Definition: CMX_top_Base.vhd:182
CMX_top_Base.P4_13
in P4_13std_logic
Definition: CMX_top_Base.vhd:204
CMX_top_Base.BF_LED_REQ_0
out BF_LED_REQ_0std_logic
Definition: CMX_top_Base.vhd:523
CMX_top_Base.P2_6
in P2_6std_logic
Definition: CMX_top_Base.vhd:147
CMX_input_module.P
in Pmat_var (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:27
CMX_top_Base.P13_6
in P13_6std_logic
Definition: CMX_top_Base.vhd:422
CMX_top_Base.BF_DOUT_CTP_00
out BF_DOUT_CTP_00std_logic
Definition: CMX_top_Base.vhd:538
CMX_top_Base.P15_19
in P15_19std_logic
Definition: CMX_top_Base.vhd:485
CMX_version
Definition: CMX_version.vhd:19
BCID_counter.BCID_out
out BCID_outstd_logic_vector (11 downto 0)
Definition: BCID_counter.vhd:32
SFP_Data_TXRX.TXPREEMPHASIS_IN
in TXPREEMPHASIS_INstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:52
vme_inreg_notri_async.width
widthinteger :=16
Definition: vme_inreg_rtl_notri_async.vhd:21
vme_inreg.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl.vhd:35
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_114_DIR
in CLK_320MHz64_LHC_BF_QUAD_114_DIRstd_logic
Definition: CMX_top_Base.vhd:759
CMX_top_Base.Behavioral.vme_local_switch
vme_local_switch
Definition: CMX_top_Base.vhd:847
sys_monitor.BF_SYSMON_03_P
in BF_SYSMON_03_PSTD_LOGIC
Definition: sys_monitor.vhd:30
CMX_top_Base.P6_11
in P6_11std_logic
Definition: CMX_top_Base.vhd:252
CMX_top_Base.P1_20
in P1_20std_logic
Definition: CMX_top_Base.vhd:136
CMX_top_Base.P15_15
in P15_15std_logic
Definition: CMX_top_Base.vhd:481
CMX_top_Base.D_CBL_20_B
in D_CBL_20_Bstd_logic
Definition: CMX_top_Base.vhd:626
CMX_top_Base.P14_6
in P14_6std_logic
Definition: CMX_top_Base.vhd:447
CMX_top_Base.P3_15
in P3_15std_logic
Definition: CMX_top_Base.vhd:181
CMX_top_Base.P5_4
in P5_4std_logic
Definition: CMX_top_Base.vhd:220
CMX_top_Base.P4_17
in P4_17std_logic
Definition: CMX_top_Base.vhd:208
CMX_top_Base.P1_18
in P1_18std_logic
Definition: CMX_top_Base.vhd:134
CMX_top_Base.Behavioral.data_to_vme_outreg_test
std_logic_vector (15 downto 0) data_to_vme_outreg_test
Definition: CMX_top_Base.vhd:813
CMX_top_Base.MP2_F07_QUAD_113_TRN_2_DIR
out MP2_F07_QUAD_113_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:737
CMX_top_Base.RXP_IN
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: CMX_top_Base.vhd:763
CMX_clock_manager.I_DS1
in I_DS1std_logic
Definition: CMX_clock_manager.vhd:30
CMX_delay_generator.del_register
out del_registerdel_register_type
Definition: CMX_delay_generator.vhd:41
CMX_top_Base.P5_2
in P5_2std_logic
Definition: CMX_top_Base.vhd:218
CMX_top_Base.D_CBL_58_B
out D_CBL_58_Bstd_logic
Definition: CMX_top_Base.vhd:668
Topo_Data_TX
Definition: Topo_Data_TX.vhd:23
CMX_top_Base.BF_DOUT_CTP_49
out BF_DOUT_CTP_49std_logic
Definition: CMX_top_Base.vhd:589
CMX_top_Base.P14_10
in P14_10std_logic
Definition: CMX_top_Base.vhd:451
sys_monitor.BF_SYSMON_09_N
in BF_SYSMON_09_NSTD_LOGIC
Definition: sys_monitor.vhd:39
CMX_top_Base.P7_7
in P7_7std_logic
Definition: CMX_top_Base.vhd:273
CMX_top_Base.P12_23
in P12_23std_logic
Definition: CMX_top_Base.vhd:414
CMX_top_Base.P10_15
in P10_15std_logic
Definition: CMX_top_Base.vhd:356
sys_monitor.BF_SYSMON_13_P
in BF_SYSMON_13_PSTD_LOGIC
Definition: sys_monitor.vhd:46
CMX_clock_manager.pll_locked
out pll_lockedstd_logic
Definition: CMX_clock_manager.vhd:39
CMX_top_Base.BF_DEBUG_7
out BF_DEBUG_7std_logic
Definition: CMX_top_Base.vhd:513
CMX_crate_cable_output_module.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_crate_cable_output_module.vhd:42
SFP_Data_TXRX.TXP_OUT
out TXP_OUTstd_logic
Definition: SFP_TXRX.vhd:45
CMX_top_Base.P9_11
in P9_11std_logic
Definition: CMX_top_Base.vhd:327
CMX_top_Base.P0_11
in P0_11std_logic
Definition: CMX_top_Base.vhd:102
CMX_clock_manager.buf_clk320
out buf_clk320std_logic
Definition: CMX_clock_manager.vhd:36
CMX_delay_generator
Definition: CMX_delay_generator.vhd:28
CMX_top_Base.BF_DOUT_CTP_64
out BF_DOUT_CTP_64std_logic
Definition: CMX_top_Base.vhd:570
BCID_counter.ds
in dsstd_logic
Definition: BCID_counter.vhd:36
CMX_top_Base.P7_3
in P7_3std_logic
Definition: CMX_top_Base.vhd:269
CMX_top_Base.MP1_F04_QUAD_112_TRN_0_CMP
out MP1_F04_QUAD_112_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:726
CMX_top_Base.P1_1
in P1_1std_logic
Definition: CMX_top_Base.vhd:117
CMX_top_Base.P5_14
in P5_14std_logic
Definition: CMX_top_Base.vhd:230
CMX_top_Base.P14_7
in P14_7std_logic
Definition: CMX_top_Base.vhd:448
SFP_Data_TXRX.DFECLKDLYADJMON
out DFECLKDLYADJMONstd_logic_vector (5 downto 0)
Definition: SFP_TXRX.vhd:57
CMX_top_Base.P2_19
in P2_19std_logic
Definition: CMX_top_Base.vhd:160
daq_collector.BCID_delayed
out BCID_delayedstd_logic_vector (11 downto 0)
Definition: daq_collector.vhd:34
CMX_top_Base.P8_16
in P8_16std_logic
Definition: CMX_top_Base.vhd:307
CMX_top_Base.BF_SYSMON_15_P
in BF_SYSMON_15_PSTD_LOGIC
Definition: CMX_top_Base.vhd:87
vme_inreg_async
Definition: vme_inreg_async_rtl.vhd:18
CMX_input_module.del_register
in del_registerdel_register_type
Definition: CMX_input_module.vhd:44
CMX_top_Base.D_CBL_21_B
out D_CBL_21_Bstd_logic
Definition: CMX_top_Base.vhd:627
CMX_Memory_spy_inhibit.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_Memory_spy_inhibit.vhd:47
CMX_top_Base.D_CBL_04_B
out D_CBL_04_Bstd_logic
Definition: CMX_top_Base.vhd:610
CMX_top_Base.BF_SYSMON_03_N
in BF_SYSMON_03_NSTD_LOGIC
Definition: CMX_top_Base.vhd:68
vme_inreg_async.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_async_rtl.vhd:33
CMX_top_Base.P12_24
in P12_24std_logic
Definition: CMX_top_Base.vhd:415
CMX_top_Base.BF_ROI_DATA_OUT_DIR
out BF_ROI_DATA_OUT_DIRstd_logic
Definition: CMX_top_Base.vhd:706
CMX_top_Base.P0_18
in P0_18std_logic
Definition: CMX_top_Base.vhd:109
daq_collector.energy_extra1
in energy_extra1std_logic_vector (23 downto 0)
Definition: daq_collector.vhd:29
CMX_top_Base.P15_0
in P15_0std_logic
Definition: CMX_top_Base.vhd:466
CMX_top_Base.P2_3
in P2_3std_logic
Definition: CMX_top_Base.vhd:144
CMX_top_Base.P5_24
in P5_24std_logic
Definition: CMX_top_Base.vhd:240
vme_inreg_notri.clk
in clkstd_logic
Definition: vme_inreg_rtl_notri.vhd:25
vme_inreg_async.width
widthinteger :=16
Definition: vme_inreg_async_rtl.vhd:21
CMX_top_Base.P15_2
in P15_2std_logic
Definition: CMX_top_Base.vhd:468
CMX_top_Base.P12_19
in P12_19std_logic
Definition: CMX_top_Base.vhd:410
CMX_top_Base.P8_8
in P8_8std_logic
Definition: CMX_top_Base.vhd:299
CMX_top_Base.P6_7
in P6_7std_logic
Definition: CMX_top_Base.vhd:248
CMX_top_Base.P12_0
in P12_0std_logic
Definition: CMX_top_Base.vhd:391
vme_inreg.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl.vhd:21
daq_collector
Definition: daq_collector.vhd:22
SFP_Data_TXRX.clk120_in
in clk120_instd_logic
Definition: SFP_TXRX.vhd:49
CMX_top_Base.P12_17
in P12_17std_logic
Definition: CMX_top_Base.vhd:408
sys_monitor.BF_SYSMON_11_N
in BF_SYSMON_11_NSTD_LOGIC
Definition: sys_monitor.vhd:43
CMX_top_Base.P13_9
in P13_9std_logic
Definition: CMX_top_Base.vhd:425
vme_local_switch.data_vme_from_below
in data_vme_from_belowarr_16
--! inputs from local registers and from
Definition: vme_local_switch.vhd:35
glink_interface.CLK_40MHz
in CLK_40MHzstd_logic
Definition: glink_interface.vhd:19
vme_inreg_notri.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri.vhd:36
glink_interface
Definition: glink_interface.vhd:17
CMX_top_Base.D_CBL_80_B
out D_CBL_80_Bstd_logic
Definition: CMX_top_Base.vhd:690
vme_inreg.ncs
in ncsstd_logic
Definition: vme_inreg_rtl.vhd:27
Topo_Data_TX.ds
in dsstd_logic
Definition: Topo_Data_TX.vhd:54
SFP_Data_TXRX.GTXTEST_diag
out GTXTEST_diagstd_logic
Definition: SFP_TXRX.vhd:41
vme_main_hub.bus_drive_from_below
in bus_drive_from_belowstd_logic
--! a request to drive the outside
Definition: vme_main_hub.vhd:32
CMX_top_Base.P14_12
in P14_12std_logic
Definition: CMX_top_Base.vhd:453
CMX_top_Base
Definition: CMX_top_Base.vhd:23
CMX_version.ncs
in ncsstd_logic
Definition: CMX_version.vhd:22
CMX_version.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_version.vhd:25
CMX_top_Base.P12_2
in P12_2std_logic
Definition: CMX_top_Base.vhd:393
CMX_top_Base.D_CBL_29_B
out D_CBL_29_Bstd_logic
Definition: CMX_top_Base.vhd:637
CMX_top_Base.D_CBL_57_B
out D_CBL_57_Bstd_logic
Definition: CMX_top_Base.vhd:667
CMX_top_Base.MP1_F01_QUAD_110_TRN_0_DIR
out MP1_F01_QUAD_110_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:709
sys_monitor.BF_SYSMON_07_N
in BF_SYSMON_07_NSTD_LOGIC
Definition: sys_monitor.vhd:35
CMX_top_Base.BF_DOUT_CTP_05
out BF_DOUT_CTP_05std_logic
Definition: CMX_top_Base.vhd:543
daq_collector.energy_extra0
in energy_extra0std_logic_vector (23 downto 0)
Definition: daq_collector.vhd:28
CMX_delay_generator.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_delay_generator.vhd:38
CMX_top_Base.BF_DEBUG_4
out BF_DEBUG_4std_logic
Definition: CMX_top_Base.vhd:510
CMX_top_Base.D_CBL_14_B
out D_CBL_14_Bstd_logic
Definition: CMX_top_Base.vhd:620
CMX_clock_manager.ds
in dsstd_logic
Definition: CMX_clock_manager.vhd:46
CMX_top_Base.P10_6
in P10_6std_logic
Definition: CMX_top_Base.vhd:347
CMX_delay_generator.rd_nwr
in rd_nwrstd_logic
Definition: CMX_delay_generator.vhd:35
CMX_top_Base.BF_DOUT_CTP_50
out BF_DOUT_CTP_50std_logic
Definition: CMX_top_Base.vhd:590
CMX_top_Base.P1_0
in P1_0std_logic
Definition: CMX_top_Base.vhd:116
CMX_top_Base.P12_9
in P12_9std_logic
Definition: CMX_top_Base.vhd:400
daq_collector.BCID_in
in BCID_instd_logic_vector (11 downto 0)
Definition: daq_collector.vhd:33
CMX_top_Base.P8_20
in P8_20std_logic
Definition: CMX_top_Base.vhd:311
CMX_top_Base.P13_2
in P13_2std_logic
Definition: CMX_top_Base.vhd:418
CMX_top_Base.P13_4
in P13_4std_logic
Definition: CMX_top_Base.vhd:420
CMX_top_Base.P11_6
in P11_6std_logic
Definition: CMX_top_Base.vhd:372
CMX_top_Base.BF_SYSMON_14_N
in BF_SYSMON_14_NSTD_LOGIC
Definition: CMX_top_Base.vhd:86
sys_monitor.BF_SYSMON_01_N
in BF_SYSMON_01_NSTD_LOGIC
Definition: sys_monitor.vhd:29
CMX_top_Base.MP2_F04_QUAD_115_TRN_0_CMP
out MP2_F04_QUAD_115_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:750
vme_outreg_notri.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri.vhd:27
CMX_top_Base.P8_1
in P8_1std_logic
Definition: CMX_top_Base.vhd:292
CMX_top_Base.CLK_40MHz08_DSKW_2_BF_LOGIC_CMP
in CLK_40MHz08_DSKW_2_BF_LOGIC_CMPstd_logic
Definition: CMX_top_Base.vhd:500
CMX_top_Base.BF_SYSMON_04_N
in BF_SYSMON_04_NSTD_LOGIC
Definition: CMX_top_Base.vhd:70
CMX_top_Base.P0_15
in P0_15std_logic
Definition: CMX_top_Base.vhd:106
vme_inreg_notri_async.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:30
CMX_clock_manager.buf_clk40_m180o
out buf_clk40_m180ostd_logic
Definition: CMX_clock_manager.vhd:34
CMX_input_module.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:62
CMX_top_Base.P12_11
in P12_11std_logic
Definition: CMX_top_Base.vhd:402
CMX_top_Base.BF_SYSMON_12_P
in BF_SYSMON_12_PSTD_LOGIC
Definition: CMX_top_Base.vhd:81
CMX_top_Base.MP2_F04_QUAD_115_TRN_0_DIR
out MP2_F04_QUAD_115_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:749
vme_inreg.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl.vhd:31
CMX_top_Base.P3_22
in P3_22std_logic
Definition: CMX_top_Base.vhd:188
sys_monitor.ncs
in ncsstd_logic
Definition: sys_monitor.vhd:53
CMX_top_Base.Behavioral.vme_address
std_logic_vector (23 downto 1) vme_address
Definition: CMX_top_Base.vhd:795
CMX_top_Base.P3_2
in P3_2std_logic
Definition: CMX_top_Base.vhd:168
CMX_top_Base.BF_DOUT_CTP_57
out BF_DOUT_CTP_57std_logic
Definition: CMX_top_Base.vhd:597
CMX_top_Base.P14_1
in P14_1std_logic
Definition: CMX_top_Base.vhd:442
CMX_top_Base.D_CBL_25_B
out D_CBL_25_Bstd_logic
Definition: CMX_top_Base.vhd:631
CMX_top_Base.P10_19
in P10_19std_logic
Definition: CMX_top_Base.vhd:360
CMX_top_Base.Behavioral.sys_monitor
sys_monitor
Definition: CMX_top_Base.vhd:961
CMX_top_Base.BF_DOUT_CTP_42
out BF_DOUT_CTP_42std_logic
Definition: CMX_top_Base.vhd:582
CMX_top_Base.P3_13
in P3_13std_logic
Definition: CMX_top_Base.vhd:179
CMX_top_Base.P15_24
in P15_24std_logic
Definition: CMX_top_Base.vhd:490
CMX_top_Base.P9_22
in P9_22std_logic
Definition: CMX_top_Base.vhd:338
CMX_Sum_Et.LOCAL_CABLE_OUT
out LOCAL_CABLE_OUTstd_logic_vector (4 * 26 - 1 downto 0)
Definition: CMX_SumEt.vhd:42
CMX_top_Base.OCB_A12
in OCB_A12std_logic
Definition: CMX_top_Base.vhd:43
CMX_top_Base.P3_4
in P3_4std_logic
Definition: CMX_top_Base.vhd:170
CMX_top_Base.P6_18
in P6_18std_logic
Definition: CMX_top_Base.vhd:259
sys_monitor.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: sys_monitor.vhd:56
CMX_top_Base.P3_0
in P3_0std_logic
Definition: CMX_top_Base.vhd:166
CMX_clock_manager.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_clock_manager.vhd:48
Topo_Data_TX.send_align
in send_alignstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:41
BCID_counter.rd_nwr
in rd_nwrstd_logic
Definition: BCID_counter.vhd:35
CMX_top_Base.P2_17
in P2_17std_logic
Definition: CMX_top_Base.vhd:158
CMX_top_Base.P2_13
in P2_13std_logic
Definition: CMX_top_Base.vhd:154
CMX_top_Base.OCB_A07
in OCB_A07std_logic
Definition: CMX_top_Base.vhd:38
CMX_top_Base.P10_9
in P10_9std_logic
Definition: CMX_top_Base.vhd:350
CMX_top_Base.BF_DOUT_CTP_51
out BF_DOUT_CTP_51std_logic
Definition: CMX_top_Base.vhd:591
vme_outreg.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl.vhd:30
CMX_top_Base.D_CBL_33_B
out D_CBL_33_Bstd_logic
Definition: CMX_top_Base.vhd:641
CMX_top_Base.BF_DOUT_CTP_54
out BF_DOUT_CTP_54std_logic
Definition: CMX_top_Base.vhd:594
CMX_top_Base.OCB_A03
in OCB_A03std_logic
Definition: CMX_top_Base.vhd:34
CMX_top_Base.MP1_F02_QUAD_112_TRN_2_DIR
out MP1_F02_QUAD_112_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:729
CMX_top_Base.BF_TO_FROM_BSPT_1
in BF_TO_FROM_BSPT_1std_logic
Definition: CMX_top_Base.vhd:529
CMX_top_Base.OCB_A22
in OCB_A22std_logic
Definition: CMX_top_Base.vhd:53
CMX_SumET_Topo_Encoder.local_data
in local_datastd_logic_vector (4 * 26 - 1 downto 0)
Definition: CMX_SumET_Topo_Encoder.vhd:28
CMX_top_Base.BF_DOUT_CTP_45
out BF_DOUT_CTP_45std_logic
Definition: CMX_top_Base.vhd:585
sys_monitor.BF_SYSMON_07_P
in BF_SYSMON_07_PSTD_LOGIC
Definition: sys_monitor.vhd:34
CMX_top_Base.P4_22
in P4_22std_logic
Definition: CMX_top_Base.vhd:213
vme_main_hub
Definition: vme_main_hub.vhd:21
Topo_Data_TX.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:57
vme_inreg_notri.write_detect
out write_detectstd_logic
Definition: vme_inreg_rtl_notri.vhd:40
CMX_top_Base.P10_10
in P10_10std_logic
Definition: CMX_top_Base.vhd:351
CMX_top_Base.P12_20
in P12_20std_logic
Definition: CMX_top_Base.vhd:411
CMX_top_Base.P14_8
in P14_8std_logic
Definition: CMX_top_Base.vhd:449
CMX_top_Base.MP2_F08_QUAD_114_TRN_3_DIR
out MP2_F08_QUAD_114_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:747
CMX_top_Base.P0_10
in P0_10std_logic
Definition: CMX_top_Base.vhd:101
CMX_top_Base.P6_14
in P6_14std_logic
Definition: CMX_top_Base.vhd:255
CMX_top_Base.Behavioral.data_vme_from_below_top
arr_16 (1762 downto 0) data_vme_from_below_top
Definition: CMX_top_Base.vhd:863
CMX_top_Base.P5_16
in P5_16std_logic
Definition: CMX_top_Base.vhd:232
CMX_top_Base.P3_8
in P3_8std_logic
Definition: CMX_top_Base.vhd:174
CMX_BASE_VME_BSPT.n_ds0_int
in n_ds0_intstd_logic
Definition: cmx_base_vme_bspt.vhd:28
CMX_top_Base.P13_19
in P13_19std_logic
Definition: CMX_top_Base.vhd:435
CMX_top_Base.BF_DOUT_CTP_60
out BF_DOUT_CTP_60std_logic
Definition: CMX_top_Base.vhd:600
CMX_Sum_Et.ENERGY_REMOTE
in ENERGY_REMOTEstd_logic_vector (26 * 4 - 1 downto 0)
Definition: CMX_SumEt.vhd:23
CMX_top_Base.Behavioral.bus_drive_up_top
std_logic bus_drive_up_top
Definition: CMX_top_Base.vhd:865
CMX_top_Base.P4_19
in P4_19std_logic
Definition: CMX_top_Base.vhd:210
vme_inreg_notri_async.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl_notri_async.vhd:20
CMX_top_Base.P4_23
in P4_23std_logic
Definition: CMX_top_Base.vhd:214
SFP_Data_TXRX.gtx_reset
in gtx_resetstd_logic
Definition: SFP_TXRX.vhd:34
CMX_top_Base.BF_DOUT_CTP_07
out BF_DOUT_CTP_07std_logic
Definition: CMX_top_Base.vhd:545
CMX_top_Base.BF_TO_FROM_BSPT_5
out BF_TO_FROM_BSPT_5std_logic
Definition: CMX_top_Base.vhd:533
CMX_top_Base.MP2_F01_QUAD_113_TRN_0_DIR
out MP2_F01_QUAD_113_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:733
CMX_top_Base.P11_2
in P11_2std_logic
Definition: CMX_top_Base.vhd:368
CMX_top_Base.P2_0
in P2_0std_logic
Definition: CMX_top_Base.vhd:141
CMX_top_Base.D_CBL_07_B
out D_CBL_07_Bstd_logic
Definition: CMX_top_Base.vhd:613
vme_outreg
Definition: vme_outreg_rtl.vhd:15
CMX_top_Base.P15_10
in P15_10std_logic
Definition: CMX_top_Base.vhd:476
SFP_Data_TXRX.local_mmcm_reset_diag
out local_mmcm_reset_diagstd_logic
Definition: SFP_TXRX.vhd:40
CMX_Memory_spy_inhibit.ncs
in ncsstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:42
vme_inreg.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl.vhd:36
CMX_top_Base.D_CBL_62_B
out D_CBL_62_Bstd_logic
Definition: CMX_top_Base.vhd:672
CMX_input_module.quiet
in quietstd_logic
Definition: CMX_input_module.vhd:48
CMX_top_Base.P12_3
in P12_3std_logic
Definition: CMX_top_Base.vhd:394
SFP_Data_TXRX.DFETAP3
in DFETAP3std_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:65
CMX_crate_cable_output_module
Definition: CMX_crate_cable_output_module.vhd:24
CMX_top_Base.P13_24
in P13_24std_logic
Definition: CMX_top_Base.vhd:440
CMX_top_Base.OCB_A16
in OCB_A16std_logic
Definition: CMX_top_Base.vhd:47
CMX_top_Base.P7_2
in P7_2std_logic
Definition: CMX_top_Base.vhd:268
vme_inreg_notri
Definition: vme_inreg_rtl_notri.vhd:19
CMX_top_Base.P1_5
in P1_5std_logic
Definition: CMX_top_Base.vhd:121
CMX_top_Base.P4_24
in P4_24std_logic
Definition: CMX_top_Base.vhd:215
CMX_top_Base.MP1_F07_QUAD_110_TRN_2_CMP
out MP1_F07_QUAD_110_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:714
CMX_top_Base.Behavioral.start_playback
std_logic start_playback
Definition: CMX_top_Base.vhd:941
vme_inreg_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_async_rtl.vhd:29
CMX_top_Base.P12_8
in P12_8std_logic
Definition: CMX_top_Base.vhd:399
CMX_top_Base.P2_24
in P2_24std_logic
Definition: CMX_top_Base.vhd:165
CMX_top_Base.BF_SYSMON_09_P
in BF_SYSMON_09_PSTD_LOGIC
Definition: CMX_top_Base.vhd:75
vme_inreg_async.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_async_rtl.vhd:20
CMX_top_Base.P4_9
in P4_9std_logic
Definition: CMX_top_Base.vhd:200
SFP_Data_TXRX.DFEEYEDACMON
out DFEEYEDACMONstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:59
CMX_crate_cable_output_module.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_crate_cable_output_module.vhd:43
CMX_top_Base.Behavioral.ds
std_logic ds
Definition: CMX_top_Base.vhd:792
CMX_top_Base.BF_DOUT_CTP_17
out BF_DOUT_CTP_17std_logic
Definition: CMX_top_Base.vhd:555
vme_outreg_notri.ncs
in ncsstd_logic
Definition: vme_outreg_rtl_notri.vhd:22
CMX_top_Base.D_CBL_09_B
out D_CBL_09_Bstd_logic
Definition: CMX_top_Base.vhd:615
CMX_top_Base.P7_17
in P7_17std_logic
Definition: CMX_top_Base.vhd:283
CMX_top_Base.BF_SYSMON_01_P
in BF_SYSMON_01_PSTD_LOGIC
Definition: CMX_top_Base.vhd:65
CMX_Sum_Et.T_MISS_E_MIN
in T_MISS_E_MINarr_ctr_31bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:33
CMX_BASE_VME_BSPT.geoadd_0
in geoadd_0std_logic
Definition: cmx_base_vme_bspt.vhd:27
CMX_input_module.start_playback
in start_playbackstd_logic
Definition: CMX_input_module.vhd:51
CMX_top_Base.BF_DOUT_CTP_31
out BF_DOUT_CTP_31std_logic
Definition: CMX_top_Base.vhd:569
CMX_top_Base.BF_DOUT_CTP_38
out BF_DOUT_CTP_38std_logic
Definition: CMX_top_Base.vhd:578
CMX_top_Base.D_CBL_22_B
out D_CBL_22_Bstd_logic
Definition: CMX_top_Base.vhd:628
CMX_top_Base.P1_24
in P1_24std_logic
Definition: CMX_top_Base.vhd:140
CMX_top_Base.BF_DOUT_CTP_37
out BF_DOUT_CTP_37std_logic
Definition: CMX_top_Base.vhd:577
CMX_top_Base.P10_14
in P10_14std_logic
Definition: CMX_top_Base.vhd:355
CMX_top_Base.P1_23
in P1_23std_logic
Definition: CMX_top_Base.vhd:139
CMX_clock_manager.bus_drive
out bus_drivestd_logic
Definition: CMX_clock_manager.vhd:50
CMX_top_Base.MP2_F08_QUAD_114_TRN_3_CMP
out MP2_F08_QUAD_114_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:748
CMX_top_Base.P11_10
in P11_10std_logic
Definition: CMX_top_Base.vhd:376
CMX_top_Base.D_CBL_83_B
out D_CBL_83_Bstd_logic
Definition: CMX_top_Base.vhd:691
CMX_top_Base.P6_3
in P6_3std_logic
Definition: CMX_top_Base.vhd:244
CMX_Memory_spy_inhibit.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_Memory_spy_inhibit.vhd:45
CMX_top_Base.BF_DEBUG_8
out BF_DEBUG_8std_logic
Definition: CMX_top_Base.vhd:514
CMX_top_Base.BF_DOUT_CTP_29
out BF_DOUT_CTP_29std_logic
Definition: CMX_top_Base.vhd:567
SFP_Data_TXRX.DFEDLYOVRD
in DFEDLYOVRDstd_logic
Definition: SFP_TXRX.vhd:58
sys_monitor.ds
in dsstd_logic
Definition: sys_monitor.vhd:55
CMX_top_Base.BF_REQ_CABLE_3_INPUT
out BF_REQ_CABLE_3_INPUTstd_logic
Definition: CMX_top_Base.vhd:522
CMX_top_Base.D_CBL_82_B
out D_CBL_82_Bstd_logic
Definition: CMX_top_Base.vhd:662
CMX_top_Base.BF_DOUT_CTP_35
out BF_DOUT_CTP_35std_logic
Definition: CMX_top_Base.vhd:575
CMX_top_Base.D_CBL_69_B
out D_CBL_69_Bstd_logic
Definition: CMX_top_Base.vhd:679
CMX_top_Base.P3_1
in P3_1std_logic
Definition: CMX_top_Base.vhd:167
daq_glink.nslices
in nslicesunsigned (7 downto 0)
Definition: daq_glink.vhd:36
CMX_top_Base.BF_DOUT_CTP_26
out BF_DOUT_CTP_26std_logic
Definition: CMX_top_Base.vhd:564
CMX_top_Base.P14_4
in P14_4std_logic
Definition: CMX_top_Base.vhd:445
CMX_top_Base.BF_DOUT_CTP_39
out BF_DOUT_CTP_39std_logic
Definition: CMX_top_Base.vhd:579
CMX_top_Base.P4_15
in P4_15std_logic
Definition: CMX_top_Base.vhd:206
Topo_Data_TX.GTX_RX_READY_OUT
out GTX_RX_READY_OUTstd_logic
Definition: Topo_Data_TX.vhd:32
CMX_top_Base.P1_22
in P1_22std_logic
Definition: CMX_top_Base.vhd:138
CMX_top_Base.BF_DOUT_CTP_23
out BF_DOUT_CTP_23std_logic
Definition: CMX_top_Base.vhd:561
CMX_top_Base.P15_23
in P15_23std_logic
Definition: CMX_top_Base.vhd:489
SFP_Data_TXRX.DFECLKDLYADJ
in DFECLKDLYADJstd_logic_vector (5 downto 0)
Definition: SFP_TXRX.vhd:56
CMX_top_Base.P6_8
in P6_8std_logic
Definition: CMX_top_Base.vhd:249
CMX_top_Base.P5_0
in P5_0std_logic
Definition: CMX_top_Base.vhd:216
CMX_top_Base.P1_15
in P1_15std_logic
Definition: CMX_top_Base.vhd:131
CMX_top_Base.MP2_F09_QUAD_114_TRN_0_DIR
out MP2_F09_QUAD_114_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:741
CMX_top_Base.BF_DOUT_CTP_16
out BF_DOUT_CTP_16std_logic
Definition: CMX_top_Base.vhd:554
CMX_input_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_input_module.vhd:31
CMX_clock_manager.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_clock_manager.vhd:49
CMX_top_Base.P4_8
in P4_8std_logic
Definition: CMX_top_Base.vhd:199
CMX_top_Base.P4_4
in P4_4std_logic
Definition: CMX_top_Base.vhd:195
vme_inreg_notri_async.ncs
in ncsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:25
CMX_top_Base.P3_7
in P3_7std_logic
Definition: CMX_top_Base.vhd:173
SFP_Data_TXRX.local_pll_lock_out
out local_pll_lock_outstd_logic
Definition: SFP_TXRX.vhd:35
CMX_rate_counter_inhibit.bus_drive
out bus_drivestd_logic
Definition: CMX_rate_counter_inhibit.vhd:41
CMX_top_Base.P5_11
in P5_11std_logic
Definition: CMX_top_Base.vhd:227
CMX_top_Base.P10_12
in P10_12std_logic
Definition: CMX_top_Base.vhd:353
CMX_top_Base.P5_18
in P5_18std_logic
Definition: CMX_top_Base.vhd:234
CMX_top_Base.D_CBL_03_B
out D_CBL_03_Bstd_logic
Definition: CMX_top_Base.vhd:609
CMX_top_Base.P10_13
in P10_13std_logic
Definition: CMX_top_Base.vhd:354
CMX_top_Base.P0_13
in P0_13std_logic
Definition: CMX_top_Base.vhd:104
CMX_rate_counter_inhibit.ncs
in ncsstd_logic
Definition: CMX_rate_counter_inhibit.vhd:35
CMX_top_Base.P8_3
in P8_3std_logic
Definition: CMX_top_Base.vhd:294
CMX_top_Base.Behavioral.counter_values
std_logic_vector (numactchan - 1 downto 0) counter_values
Definition: CMX_top_Base.vhd:1027
sys_monitor.BF_SYSMON_10_N
in BF_SYSMON_10_NSTD_LOGIC
Definition: sys_monitor.vhd:41
CMX_delay_generator.upload_delays
out upload_delaysstd_logic
Definition: CMX_delay_generator.vhd:42
SFP_Data_TXRX.RXN_IN
in RXN_INstd_logic
Definition: SFP_TXRX.vhd:42
CMX_top_Base.P0_19
in P0_19std_logic
Definition: CMX_top_Base.vhd:110
CMX_top_Base.D_CBL_54_B
out D_CBL_54_Bstd_logic
Definition: CMX_top_Base.vhd:664
CMX_top_Base.P7_0
in P7_0std_logic
Definition: CMX_top_Base.vhd:266
CMX_top_Base.D_CBL_30_B
out D_CBL_30_Bstd_logic
Definition: CMX_top_Base.vhd:638
CMX_top_Base.P3_10
in P3_10std_logic
Definition: CMX_top_Base.vhd:176
CMX_top_Base.P12_7
in P12_7std_logic
Definition: CMX_top_Base.vhd:398
CMX_input_module.counter_values
out counter_valuesstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:42
CMX_clock_manager.ncs
in ncsstd_logic
Definition: CMX_clock_manager.vhd:44
CMX_top_Base.P7_15
in P7_15std_logic
Definition: CMX_top_Base.vhd:281
vme_outreg_notri.ds
in dsstd_logic
Definition: vme_outreg_rtl_notri.vhd:24
CMX_top_Base.P3_24
in P3_24std_logic
Definition: CMX_top_Base.vhd:190
CMX_top_Base.P13_22
in P13_22std_logic
Definition: CMX_top_Base.vhd:438
CMX_Sum_Et.T_MISS_E_MAX
in T_MISS_E_MAXarr_ctr_31bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:34
vme_main_hub.data_vme_going_below
out data_vme_going_belowstd_logic_vector (15 downto 0)
Definition: vme_main_hub.vhd:34
CMX_top_Base.P14_5
in P14_5std_logic
Definition: CMX_top_Base.vhd:446
SFP_Data_TXRX.TXPOSTEMPHASIS_IN
in TXPOSTEMPHASIS_INstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:53
CMX_BASE_VME_BSPT.vme_address
in vme_addressstd_logic_vector (23 downto 1)
Definition: cmx_base_vme_bspt.vhd:30
CMX_Sum_Et.BCID_in
in BCID_instd_logic_vector (11 downto 0)
Definition: CMX_SumEt.vhd:43
CMX_Sum_Et.T_SUM_E_MIN
in T_SUM_E_MINarr_ctr_15bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:35
CMX_top_Base.D_CBL_23_B
out D_CBL_23_Bstd_logic
Definition: CMX_top_Base.vhd:629
CMX_top_Base.Behavioral.start_playback_r1
std_logic start_playback_r1
Definition: CMX_top_Base.vhd:941
CMX_top_Base.D_CBL_73_B
out D_CBL_73_Bstd_logic
Definition: CMX_top_Base.vhd:683
BCID_counter.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: BCID_counter.vhd:39
CMX_top_Base.Behavioral.data_vme_going_below
std_logic_vector (15 downto 0) data_vme_going_below
Definition: CMX_top_Base.vhd:867
CMX_top_Base.P0_17
in P0_17std_logic
Definition: CMX_top_Base.vhd:108
vme_outreg_notri.width
widthinteger :=16
Definition: vme_outreg_rtl_notri.vhd:17
CMX_top_Base.P15_20
in P15_20std_logic
Definition: CMX_top_Base.vhd:486
CMX_top_Base.IEEE
_library_ IEEEIEEE
Definition: CMX_top_Base.vhd:8
CMX_top_Base.P4_10
in P4_10std_logic
Definition: CMX_top_Base.vhd:201
vme_inreg_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_async_rtl.vhd:34
vme_outreg_notri.bus_drive
out bus_drivestd_logic
Definition: vme_outreg_rtl_notri.vhd:28
CMX_top_Base.P11_14
in P11_14std_logic
Definition: CMX_top_Base.vhd:380
CMX_delay_generator.bus_drive
out bus_drivestd_logic
Definition: CMX_delay_generator.vhd:40
CMX_top_Base.P2_11
in P2_11std_logic
Definition: CMX_top_Base.vhd:152
CMX_top_Base.MP1_F00_QUAD_112_TRN_3_CMP
out MP1_F00_QUAD_112_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:732
CMX_top_Base.Behavioral.IOB
string IOB
Definition: CMX_top_Base.vhd:774
SFP_Data_TXRX.direction
directionstd_logic
Definition: SFP_TXRX.vhd:24
CMX_top_Base.P9_4
in P9_4std_logic
Definition: CMX_top_Base.vhd:320
CMX_top_Base.P5_7
in P5_7std_logic
Definition: CMX_top_Base.vhd:223
CMX_top_Base.Behavioral.quiet
std_logic quiet
Definition: CMX_top_Base.vhd:1033
CMX_top_Base.BF_DOUT_CTP_28
out BF_DOUT_CTP_28std_logic
Definition: CMX_top_Base.vhd:566
vme_inreg_notri_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:35
vme_outreg.width
widthinteger :=16
Definition: vme_outreg_rtl.vhd:18
CMX_top_Base.P7_16
in P7_16std_logic
Definition: CMX_top_Base.vhd:282
Topo_Data_TX.GTXRXRESET_IN
in GTXRXRESET_INstd_logic
Definition: Topo_Data_TX.vhd:30
Topo_Data_TX.MGTREFCLK_PAD_P_IN
in MGTREFCLK_PAD_P_INstd_logic_vector (num_GTX_groups - 1 downto 0)
Definition: Topo_Data_TX.vhd:28
sys_monitor.BF_SYSMON_04_N
in BF_SYSMON_04_NSTD_LOGIC
Definition: sys_monitor.vhd:33
CMX_top_Base.P11_19
in P11_19std_logic
Definition: CMX_top_Base.vhd:385
CMX_top_Base.P0_1
in P0_1std_logic
Definition: CMX_top_Base.vhd:92
CMX_top_Base.P15_12
in P15_12std_logic
Definition: CMX_top_Base.vhd:478
glink_interface.DAQ_DAV
in DAQ_DAVstd_logic
Definition: glink_interface.vhd:24
CMX_version.bus_drive
out bus_drivestd_logic
Definition: CMX_version.vhd:27
vme_outreg_notri_async.bus_drive
out bus_drivestd_logic
Definition: vme_outreg_rtl_notri_async.vhd:28
CMX_top_Base.P2_23
in P2_23std_logic
Definition: CMX_top_Base.vhd:164
CMX_top_Base.D_CBL_08_B
in D_CBL_08_Bstd_logic
Definition: CMX_top_Base.vhd:614
CMX_top_Base.OCB_A05
in OCB_A05std_logic
Definition: CMX_top_Base.vhd:36
CMX_top_Base.P2_22
in P2_22std_logic
Definition: CMX_top_Base.vhd:163
CMX_delay_generator.ds
in dsstd_logic
Definition: CMX_delay_generator.vhd:36
CMX_top_Base.Behavioral.vme_outreg_notri
vme_outreg_notri
Definition: CMX_top_Base.vhd:918
sys_monitor.BF_SYSMON_14_P
in BF_SYSMON_14_PSTD_LOGIC
Definition: sys_monitor.vhd:48
CMX_top_Base.Behavioral.data_from_vme_test_rw
std_logic_vector (15 downto 0) data_from_vme_test_rw
Definition: CMX_top_Base.vhd:934
CMX_top_Base.P2_21
in P2_21std_logic
Definition: CMX_top_Base.vhd:162
CMX_top_Base.P8_15
in P8_15std_logic
Definition: CMX_top_Base.vhd:306
vme_local_switch.data_vme_up
out data_vme_upstd_logic_vector (15 downto 0)
--! connect this to
Definition: vme_local_switch.vhd:24
Topo_Data_TX.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:55
CMX_top_Base.P1_17
in P1_17std_logic
Definition: CMX_top_Base.vhd:133
CMX_top_Base.P12_18
in P12_18std_logic
Definition: CMX_top_Base.vhd:409
CMX_top_Base.P8_6
in P8_6std_logic
Definition: CMX_top_Base.vhd:297
CMX_rate_counter_inhibit.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_rate_counter_inhibit.vhd:38
CMX_top_Base.BF_DOUT_CTP_24
out BF_DOUT_CTP_24std_logic
Definition: CMX_top_Base.vhd:562
daq_glink.bc_counter
in bc_counterunsigned (11 downto 0)
Definition: daq_glink.vhd:27
CMX_top_Base.BF_TO_TP_DAQ_SLINK_RETURN_CMP
in BF_TO_TP_DAQ_SLINK_RETURN_CMPstd_logic
Definition: CMX_top_Base.vhd:694
CMX_top_Base.P3_5
in P3_5std_logic
Definition: CMX_top_Base.vhd:171
Topo_Data_TX.GTX_TX_READY_OUT
out GTX_TX_READY_OUTstd_logic
Definition: Topo_Data_TX.vhd:31
CMX_top_Base.P4_6
in P4_6std_logic
Definition: CMX_top_Base.vhd:197
CMX_top_Base.BF_SYSMON_09_N
in BF_SYSMON_09_NSTD_LOGIC
Definition: CMX_top_Base.vhd:76
CMX_top_Base.P14_14
in P14_14std_logic
Definition: CMX_top_Base.vhd:455
CMX_top_Base.D_CBL_78_B
out D_CBL_78_Bstd_logic
Definition: CMX_top_Base.vhd:688
CMX_top_Base.P13_23
in P13_23std_logic
Definition: CMX_top_Base.vhd:439
CMX_top_Base.OCB_A18
in OCB_A18std_logic
Definition: CMX_top_Base.vhd:49
vme_inreg_notri_async.bus_drive
out bus_drivestd_logic
Definition: vme_inreg_rtl_notri_async.vhd:32
CMX_top_Base.BF_DOUT_CTP_53
out BF_DOUT_CTP_53std_logic
Definition: CMX_top_Base.vhd:593
CMX_top_Base.MP2_F02_QUAD_115_TRN_2_DIR
out MP2_F02_QUAD_115_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:753
CMX_top_Base.P15_16
in P15_16std_logic
Definition: CMX_top_Base.vhd:482
CMX_clock_manager.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_clock_manager.vhd:47
CMX_top_Base.P15_14
in P15_14std_logic
Definition: CMX_top_Base.vhd:480
CMX_top_Base.P13_0
in P13_0std_logic
Definition: CMX_top_Base.vhd:416
CMX_top_Base.P7_14
in P7_14std_logic
Definition: CMX_top_Base.vhd:280
BCID_counter.clk_40
in clk_40std_logic
Definition: BCID_counter.vhd:31
CMX_top_Base.BF_REQ_CABLE_1_INPUT
out BF_REQ_CABLE_1_INPUTstd_logic
Definition: CMX_top_Base.vhd:520
CMX_top_Base.P11_16
in P11_16std_logic
Definition: CMX_top_Base.vhd:382
CMX_top_Base.Behavioral.read_detect_outreg_test
std_logic read_detect_outreg_test
Definition: CMX_top_Base.vhd:812
CMX_top_Base.OCB_A17
in OCB_A17std_logic
Definition: CMX_top_Base.vhd:48
CMX_top_Base.Behavioral.del_register
del_register_type del_register
Definition: CMX_top_Base.vhd:1028
CMX_Sum_Et.SUM_ET_RES_THR
in SUM_ET_RES_THRarr_ctr_15bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:30
CMX_top_Base.OCB_A23
in OCB_A23std_logic
Definition: CMX_top_Base.vhd:54
CMX_top_Base.OCB_A01
in OCB_A01std_logic
Definition: CMX_top_Base.vhd:32
vme_outreg_notri_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:26
CMX_top_Base.MP2_F09_QUAD_114_TRN_0_CMP
out MP2_F09_QUAD_114_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:742
CMX_top_Base.P9_20
in P9_20std_logic
Definition: CMX_top_Base.vhd:336
CMX_top_Base.P0_7
in P0_7std_logic
Definition: CMX_top_Base.vhd:98
daq_glink.clk4000
in clk4000std_logic
Definition: daq_glink.vhd:31
sys_monitor.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: sys_monitor.vhd:57
CMX_crate_cable_output_module.data
in datastd_logic_vector (numbits_in_RTM_connector * 2 * num_RTM_cables - 1 downto 0)
Definition: CMX_crate_cable_output_module.vhd:28
CMX_top_Base.D_CBL_15_B
out D_CBL_15_Bstd_logic
Definition: CMX_top_Base.vhd:621
CMX_top_Base.P0_22
in P0_22std_logic
Definition: CMX_top_Base.vhd:113
SFP_Data_TXRX.clk120_out
out clk120_outstd_logic
Definition: SFP_TXRX.vhd:47
CMX_top_Base.P14_20
in P14_20std_logic
Definition: CMX_top_Base.vhd:461
CMX_top_Base.CLK_120MHz000_XTAL_1_BF_TRNCV_CMP
in CLK_120MHz000_XTAL_1_BF_TRNCV_CMPstd_logic
Definition: CMX_top_Base.vhd:703
CMX_top_Base.P8_13
in P8_13std_logic
Definition: CMX_top_Base.vhd:304
CMX_top_Base.BF_DOUT_CTP_18
out BF_DOUT_CTP_18std_logic
Definition: CMX_top_Base.vhd:556
CMX_top_Base.BF_DOUT_CTP_06
out BF_DOUT_CTP_06std_logic
Definition: CMX_top_Base.vhd:544
vme_inreg.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl.vhd:28
CMX_delay_generator.clk40
in clk40std_logic
Definition: CMX_delay_generator.vhd:33
CMX_top_Base.BF_DOUT_CTP_27
out BF_DOUT_CTP_27std_logic
Definition: CMX_top_Base.vhd:565
CMX_top_Base.BF_DOUT_CTP_43
out BF_DOUT_CTP_43std_logic
Definition: CMX_top_Base.vhd:583
CMX_clock_manager.buf_clk200
out buf_clk200std_logic
Definition: CMX_clock_manager.vhd:38
CMX_top_Base.MP2_F03_QUAD_113_TRN_1_DIR
out MP2_F03_QUAD_113_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:735
CMX_top_Base.D_CBL_49_B
out D_CBL_49_Bstd_logic
Definition: CMX_top_Base.vhd:657
Topo_Data_TX.ext_trigger
in ext_triggerstd_logic
Definition: Topo_Data_TX.vhd:50
CMX_top_Base.BF_SYSMON_11_N
in BF_SYSMON_11_NSTD_LOGIC
Definition: CMX_top_Base.vhd:80
CMX_top_Base.RXN_IN
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: CMX_top_Base.vhd:762
CMX_Sum_Et.BCID_delayed
out BCID_delayedstd_logic_vector (11 downto 0)
Definition: CMX_SumEt.vhd:44
CMX_top_Base.P3_19
in P3_19std_logic
Definition: CMX_top_Base.vhd:185
CMX_top_Base.Behavioral.data_to_vme_test_r
std_logic_vector (15 downto 0) data_to_vme_test_r
Definition: CMX_top_Base.vhd:939
CMX_top_Base.MP2_F11_QUAD_114_TRN_1_CMP
out MP2_F11_QUAD_114_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:744
CMX_top_Base.P2_16
in P2_16std_logic
Definition: CMX_top_Base.vhd:157
CMX_top_Base.P9_14
in P9_14std_logic
Definition: CMX_top_Base.vhd:330
SFP_Data_TXRX.DFETAP3MONITOR
out DFETAP3MONITORstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:66
vme_local_switch
Definition: vme_local_switch.vhd:22
CMX_top_Base.D_CBL_11_B
out D_CBL_11_Bstd_logic
Definition: CMX_top_Base.vhd:617
daq_collector.energy_local
in energy_localstd_logic_vector (26 * 4 - 1 downto 0)
Definition: daq_collector.vhd:25
CMX_top_Base.P2_7
in P2_7std_logic
Definition: CMX_top_Base.vhd:148
CMX_top_Base.P12_10
in P12_10std_logic
Definition: CMX_top_Base.vhd:401
BCID_counter.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: BCID_counter.vhd:38
CMX_top_Base.P10_24
in P10_24std_logic
Definition: CMX_top_Base.vhd:365
Topo_Data_TX.TXP_OUT
out TXP_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:37
CMX_top_Base.P0_0
in P0_0std_logic
Definition: CMX_top_Base.vhd:91
daq_glink.l1a
in l1astd_logic
Definition: daq_glink.vhd:28
vme_outreg_notri_async
Definition: vme_outreg_rtl_notri_async.vhd:16
CMX_top_Base.P9_1
in P9_1std_logic
Definition: CMX_top_Base.vhd:317
CMX_top_Base.MP1_F00_QUAD_112_TRN_3_DIR
out MP1_F00_QUAD_112_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:731
BCID_counter.reset
in resetstd_logic
Definition: BCID_counter.vhd:30
CMX_top_Base.P11_5
in P11_5std_logic
Definition: CMX_top_Base.vhd:371
CMX_top_Base.MP1_F06_QUAD_112_TRN_1_CMP
out MP1_F06_QUAD_112_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:728
CMX_top_Base.P14_16
in P14_16std_logic
Definition: CMX_top_Base.vhd:457
CMX_top_Base.BF_SYSMON_11_P
in BF_SYSMON_11_PSTD_LOGIC
Definition: CMX_top_Base.vhd:79
SFP_Data_TXRX.GTX_RX_READY_OUT
out GTX_RX_READY_OUTstd_logic
Definition: SFP_TXRX.vhd:37
sys_monitor.BF_SYSMON_01_P
in BF_SYSMON_01_PSTD_LOGIC
Definition: sys_monitor.vhd:28
CMX_delay_generator.ncs
in ncsstd_logic
Definition: CMX_delay_generator.vhd:34
CMX_top_Base.D_CBL_34_B
out D_CBL_34_Bstd_logic
Definition: CMX_top_Base.vhd:642
CMX_top_Base.BF_DOUT_CTP_58
out BF_DOUT_CTP_58std_logic
Definition: CMX_top_Base.vhd:598
CMX_top_Base.P8_2
in P8_2std_logic
Definition: CMX_top_Base.vhd:293
CMX_top_Base.BF_DOUT_CTP_10
out BF_DOUT_CTP_10std_logic
Definition: CMX_top_Base.vhd:548
vme_outreg_notri.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl_notri.vhd:30
CMX_top_Base.OCB_SYS_RESET_B
in OCB_SYS_RESET_Bstd_logic
Definition: CMX_top_Base.vhd:60
CMX_top_Base.P10_1
in P10_1std_logic
Definition: CMX_top_Base.vhd:342
CMX_top_Base.P7_22
in P7_22std_logic
Definition: CMX_top_Base.vhd:288
CMX_Sum_Et.par_err
in par_errstd_logic_vector (1 downto 0)
Definition: CMX_SumEt.vhd:49
SFP_Data_TXRX.DFETAP1
in DFETAP1std_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:61
CMX_BASE_VME_BSPT
Definition: cmx_base_vme_bspt.vhd:24
CMX_Sum_Et.SUM_ET_THR
in SUM_ET_THRarr_ctr_15bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:29
CMX_top_Base.P15_4
in P15_4std_logic
Definition: CMX_top_Base.vhd:470
CMX_top_Base.D_CBL_70_B
out D_CBL_70_Bstd_logic
Definition: CMX_top_Base.vhd:680
CMX_top_Base.P3_3
in P3_3std_logic
Definition: CMX_top_Base.vhd:169
BCID_counter.ncs
in ncsstd_logic
Definition: BCID_counter.vhd:34
vme_outreg.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl.vhd:27
vme_local_switch.bus_drive_up
out bus_drive_upstd_logic
or of all bus drive requests from below
Definition: vme_local_switch.vhd:38
CMX_top_Base.BF_DOUT_CTP_03
out BF_DOUT_CTP_03std_logic
Definition: CMX_top_Base.vhd:541
CMX_top_Base.D_CBL_65_B
out D_CBL_65_Bstd_logic
Definition: CMX_top_Base.vhd:675
CMX_clock_manager.buf_clk40
out buf_clk40std_logic
Definition: CMX_clock_manager.vhd:32
CMX_top_Base.P14_22
in P14_22std_logic
Definition: CMX_top_Base.vhd:463
CMX_top_Base.BUF_TTC_BNCH_CNT_RES
in BUF_TTC_BNCH_CNT_RESstd_logic
Definition: CMX_top_Base.vhd:699
CMX_top_Base.BF_DEBUG_9
out BF_DEBUG_9std_logic
Definition: CMX_top_Base.vhd:515
CMX_top_Base.P12_22
in P12_22std_logic
Definition: CMX_top_Base.vhd:413
CMX_top_Base.D_CBL_51_B
out D_CBL_51_Bstd_logic
Definition: CMX_top_Base.vhd:659
CMX_top_Base.P6_22
in P6_22std_logic
Definition: CMX_top_Base.vhd:263
CMX_top_Base.P11_22
in P11_22std_logic
Definition: CMX_top_Base.vhd:388
CMX_top_Base.P13_15
in P13_15std_logic
Definition: CMX_top_Base.vhd:431
CMX_Memory_spy_inhibit.buf_clk40
in buf_clk40std_logic
Definition: CMX_Memory_spy_inhibit.vhd:40
CMX_top_Base.P10_8
in P10_8std_logic
Definition: CMX_top_Base.vhd:349
CMX_top_Base.D_CBL_72_B
out D_CBL_72_Bstd_logic
Definition: CMX_top_Base.vhd:682
CMX_top_Base.D_CBL_00_B
out D_CBL_00_Bstd_logic
Definition: CMX_top_Base.vhd:606
CMX_top_Base.BF_DEBUG_5
out BF_DEBUG_5std_logic
Definition: CMX_top_Base.vhd:511
CMX_top_Base.MP2_F10_QUAD_114_TRN_2_CMP
out MP2_F10_QUAD_114_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:746
daq_glink.RAM_global_offset
in RAM_global_offsetunsigned (7 downto 0)
Definition: daq_glink.vhd:34
CMX_top_Base.P11_21
in P11_21std_logic
Definition: CMX_top_Base.vhd:387
CMX_top_Base.P12_16
in P12_16std_logic
Definition: CMX_top_Base.vhd:407
CMX_top_Base.MP1_F10_QUAD_111_TRN_2_CMP
out MP1_F10_QUAD_111_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:722
CMX_top_Base.P9_16
in P9_16std_logic
Definition: CMX_top_Base.vhd:332
CMX_top_Base.P0_21
in P0_21std_logic
Definition: CMX_top_Base.vhd:112
CMX_top_Base.BF_SYSMON_07_P
in BF_SYSMON_07_PSTD_LOGIC
Definition: CMX_top_Base.vhd:71
CMX_input_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:60
CMX_top_Base.D_CBL_77_B
out D_CBL_77_Bstd_logic
Definition: CMX_top_Base.vhd:687
CMX_top_Base.D_CBL_41_B
out D_CBL_41_Bstd_logic
Definition: CMX_top_Base.vhd:649
CMX_top_Base.P1_6
in P1_6std_logic
Definition: CMX_top_Base.vhd:122
daq_collector.energy_total
in energy_totalarr_ctr_15bit (5 downto 0)
Definition: daq_collector.vhd:26
CMX_top_Base.P13_8
in P13_8std_logic
Definition: CMX_top_Base.vhd:424
CMX_top_Base.D_CBL_53_B
out D_CBL_53_Bstd_logic
Definition: CMX_top_Base.vhd:661
CMX_input_module.ncs
in ncsstd_logic
Definition: CMX_input_module.vhd:57
CMX_top_Base.P15_13
in P15_13std_logic
Definition: CMX_top_Base.vhd:479
CMX_rate_counter_inhibit.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_rate_counter_inhibit.vhd:39
CMX_crate_cable_output_module.ddr_data_out
out ddr_data_outarr_RTM (num_RTM_cables - 1 downto 0)
Definition: CMX_crate_cable_output_module.vhd:30
CMX_top_Base.P8_5
in P8_5std_logic
Definition: CMX_top_Base.vhd:296
CMX_top_Base.BF_DEBUG_0
out BF_DEBUG_0std_logic
Definition: CMX_top_Base.vhd:506
sys_monitor.BF_SYSMON_08_N
in BF_SYSMON_08_NSTD_LOGIC
Definition: sys_monitor.vhd:37
CMX_rate_counter_inhibit.counter_inhibit
out counter_inhibitstd_logic
Definition: CMX_rate_counter_inhibit.vhd:31
CMX_top_Base.P3_20
in P3_20std_logic
Definition: CMX_top_Base.vhd:186
CMX_top_Base.P10_21
in P10_21std_logic
Definition: CMX_top_Base.vhd:362
CMX_top_Base.P11_12
in P11_12std_logic
Definition: CMX_top_Base.vhd:378
CMX_top_Base.MP1_F09_QUAD_111_TRN_0_DIR
out MP1_F09_QUAD_111_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:717
CMX_top_Base.OCB_A08
in OCB_A08std_logic
Definition: CMX_top_Base.vhd:39
CMX_top_Base.BF_REQ_CTP_1_INPUT
out BF_REQ_CTP_1_INPUTstd_logic
Definition: CMX_top_Base.vhd:518
CMX_top_Base.BF_LED_REQ_3
out BF_LED_REQ_3std_logic
Definition: CMX_top_Base.vhd:526
CMX_top_Base.Behavioral.upload_delays
std_logic upload_delays
Definition: CMX_top_Base.vhd:1029
CMX_rate_counter_inhibit.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_rate_counter_inhibit.vhd:40
CMX_top_Base.BF_TO_FROM_BSPT_7
out BF_TO_FROM_BSPT_7std_logic
Definition: CMX_top_Base.vhd:535
CMX_top_Base.P4_11
in P4_11std_logic
Definition: CMX_top_Base.vhd:202
CMX_top_Base.BF_DOUT_CTP_25
out BF_DOUT_CTP_25std_logic
Definition: CMX_top_Base.vhd:563
CMX_top_Base.D_CBL_63_B
out D_CBL_63_Bstd_logic
Definition: CMX_top_Base.vhd:673
CMX_input_module.ODATA_first_half
out ODATA_first_halfarr_2Xword (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:35
CMX_rate_counter_inhibit.ds
in dsstd_logic
Definition: CMX_rate_counter_inhibit.vhd:37
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_114_CMP
in CLK_320MHz64_LHC_BF_QUAD_114_CMPstd_logic
Definition: CMX_top_Base.vhd:760
sys_monitor.BF_SYSMON_14_N
in BF_SYSMON_14_NSTD_LOGIC
Definition: sys_monitor.vhd:49
CMX_Memory_spy_inhibit.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_Memory_spy_inhibit.vhd:46
CMX_rate_counter_inhibit
Definition: CMX_rate_counter_inhibit.vhd:29
CMX_top_Base.BF_SYSMON_07_N
in BF_SYSMON_07_NSTD_LOGIC
Definition: CMX_top_Base.vhd:72
CMX_top_Base.P14_24
in P14_24std_logic
Definition: CMX_top_Base.vhd:465
glink_interface.ROI_BYTE
out ROI_BYTEstd_logic_vector (7 downto 0)
Definition: glink_interface.vhd:27
vme_inreg.ds
in dsstd_logic
Definition: vme_inreg_rtl.vhd:29
SFP_Data_TXRX.clk40_in
in clk40_instd_logic
Definition: SFP_TXRX.vhd:48
CMX_top_Base.P14_18
in P14_18std_logic
Definition: CMX_top_Base.vhd:459
CMX_top_Base.P7_23
in P7_23std_logic
Definition: CMX_top_Base.vhd:289
sys_monitor.BF_SYSMON_08_P
in BF_SYSMON_08_PSTD_LOGIC
Definition: sys_monitor.vhd:36
CMX_flavor_package
Definition: CMX_flavor_package.vhd:19
CMX_top_Base.P5_12
in P5_12std_logic
Definition: CMX_top_Base.vhd:228
CMX_top_Base.P13_11
in P13_11std_logic
Definition: CMX_top_Base.vhd:427
daq_glink.reset
in resetstd_logic
Definition: daq_glink.vhd:33
daq_collector.energy_ovflw
in energy_ovflwstd_logic_vector (5 downto 0)
Definition: daq_collector.vhd:27
SFP_Data_TXRX.DFETAP4MONITOR
out DFETAP4MONITORstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:68
vme_inreg_notri.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl_notri.vhd:21
CMX_top_Base.MP1_F05_QUAD_110_TRN_3_DIR
out MP1_F05_QUAD_110_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:715
CMX_top_Base.P2_10
in P2_10std_logic
Definition: CMX_top_Base.vhd:151
CMX_top_Base.P3_18
in P3_18std_logic
Definition: CMX_top_Base.vhd:184
CMX_top_Base.P3_12
in P3_12std_logic
Definition: CMX_top_Base.vhd:178
CMX_top_Base.P8_17
in P8_17std_logic
Definition: CMX_top_Base.vhd:308
CMX_top_Base.BF_DOUT_CTP_20
out BF_DOUT_CTP_20std_logic
Definition: CMX_top_Base.vhd:558
CMX_top_Base.BF_SYSMON_15_N
in BF_SYSMON_15_NSTD_LOGIC
Definition: CMX_top_Base.vhd:88
CMX_top_Base.P13_5
in P13_5std_logic
Definition: CMX_top_Base.vhd:421
CMX_top_Base.P13_14
in P13_14std_logic
Definition: CMX_top_Base.vhd:430
vme_main_hub.data_vme_from_below
in data_vme_from_belowstd_logic_vector (15 downto 0)
--! input: ORed
Definition: vme_main_hub.vhd:25
CMX_top_Base.P11_11
in P11_11std_logic
Definition: CMX_top_Base.vhd:377
CMX_clock_manager.buf_clk40_m90o
out buf_clk40_m90ostd_logic
Definition: CMX_clock_manager.vhd:35
CMX_top_Base.OCB_A06
in OCB_A06std_logic
Definition: CMX_top_Base.vhd:37
CMX_top_Base.D_CBL_05_B
out D_CBL_05_Bstd_logic
Definition: CMX_top_Base.vhd:611
CMX_top_Base.P1_9
in P1_9std_logic
Definition: CMX_top_Base.vhd:125
glink_interface.ROI_IN
in ROI_INstd_logic_vector (19 downto 0)
Definition: glink_interface.vhd:23
CMX_top_Base.P9_9
in P9_9std_logic
Definition: CMX_top_Base.vhd:325
CMX_top_Base.P15_6
in P15_6std_logic
Definition: CMX_top_Base.vhd:472
CMX_top_Base.P0_16
in P0_16std_logic
Definition: CMX_top_Base.vhd:107
CMX_top_Base.P11_4
in P11_4std_logic
Definition: CMX_top_Base.vhd:370
CMX_top_Base.MP1_F06_QUAD_112_TRN_1_DIR
out MP1_F06_QUAD_112_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:727
CMX_top_Base.P14_3
in P14_3std_logic
Definition: CMX_top_Base.vhd:444
CMX_BASE_VME_BSPT.board_ds
out board_dsstd_logic
Definition: cmx_base_vme_bspt.vhd:31
CMX_top_Base.BF_DOUT_CTP_30
out BF_DOUT_CTP_30std_logic
Definition: CMX_top_Base.vhd:568
CMX_top_Base.P13_13
in P13_13std_logic
Definition: CMX_top_Base.vhd:429
sys_monitor.BF_SYSMON_11_P
in BF_SYSMON_11_PSTD_LOGIC
Definition: sys_monitor.vhd:42
CMX_top_Base.MP2_F05_QUAD_113_TRN_3_DIR
out MP2_F05_QUAD_113_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:739
CMX_top_Base.P4_1
in P4_1std_logic
Definition: CMX_top_Base.vhd:192
sys_monitor.clk
in clkstd_logic
Definition: sys_monitor.vhd:27
CMX_top_Base.P0_5
in P0_5std_logic
Definition: CMX_top_Base.vhd:96
CMX_rate_counter_inhibit.rd_nwr
in rd_nwrstd_logic
Definition: CMX_rate_counter_inhibit.vhd:36
CMX_input_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_input_module.vhd:54
BCID_counter.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: BCID_counter.vhd:37
CMX_top_Base.P6_6
in P6_6std_logic
Definition: CMX_top_Base.vhd:247
CMX_top_Base.P5_15
in P5_15std_logic
Definition: CMX_top_Base.vhd:231
CMX_top_Base.MP1_F09_QUAD_111_TRN_0_CMP
out MP1_F09_QUAD_111_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:718
CMX_top_Base.P5_1
in P5_1std_logic
Definition: CMX_top_Base.vhd:217
CMX_top_Base.MP1_F05_QUAD_110_TRN_3_CMP
out MP1_F05_QUAD_110_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:716
CMX_top_Base.BUF_TTC_L1_ACCEPT
in BUF_TTC_L1_ACCEPTstd_logic
Definition: CMX_top_Base.vhd:698
CMX_top_Base.P6_10
in P6_10std_logic
Definition: CMX_top_Base.vhd:251
CMX_SumET_Topo_Encoder.bcid_in
in bcid_instd_logic_vector (11 downto 0)
Definition: CMX_SumET_Topo_Encoder.vhd:34
vme_inreg_notri.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:31
CMX_top_Base.BF_DEBUG_3
out BF_DEBUG_3std_logic
Definition: CMX_top_Base.vhd:509
Topo_Data_TX.ncs
in ncsstd_logic
Definition: Topo_Data_TX.vhd:52
CMX_top_Base.BF_SYSMON_08_N
in BF_SYSMON_08_NSTD_LOGIC
Definition: CMX_top_Base.vhd:74
CMX_top_Base.P2_4
in P2_4std_logic
Definition: CMX_top_Base.vhd:145
CMX_top_Base.P12_14
in P12_14std_logic
Definition: CMX_top_Base.vhd:405
CMX_top_Base.P8_7
in P8_7std_logic
Definition: CMX_top_Base.vhd:298
CMX_top_Base.BF_SYSMON_10_P
in BF_SYSMON_10_PSTD_LOGIC
Definition: CMX_top_Base.vhd:77
CMX_top_Base.P12_1
in P12_1std_logic
Definition: CMX_top_Base.vhd:392
CMX_top_Base.P7_12
in P7_12std_logic
Definition: CMX_top_Base.vhd:278
SFP_Data_TXRX.RXEQMIX_IN
in RXEQMIX_INstd_logic_vector (2 downto 0)
Definition: SFP_TXRX.vhd:55
CMX_top_Base.P14_11
in P14_11std_logic
Definition: CMX_top_Base.vhd:452
CMX_Sum_Et.MISS_E_THR
in MISS_E_THRarr_ctr_31bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:27
CMX_top_Base.P0_14
in P0_14std_logic
Definition: CMX_top_Base.vhd:105
CMX_top_Base.D_CBL_37_B
out D_CBL_37_Bstd_logic
Definition: CMX_top_Base.vhd:645
CMX_top_Base.P8_10
in P8_10std_logic
Definition: CMX_top_Base.vhd:301
Topo_Data_TX.clk320
in clk320std_logic
Definition: Topo_Data_TX.vhd:39
CMX_top_Base.BF_DAQ_DATA_OUT_DIR
out BF_DAQ_DATA_OUT_DIRstd_logic
Definition: CMX_top_Base.vhd:704
CMX_top_Base.BF_DOUT_CTP_22
out BF_DOUT_CTP_22std_logic
Definition: CMX_top_Base.vhd:560
SFP_Data_TXRX.indata
in indatastd_logic_vector (7 downto 0)
Definition: SFP_TXRX.vhd:50
CMX_top_Base.P5_17
in P5_17std_logic
Definition: CMX_top_Base.vhd:233
CMX_top_Base.BF_DOUT_CTP_08
out BF_DOUT_CTP_08std_logic
Definition: CMX_top_Base.vhd:546
CMX_top_Base.P7_19
in P7_19std_logic
Definition: CMX_top_Base.vhd:285
CMX_top_Base.D_CBL_44_B
out D_CBL_44_Bstd_logic
Definition: CMX_top_Base.vhd:652
vme_inreg.clk
in clkstd_logic
Definition: vme_inreg_rtl.vhd:25
CMX_top_Base.P15_8
in P15_8std_logic
Definition: CMX_top_Base.vhd:474
glink_interface.daq_byte_out
out daq_byte_outstd_logic_vector (1 downto 0)
Definition: glink_interface.vhd:29
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_111_CMP
in CLK_320MHz64_LHC_BF_QUAD_111_CMPstd_logic
Definition: CMX_top_Base.vhd:758
CMX_top_Base.P14_2
in P14_2std_logic
Definition: CMX_top_Base.vhd:443
sys_monitor.ADDR_REG_RO_SYSMON_DATA_BLOCK
ADDR_REG_RO_SYSMON_DATA_BLOCKinteger :=16#1364#
Definition: sys_monitor.vhd:22
CMX_rate_counter_inhibit.counter_reset
out counter_resetstd_logic
Definition: CMX_rate_counter_inhibit.vhd:32
vme_inreg_notri.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri.vhd:37
CMX_top_Base.P8_0
in P8_0std_logic
Definition: CMX_top_Base.vhd:291
CMX_top_Base.BF_TO_FROM_BSPT_4
out BF_TO_FROM_BSPT_4std_logic
Definition: CMX_top_Base.vhd:532
CMX_top_Base.BF_DEBUG_6
out BF_DEBUG_6std_logic
Definition: CMX_top_Base.vhd:512
vme_outreg.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl.vhd:28
CMX_top_Base.P15_22
in P15_22std_logic
Definition: CMX_top_Base.vhd:488
CMX_top_Base.BF_DOUT_CTP_09
out BF_DOUT_CTP_09std_logic
Definition: CMX_top_Base.vhd:547
CMX_top_Base.P8_14
in P8_14std_logic
Definition: CMX_top_Base.vhd:305
SFP_Data_TXRX.odata
out odatastd_logic_vector (7 downto 0)
Definition: SFP_TXRX.vhd:51
vme_outreg_notri_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:23
CMX_top_Base.MP1_F08_QUAD_111_TRN_3_CMP
out MP1_F08_QUAD_111_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:724
vme_outreg_notri.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl_notri.vhd:23
CMX_top_Base.P15_3
in P15_3std_logic
Definition: CMX_top_Base.vhd:469
CMX_top_Base.P11_24
in P11_24std_logic
Definition: CMX_top_Base.vhd:390
CMX_top_Base.P9_15
in P9_15std_logic
Definition: CMX_top_Base.vhd:331
CMX_top_Base.P4_16
in P4_16std_logic
Definition: CMX_top_Base.vhd:207
SFP_Data_TXRX.GTX_TX_READY_OUT
out GTX_TX_READY_OUTstd_logic
Definition: SFP_TXRX.vhd:36
CMX_top_Base.P15_21
in P15_21std_logic
Definition: CMX_top_Base.vhd:487
BCID_counter.bus_drive
out bus_drivestd_logic
Definition: BCID_counter.vhd:40
sys_monitor.BF_SYSMON_15_P
in BF_SYSMON_15_PSTD_LOGIC
Definition: sys_monitor.vhd:50
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_111_DIR
in CLK_320MHz64_LHC_BF_QUAD_111_DIRstd_logic
Definition: CMX_top_Base.vhd:757
CMX_top_Base.P12_21
in P12_21std_logic
Definition: CMX_top_Base.vhd:412
CMX_top_Base.P7_13
in P7_13std_logic
Definition: CMX_top_Base.vhd:279
CMX_top_Base.P13_21
in P13_21std_logic
Definition: CMX_top_Base.vhd:437
CMX_top_Base.P0_12
in P0_12std_logic
Definition: CMX_top_Base.vhd:103
CMX_top_Base.OCB_A13
in OCB_A13std_logic
Definition: CMX_top_Base.vhd:44
vme_inreg_notri_async.ds
in dsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:27
CMX_top_Base.D_CBL_16_B
in D_CBL_16_Bstd_logic
Definition: CMX_top_Base.vhd:622
CMX_top_Base.MP1_F11_QUAD_111_TRN_1_DIR
out MP1_F11_QUAD_111_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:719
CMX_top_Base.P7_4
in P7_4std_logic
Definition: CMX_top_Base.vhd:270
vme_inreg_notri_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:26
CMX_top_Base.MP1_F03_QUAD_110_TRN_1_CMP
out MP1_F03_QUAD_110_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:712
CMX_top_Base.P7_24
in P7_24std_logic
Definition: CMX_top_Base.vhd:290
CMX_top_Base.OCB_A04
in OCB_A04std_logic
Definition: CMX_top_Base.vhd:35
CMX_top_Base.BF_REQ_CABLE_2_INPUT
out BF_REQ_CABLE_2_INPUTstd_logic
Definition: CMX_top_Base.vhd:521
CMX_top_Base.MP2_F03_QUAD_113_TRN_1_CMP
out MP2_F03_QUAD_113_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:736
CMX_Sum_Et.CLK
in CLKstd_logic
Definition: CMX_SumEt.vhd:21
CMX_top_Base.P8_23
in P8_23std_logic
Definition: CMX_top_Base.vhd:314
glink_interface.readout_rst_out
out readout_rst_outstd_logic
Definition: glink_interface.vhd:32
CMX_top_Base.P9_8
in P9_8std_logic
Definition: CMX_top_Base.vhd:324
vme_inreg_notri_async.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:31
CMX_clock_manager.pll_locked_ds2
out pll_locked_ds2std_logic
Definition: CMX_clock_manager.vhd:43
CMX_top_Base.OCB_WRITE_B
in OCB_WRITE_Bstd_logic
Definition: CMX_top_Base.vhd:58
CMX_top_Base.P4_2
in P4_2std_logic
Definition: CMX_top_Base.vhd:193
CMX_top_Base.OCB_GEO_ADRS_0
in OCB_GEO_ADRS_0std_logic
Definition: CMX_top_Base.vhd:30
CMX_top_Base.P13_3
in P13_3std_logic
Definition: CMX_top_Base.vhd:419
CMX_version.rd_nwr
in rd_nwrstd_logic
Definition: CMX_version.vhd:23
CMX_Memory_spy_inhibit.spy_write_inhibit
out spy_write_inhibitstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:39
CMX_top_Base.P5_9
in P5_9std_logic
Definition: CMX_top_Base.vhd:225
CMX_top_Base.P10_4
in P10_4std_logic
Definition: CMX_top_Base.vhd:345
CMX_clock_manager.IB_DS2
in IB_DS2std_logic
Definition: CMX_clock_manager.vhd:41
CMX_top_Base.P2_9
in P2_9std_logic
Definition: CMX_top_Base.vhd:150
glink_interface.CLK_120MHz
in CLK_120MHzstd_logic
Definition: glink_interface.vhd:20
CMX_top_Base.P0_20
in P0_20std_logic
Definition: CMX_top_Base.vhd:111
SFP_Data_TXRX.DFETAP1MONITOR
out DFETAP1MONITORstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:62
CMX_top_Base.MP2_F10_QUAD_114_TRN_2_DIR
out MP2_F10_QUAD_114_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:745
CMX_top_Base.P1_14
in P1_14std_logic
Definition: CMX_top_Base.vhd:130
SFP_Data_TXRX.DFETAP2
in DFETAP2std_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:63
CMX_top_Base.P12_13
in P12_13std_logic
Definition: CMX_top_Base.vhd:404
Topo_Data_TX.indata
in indatastd_logic_vector (TX_indata_length - 1 downto 0)
Definition: Topo_Data_TX.vhd:48
CMX_top_Base.BF_DOUT_CTP_63
out BF_DOUT_CTP_63std_logic
Definition: CMX_top_Base.vhd:603
CMX_top_Base.Behavioral.vme_outreg_notri_async
vme_outreg_notri_async
Definition: CMX_top_Base.vhd:885
CMX_top_Base.D_CBL_75_B
out D_CBL_75_Bstd_logic
Definition: CMX_top_Base.vhd:685
CMX_top_Base.P6_20
in P6_20std_logic
Definition: CMX_top_Base.vhd:261
CMX_top_Base.BF_SYSMON_03_P
in BF_SYSMON_03_PSTD_LOGIC
Definition: CMX_top_Base.vhd:67
vme_outreg_notri.clk
in clkstd_logic
Definition: vme_outreg_rtl_notri.vhd:20
CMX_top_Base.P1_13
in P1_13std_logic
Definition: CMX_top_Base.vhd:129
CMX_clock_manager.rd_nwr
in rd_nwrstd_logic
Definition: CMX_clock_manager.vhd:45
CMX_Sum_Et.XS_B2
in XS_B2arr_ctr_15bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:37
CMX_crate_cable_output_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_crate_cable_output_module.vhd:36
CMX_top_Base.P2_12
in P2_12std_logic
Definition: CMX_top_Base.vhd:153
CMX_top_Base.P5_19
in P5_19std_logic
Definition: CMX_top_Base.vhd:235
CMX_top_Base.P6_23
in P6_23std_logic
Definition: CMX_top_Base.vhd:264
CMX_top_Base.P11_13
in P11_13std_logic
Definition: CMX_top_Base.vhd:379
CMX_SumET_Topo_Encoder.Data_out
out Data_outstd_logic_vector (TX_indata_length - 1 downto 0)
Definition: CMX_SumET_Topo_Encoder.vhd:33
daq_glink
Definition: daq_glink.vhd:21
sys_monitor.BF_SYSMON_04_P
in BF_SYSMON_04_PSTD_LOGIC
Definition: sys_monitor.vhd:32
CMX_top_Base.Behavioral.vme_inreg_async
vme_inreg_async
Definition: CMX_top_Base.vhd:833
Topo_Data_TX.BCID
in BCIDstd_logic_vector (11 downto 0)
Definition: Topo_Data_TX.vhd:42
CMX_top_Base.BF_DOUT_CTP_40
out BF_DOUT_CTP_40std_logic
Definition: CMX_top_Base.vhd:580
CMX_input_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_input_module.vhd:28
daq_collector.datai
in dataiarr_4Xword (max_jems - 1 downto 0)
Definition: daq_collector.vhd:25
SFP_Data_TXRX.PLLLKDET_diag
out PLLLKDET_diagstd_logic
Definition: SFP_TXRX.vhd:38
CMX_top_Base.P5_20
in P5_20std_logic
Definition: CMX_top_Base.vhd:236
CMX_top_Base.P5_22
in P5_22std_logic
Definition: CMX_top_Base.vhd:238
CMX_top_Base.BF_SYSMON_04_P
in BF_SYSMON_04_PSTD_LOGIC
Definition: CMX_top_Base.vhd:69
CMX_top_Base.D_CBL_60_B
out D_CBL_60_Bstd_logic
Definition: CMX_top_Base.vhd:670
CMX_top_Base.BF_ROI_DATA_OUT_CMP
out BF_ROI_DATA_OUT_CMPstd_logic
Definition: CMX_top_Base.vhd:707
CMX_top_Base.BF_DOUT_CTP_15
out BF_DOUT_CTP_15std_logic
Definition: CMX_top_Base.vhd:553
CMX_top_Base.P6_9
in P6_9std_logic
Definition: CMX_top_Base.vhd:250
CMX_top_Base.D_CBL_43_B
in D_CBL_43_Bstd_logic
Definition: CMX_top_Base.vhd:651
CMX_top_Base.P2_5
in P2_5std_logic
Definition: CMX_top_Base.vhd:146
CMX_top_Base.BF_DOUT_CTP_62
out BF_DOUT_CTP_62std_logic
Definition: CMX_top_Base.vhd:602
CMX_top_Base.P10_2
in P10_2std_logic
Definition: CMX_top_Base.vhd:343
daq_glink.dav
out davstd_logic
Definition: daq_glink.vhd:30
glink_interface.byte_pos_out
out byte_pos_outstd_logic_vector (5 downto 0)
Definition: glink_interface.vhd:30
CMX_top_Base.P14_19
in P14_19std_logic
Definition: CMX_top_Base.vhd:460
CMX_BASE_VME_BSPT.brdsel_n
out brdsel_nstd_logic
Definition: cmx_base_vme_bspt.vhd:32
CMX_crate_cable_output_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_crate_cable_output_module.vhd:33
CMX_top_Base.Behavioral.vme_main_hub
vme_main_hub
Definition: CMX_top_Base.vhd:855
SFP_Data_TXRX.clock_source
clock_sourcestd_logic
Definition: SFP_TXRX.vhd:27
CMX_top_Base.BF_DOUT_CTP_33
out BF_DOUT_CTP_33std_logic
Definition: CMX_top_Base.vhd:573
CMX_top_Base.P0_23
in P0_23std_logic
Definition: CMX_top_Base.vhd:114
CMX_top_Base.D_CBL_26_B
out D_CBL_26_Bstd_logic
Definition: CMX_top_Base.vhd:632
vme_inreg_notri.bus_drive
out bus_drivestd_logic
Definition: vme_inreg_rtl_notri.vhd:34
CMX_top_Base.P12_5
in P12_5std_logic
Definition: CMX_top_Base.vhd:396
CMX_top_Base.P8_18
in P8_18std_logic
Definition: CMX_top_Base.vhd:309
CMX_top_Base.P0_24
in P0_24std_logic
Definition: CMX_top_Base.vhd:115
Topo_Data_TX.bus_drive
out bus_drivestd_logic
Definition: Topo_Data_TX.vhd:58
vme_outreg_notri.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri.vhd:26
sys_monitor.BF_SYSMON_15_N
in BF_SYSMON_15_NSTD_LOGIC
Definition: sys_monitor.vhd:51
CMX_top_Base.MP2_F00_QUAD_115_TRN_3_DIR
out MP2_F00_QUAD_115_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:755
CMX_crate_cable_output_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_crate_cable_output_module.vhd:41
Topo_Data_TX.RXN_IN
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:34
BCID_counter
Definition: BCID_counter.vhd:28
CMX_top_Base.D_CBL_47_B
out D_CBL_47_Bstd_logic
Definition: CMX_top_Base.vhd:655
CMX_top_Base.P8_11
in P8_11std_logic
Definition: CMX_top_Base.vhd:302
CMX_input_module.bus_drive
out bus_drivestd_logic
Definition: CMX_input_module.vhd:63
glink_interface.word_sel_out
out word_sel_outstd_logic_vector (1 downto 0)
Definition: glink_interface.vhd:31
CMX_top_Base.D_CBL_68_B
out D_CBL_68_Bstd_logic
Definition: CMX_top_Base.vhd:678
vme_outreg.ncs
in ncsstd_logic
Definition: vme_outreg_rtl.vhd:23
CMX_top_Base.P12_15
in P12_15std_logic
Definition: CMX_top_Base.vhd:406
Topo_Data_TX.RXP_IN
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:35
CMX_Memory_spy_inhibit.ds
in dsstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:44
CMX_top_Base.Behavioral.test_rw_counter
unsigned (15 downto 0) test_rw_counter
Definition: CMX_top_Base.vhd:938
CMX_top_Base.P7_11
in P7_11std_logic
Definition: CMX_top_Base.vhd:277
CMX_top_Base.P8_12
in P8_12std_logic
Definition: CMX_top_Base.vhd:303
CMX_top_Base.D_CBL_55_B
out D_CBL_55_Bstd_logic
Definition: CMX_top_Base.vhd:665
glink_interface.DAQ_IN
in DAQ_INstd_logic_vector (19 downto 0)
Definition: glink_interface.vhd:22
CMX_top_Base.P4_3
in P4_3std_logic
Definition: CMX_top_Base.vhd:194
daq_glink.clk4008
in clk4008std_logic
Definition: daq_glink.vhd:32
CMX_top_Base.P0_9
in P0_9std_logic
Definition: CMX_top_Base.vhd:100
SFP_Data_TXRX.DFESENSCAL
out DFESENSCALstd_logic_vector (2 downto 0)
Definition: SFP_TXRX.vhd:60
CMX_top_Base.P11_9
in P11_9std_logic
Definition: CMX_top_Base.vhd:375
vme_inreg_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_async_rtl.vhd:26
CMX_top_Base.P6_12
in P6_12std_logic
Definition: CMX_top_Base.vhd:253
CMX_top_Base.P13_7
in P13_7std_logic
Definition: CMX_top_Base.vhd:423
CMX_top_Base.D_CBL_36_B
out D_CBL_36_Bstd_logic
Definition: CMX_top_Base.vhd:644
vme_inreg_notri.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl_notri.vhd:28
daq_collector.energy_remote
in energy_remotestd_logic_vector (26 * 4 - 1 downto 0)
Definition: daq_collector.vhd:24
CMX_Sum_Et
Definition: CMX_SumEt.vhd:18
CMX_top_Base.D_CBL_56_B
out D_CBL_56_Bstd_logic
Definition: CMX_top_Base.vhd:666
CMX_top_Base.CLK_40MHz08_DSKW_1_BF_LOGIC_CMP
in CLK_40MHz08_DSKW_1_BF_LOGIC_CMPstd_logic
Definition: CMX_top_Base.vhd:497
CMX_top_Base.P9_24
in P9_24std_logic
Definition: CMX_top_Base.vhd:340
CMX_clock_manager.buf_clk40_90o
out buf_clk40_90ostd_logic
Definition: CMX_clock_manager.vhd:33
CMX_top_Base.BF_DOUT_CTP_48
out BF_DOUT_CTP_48std_logic
Definition: CMX_top_Base.vhd:588
CMX_top_Base.OCB_A02
in OCB_A02std_logic
Definition: CMX_top_Base.vhd:33
SFP_Data_TXRX.MGTREFCLK
in MGTREFCLKstd_logic
Definition: SFP_TXRX.vhd:33
CMX_top_Base.P4_0
in P4_0std_logic
Definition: CMX_top_Base.vhd:191
CMX_top_Base.D_CBL_50_B
out D_CBL_50_Bstd_logic
Definition: CMX_top_Base.vhd:658
CMX_top_Base.D_CBL_40_B
out D_CBL_40_Bstd_logic
Definition: CMX_top_Base.vhd:648
CMX_top_Base.BF_DOUT_CTP_44
out BF_DOUT_CTP_44std_logic
Definition: CMX_top_Base.vhd:584
CMX_top_Base.BF_SYSMON_08_P
in BF_SYSMON_08_PSTD_LOGIC
Definition: CMX_top_Base.vhd:73
CMX_top_Base.P9_23
in P9_23std_logic
Definition: CMX_top_Base.vhd:339
CMX_top_Base.P13_12
in P13_12std_logic
Definition: CMX_top_Base.vhd:428
CMX_top_Base.BF_DOUT_CTP_52
out BF_DOUT_CTP_52std_logic
Definition: CMX_top_Base.vhd:592
CMX_top_Base.P15_9
in P15_9std_logic
Definition: CMX_top_Base.vhd:475
CMX_VME_defs
test registers
Definition: CMX_VME_defs.vhd:13
CMX_clock_manager.I_DS2
in I_DS2std_logic
Definition: CMX_clock_manager.vhd:40
CMX_local_package
Definition: CMX_local_package.vhd:13
CMX_Sum_Et.MISS_E_RES_THR
in MISS_E_RES_THRarr_ctr_31bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:28
CMX_top_Base.D_CBL_12_B
out D_CBL_12_Bstd_logic
Definition: CMX_top_Base.vhd:618
CMX_top_Base.OCB_A20
in OCB_A20std_logic
Definition: CMX_top_Base.vhd:51
CMX_top_Base.P0_4
in P0_4std_logic
Definition: CMX_top_Base.vhd:95
CMX_BASE_VME_BSPT.clk40
in clk40std_logic
Definition: cmx_base_vme_bspt.vhd:26
CMX_top_Base.P6_13
in P6_13std_logic
Definition: CMX_top_Base.vhd:254
CMX_top_Base.Behavioral.bus_drive_from_below_top
std_logic_vector (1762 downto 0) bus_drive_from_below_top
Definition: CMX_top_Base.vhd:864
glink_interface.DAQ_ENCODED_DIAG
out DAQ_ENCODED_DIAGstd_logic_vector (23 downto 0)
Definition: glink_interface.vhd:28
CMX_top_Base.P10_3
in P10_3std_logic
Definition: CMX_top_Base.vhd:344
CMX_top_Base.Behavioral.keep
string keep
Definition: CMX_top_Base.vhd:773
CMX_top_Base.P1_3
in P1_3std_logic
Definition: CMX_top_Base.vhd:119
CMX_top_Base.P0_3
in P0_3std_logic
Definition: CMX_top_Base.vhd:94
CMX_top_Base.BF_REQ_CTP_2_INPUT
out BF_REQ_CTP_2_INPUTstd_logic
Definition: CMX_top_Base.vhd:519
CMX_top_Base.P14_15
in P14_15std_logic
Definition: CMX_top_Base.vhd:456
CMX_top_Base.P9_5
in P9_5std_logic
Definition: CMX_top_Base.vhd:321
CMX_top_Base.Behavioral.vme_inreg_notri
vme_inreg_notri
Definition: CMX_top_Base.vhd:899
SFP_Data_TXRX.clk40_out
out clk40_outstd_logic
Definition: SFP_TXRX.vhd:46
CMX_crate_cable_output_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_crate_cable_output_module.vhd:31
CMX_top_Base.P9_19
in P9_19std_logic
Definition: CMX_top_Base.vhd:335
glink_interface.DAQ_BYTE
out DAQ_BYTEstd_logic_vector (7 downto 0)
Definition: glink_interface.vhd:26
vme_outreg_notri_async.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl_notri_async.vhd:18
CMX_top_Base.D_CBL_46_B
out D_CBL_46_Bstd_logic
Definition: CMX_top_Base.vhd:654
CMX_top_Base.P7_8
in P7_8std_logic
Definition: CMX_top_Base.vhd:274
CMX_top_Base.MP1_F02_QUAD_112_TRN_2_CMP
out MP1_F02_QUAD_112_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:730
CMX_top_Base.P14_0
in P14_0std_logic
Definition: CMX_top_Base.vhd:441
CMX_top_Base.P2_2
in P2_2std_logic
Definition: CMX_top_Base.vhd:143
CMX_top_Base.P10_0
in P10_0std_logic
Definition: CMX_top_Base.vhd:341
sys_monitor.bus_drive
out bus_drivestd_logic
Definition: sys_monitor.vhd:59
CMX_top_Base.MP2_F00_QUAD_115_TRN_3_CMP
out MP2_F00_QUAD_115_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:756
CMX_top_Base.P6_2
in P6_2std_logic
Definition: CMX_top_Base.vhd:243
vme_outreg_notri_async.ds
in dsstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:24
CMX_top_Base.P10_7
in P10_7std_logic
Definition: CMX_top_Base.vhd:348
sys_monitor.BF_SYSMON_12_N
in BF_SYSMON_12_NSTD_LOGIC
Definition: sys_monitor.vhd:45
CMX_top_Base.P10_22
in P10_22std_logic
Definition: CMX_top_Base.vhd:363
CMX_top_Base.P4_5
in P4_5std_logic
Definition: CMX_top_Base.vhd:196
CMX_top_Base.P8_4
in P8_4std_logic
Definition: CMX_top_Base.vhd:295
CMX_top_Base.P7_1
in P7_1std_logic
Definition: CMX_top_Base.vhd:267
Topo_Data_TX.clk40
in clk40std_logic
Definition: Topo_Data_TX.vhd:38
sys_monitor
Definition: sys_monitor.vhd:20
CMX_top_Base.MP2_F05_QUAD_113_TRN_3_CMP
out MP2_F05_QUAD_113_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:740
CMX_Sum_Et.XS_T2_A2
in XS_T2_A2arr_ctr_31bit (num_thresholds - 1 downto 0)
Definition: CMX_SumEt.vhd:31
CMX_top_Base.MP1_F08_QUAD_111_TRN_3_DIR
out MP1_F08_QUAD_111_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:723
CMX_top_Base.Behavioral.write_detect_inreg_test
std_logic write_detect_inreg_test
Definition: CMX_top_Base.vhd:937
CMX_Sum_Et.ov_all_out
out ov_all_outstd_logic_vector (5 downto 0)
Definition: CMX_SumEt.vhd:38
Topo_Data_TX.pll_locked
in pll_lockedstd_logic
Definition: Topo_Data_TX.vhd:40
CMX_top_Base.Behavioral.vme_inreg_notri_async
vme_inreg_notri_async
Definition: CMX_top_Base.vhd:869
CMX_top_Base.P15_1
in P15_1std_logic
Definition: CMX_top_Base.vhd:467
vme_inreg_notri.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:32
CMX_top_Base.OCB_D
inout OCB_Dstd_logic_vector (15 downto 0)
Definition: CMX_top_Base.vhd:62
CMX_top_Base.P13_10
in P13_10std_logic
Definition: CMX_top_Base.vhd:426
CMX_top_Base.D_CBL_35_B
in D_CBL_35_Bstd_logic
Definition: CMX_top_Base.vhd:643
SFP_Data_TXRX.DFETAPOVRD
in DFETAPOVRDstd_logic
Definition: SFP_TXRX.vhd:69
CMX_version.ds
in dsstd_logic
Definition: CMX_version.vhd:24
CMX_top_Base.P0_2
in P0_2std_logic
Definition: CMX_top_Base.vhd:93
CMX_top_Base.P10_20
in P10_20std_logic
Definition: CMX_top_Base.vhd:361
CMX_top_Base.P2_8
in P2_8std_logic
Definition: CMX_top_Base.vhd:149
CMX_top_Base.P5_5
in P5_5std_logic
Definition: CMX_top_Base.vhd:221
vme_inreg_async.ncs
in ncsstd_logic
Definition: vme_inreg_async_rtl.vhd:25
CMX_clock_manager.IB_DS1
in IB_DS1std_logic
Definition: CMX_clock_manager.vhd:31
CMX_top_Base.P15_11
in P15_11std_logic
Definition: CMX_top_Base.vhd:477
CMX_top_Base.BF_DOUT_CTP_02
out BF_DOUT_CTP_02std_logic
Definition: CMX_top_Base.vhd:540
CMX_top_Base.MP1_F01_QUAD_110_TRN_0_CMP
out MP1_F01_QUAD_110_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:710
CMX_top_Base.P3_9
in P3_9std_logic
Definition: CMX_top_Base.vhd:175
CMX_top_Base.D_CBL_31_B
in D_CBL_31_Bstd_logic
Definition: CMX_top_Base.vhd:639
vme_inreg_async.data_vme
inout data_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_async_rtl.vhd:30
CMX_Sum_Et.CTP_CABLE_1
out CTP_CABLE_1std_logic_vector (23 downto 0)
Definition: CMX_SumEt.vhd:25
vme_outreg_notri.read_detect
out read_detectstd_logic
Definition: vme_outreg_rtl_notri.vhd:31
vme_outreg_notri_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:30
CMX_top_Base.D_CBL_13_B
out D_CBL_13_Bstd_logic
Definition: CMX_top_Base.vhd:619
CMX_SumET_Topo_Encoder.clk
in clkstd_logic
Definition: CMX_SumET_Topo_Encoder.vhd:37
CMX_top_Base.CLK_40MHz08_DSKW_1_BF_LOGIC_DIR
in CLK_40MHz08_DSKW_1_BF_LOGIC_DIRstd_logic
Definition: CMX_top_Base.vhd:496
CMX_top_Base.BF_DOUT_CTP_13
out BF_DOUT_CTP_13std_logic
Definition: CMX_top_Base.vhd:551
CMX_top_Base.P13_1
in P13_1std_logic
Definition: CMX_top_Base.vhd:417
CMX_top_Base.Behavioral.CMX_version
CMX_version
Definition: CMX_top_Base.vhd:948
CMX_top_Base.MP2_F02_QUAD_115_TRN_2_CMP
out MP2_F02_QUAD_115_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:754
CMX_top_Base.P15_7
in P15_7std_logic
Definition: CMX_top_Base.vhd:473
CMX_top_Base.MP2_F06_QUAD_115_TRN_1_CMP
out MP2_F06_QUAD_115_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:752
CMX_top_Base.D_CBL_61_B
out D_CBL_61_Bstd_logic
Definition: CMX_top_Base.vhd:671
CMX_version.clk40
in clk40std_logic
Definition: CMX_version.vhd:21
CMX_clock_manager.buf_clk40_ds2
out buf_clk40_ds2std_logic
Definition: CMX_clock_manager.vhd:42
CMX_top_Base.P6_17
in P6_17std_logic
Definition: CMX_top_Base.vhd:258
CMX_top_Base.P5_3
in P5_3std_logic
Definition: CMX_top_Base.vhd:219
CMX_top_Base.BF_DOUT_CTP_59
out BF_DOUT_CTP_59std_logic
Definition: CMX_top_Base.vhd:599
CMX_top_Base.D_CBL_71_B
out D_CBL_71_Bstd_logic
Definition: CMX_top_Base.vhd:681
glink_interface.ROI_DAV
in ROI_DAVstd_logic
Definition: glink_interface.vhd:25
CMX_input_module.buf_clk200
in buf_clk200std_logic
Definition: CMX_input_module.vhd:30
CMX_top_Base.CLK_40MHz08_DSKW_2_BF_LOGIC_DIR
in CLK_40MHz08_DSKW_2_BF_LOGIC_DIRstd_logic
Definition: CMX_top_Base.vhd:499
CMX_top_Base.BF_TO_TP_ROI_SLINK_RETURN_DIR
in BF_TO_TP_ROI_SLINK_RETURN_DIRstd_logic
Definition: CMX_top_Base.vhd:695
CMX_input_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_input_module.vhd:58
CMX_top_Base.BF_DOUT_CTP_56
out BF_DOUT_CTP_56std_logic
Definition: CMX_top_Base.vhd:596
vme_outreg_notri
Definition: vme_outreg_rtl_notri.vhd:14
CMX_top_Base.P15_17
in P15_17std_logic
Definition: CMX_top_Base.vhd:483
Topo_Data_TX.GTXTXRESET_IN
in GTXTXRESET_INstd_logic
Definition: Topo_Data_TX.vhd:29
CMX_top_Base.MP2_F07_QUAD_113_TRN_2_CMP
out MP2_F07_QUAD_113_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:738
CMX_top_Base.P4_7
in P4_7std_logic
Definition: CMX_top_Base.vhd:198
CMX_top_Base.P2_20
in P2_20std_logic
Definition: CMX_top_Base.vhd:161
CMX_top_Base.D_CBL_19_B
out D_CBL_19_Bstd_logic
Definition: CMX_top_Base.vhd:625
CMX_top_Base.P14_23
in P14_23std_logic
Definition: CMX_top_Base.vhd:464
CMX_top_Base.BF_DOUT_CTP_11
out BF_DOUT_CTP_11std_logic
Definition: CMX_top_Base.vhd:549
CMX_top_Base.P3_17
in P3_17std_logic
Definition: CMX_top_Base.vhd:183
vme_inreg
Definition: vme_inreg_rtl.vhd:19
CMX_top_Base.BF_DOUT_CTP_36
out BF_DOUT_CTP_36std_logic
Definition: CMX_top_Base.vhd:576
vme_inreg_notri.ds
in dsstd_logic
Definition: vme_inreg_rtl_notri.vhd:29
CMX_top_Base.MP1_F03_QUAD_110_TRN_1_DIR
out MP1_F03_QUAD_110_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:711
CMX_top_Base.UNISIM
_library_ UNISIMUNISIM
Definition: CMX_top_Base.vhd:12
CMX_top_Base.D_CBL_66_B
out D_CBL_66_Bstd_logic
Definition: CMX_top_Base.vhd:676
daq_glink.data_out
out data_outstd_logic_vector (19 downto 0)
Definition: daq_glink.vhd:29
vme_local_switch.bus_drive_from_below
in bus_drive_from_belowstd_logic_vector
Definition: vme_local_switch.vhd:40
SFP_Data_TXRX.RXP_IN
in RXP_INstd_logic
Definition: SFP_TXRX.vhd:43
CMX_top_Base.P11_15
in P11_15std_logic
Definition: CMX_top_Base.vhd:381
CMX_top_Base.P5_23
in P5_23std_logic
Definition: CMX_top_Base.vhd:239
CMX_top_Base.P13_16
in P13_16std_logic
Definition: CMX_top_Base.vhd:432
CMX_top_Base.P9_0
in P9_0std_logic
Definition: CMX_top_Base.vhd:316
vme_inreg_notri_async
Definition: vme_inreg_rtl_notri_async.vhd:18
CMX_top_Base.P1_12
in P1_12std_logic
Definition: CMX_top_Base.vhd:128
CMX_delay_generator.start_address
start_addressinteger
Definition: CMX_delay_generator.vhd:30
CMX_top_Base.BF_SYSMON_12_N
in BF_SYSMON_12_NSTD_LOGIC
Definition: CMX_top_Base.vhd:82
CMX_top_Base.P8_22
in P8_22std_logic
Definition: CMX_top_Base.vhd:313
CMX_Sum_Et.CTP_CABLE_0
out CTP_CABLE_0std_logic_vector (23 downto 0)
Definition: CMX_SumEt.vhd:24
CMX_top_Base.BF_DEBUG_1
out BF_DEBUG_1std_logic
Definition: CMX_top_Base.vhd:507
CMX_top_Base.D_CBL_02_B
out D_CBL_02_Bstd_logic
Definition: CMX_top_Base.vhd:608
CMX_top_Base.D_CBL_52_B
out D_CBL_52_Bstd_logic
Definition: CMX_top_Base.vhd:660
CMX_top_Base.P11_17
in P11_17std_logic
Definition: CMX_top_Base.vhd:383
CMX_top_Base.D_CBL_18_B
out D_CBL_18_Bstd_logic
Definition: CMX_top_Base.vhd:624
CMX_top_Base.D_CBL_10_B
out D_CBL_10_Bstd_logic
Definition: CMX_top_Base.vhd:616
CMX_top_Base.P10_17
in P10_17std_logic
Definition: CMX_top_Base.vhd:358
CMX_top_Base.MP2_F06_QUAD_115_TRN_1_DIR
out MP2_F06_QUAD_115_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:751
CMX_top_Base.BF_DOUT_CTP_12
out BF_DOUT_CTP_12std_logic
Definition: CMX_top_Base.vhd:550
CMX_crate_cable_output_module.bus_drive
out bus_drivestd_logic
Definition: CMX_crate_cable_output_module.vhd:44
CMX_top_Base.D_CBL_45_B
out D_CBL_45_Bstd_logic
Definition: CMX_top_Base.vhd:653