daq_collector.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.CONV_STD_LOGIC_VECTOR;

LIBRARY work;
use work.CMXpackage.all;
use work.CMX_flavor_package.all;


entity daq_collector is
  port (
    clk         : in  T_SL;
    datai       : in  arr_4Xword(max_jems-1 downto 0);
    din_cbl     : in  T_SLV65;
    din_cbl_ro  : in  T_SL;
    din_lcl     : in  T_SLV60;
    din_lcl_ro  : in  T_SL;
    dout        : in  T_SLV62;
    dout_ro     : in  T_SL;
    data_in_daq : out arr_96(19 downto 0);
    BCID_in     : in std_logic_vector(11 downto 0);
    BCID_delayed : out std_logic_vector(11 downto 0)
    );  
end daq_collector;

architecture Behavioral of daq_collector is

  component parity_gen 
    GENERIC( 
      width : integer := 60
      );
    PORT( 
      din    : IN     std_logic_vector (width-1 downto 0) ;
      parity : OUT    std_logic 
      );
  end component;
  

-- signal declarations

  
  attribute keep : string;  
 

  signal datai_r       :   arr_4Xword(max_jems-1 downto 0);
  signal din_cbl_r     :   T_SLV65;
  signal din_cbl_ro_r  :   T_SL;
  signal din_lcl_r     :   T_SLV60;
  signal din_lcl_ro_r  :   T_SL;
  signal dout_r        :   T_SLV62;
  signal dout_ro_r     :   T_SL;

  signal din_cbl_rr    :   T_SLV65;
  signal din_cbl_ro_rr :   T_SL;
  signal din_lcl_rr    :   T_SLV60;
  signal din_lcl_ro_rr :   T_SL;
  signal dout_rr       :   T_SLV62;
  signal dout_ro_rr    :   T_SL;

  signal jem_occupied_map : std_logic_vector(15 downto 0);
  signal jem_mult         : std_logic_vector(47 downto 0);
  signal datai_corr       : arr_4Xword(max_jems-1 downto 0);

  signal calc_par :  calc_parity_type(max_jems-1 downto 0);
  signal par_err  :  calc_parity_type(max_jems-1 downto 0);

  signal par_err_0 : T_SL;
  signal par_err_1 : T_SL;
  signal par_err_2 : T_SL;
  signal par_err_3 : T_SL;

  signal par_calc_0 : T_SL;
  signal par_calc_1 : T_SL;
  signal par_calc_2 : T_SL;
  signal par_calc_3 : T_SL;

  signal BCID_r : std_logic_vector(11 downto 0);


  attribute keep of datai_r, din_cbl_r, din_cbl_ro_r, din_lcl_r, din_lcl_ro_r, dout_r, dout_ro_r : signal is "TRUE";     


  
begin

  --first register all data locally, and everything except data_i doublr reg
  --data_i_r will have parity error added synchroneously below
  process(clk)
  begin
    if rising_edge(clk) then

      BCID_delayed<=BCID_r;
      BCID_r<=BCID_in;

      datai_r       <= datai;       
      din_cbl_r     <= din_cbl; 
      din_cbl_ro_r  <= din_cbl_ro;
      din_lcl_r     <= din_lcl;     
      din_lcl_ro_r  <= din_lcl_ro; 
      dout_r        <= dout;       
      dout_ro_r     <= dout_ro;
      
      din_cbl_rr    <= din_cbl_r;     
      din_cbl_ro_rr <= din_cbl_ro_r;
      din_lcl_rr    <= din_lcl_r;     
      din_lcl_ro_rr <= din_lcl_ro_r; 
      dout_rr       <= dout_r;       
      dout_ro_rr    <= dout_ro_r;
      
    end if;
  end process;


  par_err_i: for i in 0 to max_jems-1 generate
    par_err_j: for j in 0 to 3 generate
      
      calc_par_i : parity_gen
        generic map (
          width  => 23
          )
        port map (
          din  => datai_r (i)((24*j)+22 downto 24*j),
          parity  => calc_par(i)(j)
          );

      par_err(i)(j) <= calc_par(i)(j) xor datai_r(i)((24*j)+23);   -- parity error 


      process(clk)
      begin
        if rising_edge(clk) then
          datai_corr(i)((24*j)+23 downto 24*j) <=  par_err(i)(j) & datai_r(i)((24*j)+22 downto 24*j);
        end if;
      end process;
      
      
    end generate;
  end generate; 

  calc_par_cbl_0 : parity_gen     -- parity bit calc. (cbl)
    generic map (
      width  => 15
      )
    port map (
      din  => din_cbl_r(14 downto 0),
      parity  => par_calc_0
      );

  --
  -- overflow bit added by Pawel Plucinski 2015-08-21
  -- 
  calc_par_cbl_1 : parity_gen
    generic map (
      width  => 16
      )
    port map (
      din  => din_cbl_ro_r & din_cbl_r   (29 downto 15),
      parity  => par_calc_1
      );

  calc_par_cbl_2 : parity_gen
    generic map (
      width  => 16
      )
    port map (
      din  => din_cbl_r(45 downto 30),
      parity  => par_calc_2
      );

  calc_par_cbl_3 : parity_gen
    generic map (
      width  => 14
      )
    port map (
      din  => din_cbl_r(59 downto 46),
      parity  => par_calc_3
      );


  process(clk)
  begin
    if rising_edge(clk) then
      par_err_0 <= par_calc_0 xor din_cbl_r(60);   -- parity error (cbl)
      par_err_1 <= par_calc_1 xor din_cbl_r(61);
      par_err_2 <= par_calc_2 xor din_cbl_r(62);
      par_err_3 <= par_calc_3 xor din_cbl_r(63);
    end if;
  end process;
  

  
  gen_daq_data: for i_source in 0 to max_jems-1 generate
    data_in_daq(i_source)<=datai_corr(i_source);
  end generate gen_daq_data;
  
--
-- multiplicity remote  
--
  data_in_daq(16)(14 downto 0)  <= din_cbl_rr(14 downto 0);  -- 3 bit multiplicity
  data_in_daq(16)(15)           <= par_err_0;             -- parity error
  data_in_daq(16)(30 downto 16) <= din_cbl_rr(29 downto 15); -- 3 bit multiplicity
  data_in_daq(16)(31)           <= par_err_1;                
  data_in_daq(16)(47 downto 32) <= din_cbl_rr(45 downto 30); -- 2 bit multiplicity
  data_in_daq(16)(48)           <= par_err_2;             
  data_in_daq(16)(62 downto 49) <= din_cbl_rr(59 downto 46); -- 2 bit multiplicity
  data_in_daq(16)(63)           <= par_err_3;             
  data_in_daq(16)(64)           <= din_cbl_ro_rr;            -- remote overflow
  data_in_daq(16)(95 downto 65) <= (others=>'0');         

--
-- multiplicity local  
--

  data_in_daq(17)(14 downto 0)  <= din_lcl_rr(14 downto 0);  -- 3 bit multiplicity
  data_in_daq(17)(15)           <= '0';
  data_in_daq(17)(30 downto 16) <= din_lcl_rr(29 downto 15); -- 3 bit multiplicity
  data_in_daq(17)(31)           <= '0';           
  data_in_daq(17)(47 downto 32) <= din_lcl_rr(45 downto 30); -- 2 bit multiplicity
  data_in_daq(17)(48)           <= '0';           
  data_in_daq(17)(62 downto 49) <= din_lcl_rr(59 downto 46); -- 2 bit multiplicity
  data_in_daq(17)(63)           <= '0';           
  data_in_daq(17)(64)           <= din_lcl_ro_rr;            -- local overflow
  data_in_daq(17)(95 downto 65) <= (others=>'0');              
  
--
-- multiplicity global  
--
  
  data_in_daq(18)(14 downto 0)  <= dout_rr(14 downto 0);  -- 3 bit multiplicity
  data_in_daq(18)(15)           <= '0';
  data_in_daq(18)(30 downto 16) <= dout_rr(29 downto 15); -- 3 bit multiplicity
  data_in_daq(18)(31)           <= '0';           
  data_in_daq(18)(47 downto 32) <= dout_rr(46 downto 31); -- 2 bit multiplicity
  data_in_daq(18)(48)           <= '0';           
  data_in_daq(18)(62 downto 49) <= dout_rr(60 downto 47); -- 2 bit multiplicity
  data_in_daq(18)(63)           <= '0';           
  data_in_daq(18)(64)           <= dout_ro_rr;            -- global overflow
  data_in_daq(18)(95 downto 65) <= (others=>'0');              
  
--
-- Additional data
--
  
  data_in_daq(19)(28 downto 0)  <= (others=>'0'); 
  data_in_daq(19)(44 downto 29) <= jem_occupied_map;    
  data_in_daq(19)(92 downto 45) <= jem_mult;        
  data_in_daq(19)(95 downto 93) <= (others=>'0'); -- zero

  gen_jem_occupied_map: for i_jem in 0 to max_jems-1 generate
    process(clk)
    begin
      if rising_edge(clk) then
        if datai_r(i_jem)(7 downto 0) > 0 then
          jem_occupied_map(i_jem) <= '1';
        else
          jem_occupied_map(i_jem) <= '0';
        end if;
      end if;
    end process;
  end generate;
  

  gen_jem_ntobs: for i_jem in 0 to max_jems-1 generate

    process(clk)
    begin
      if rising_edge(clk) then
        jem_mult((3*i_jem)+2 downto 3*i_jem) <= ofwntobs(conv_integer(datai_r(i_jem)(7 downto 0)))(2 downto 0);
      end if;
    end process;

  end generate;

  
end Behavioral;