1 ----------------------------------------------------------------------------------
7 ----------------------------------------------------------------------------------
9 use IEEE.STD_LOGIC_1164.
ALL;
10 use IEEE.NUMERIC_STD.
ALL;
13 use UNISIM.VComponents.
all;
26 ----------------------------------------------------------------------------
27 -- VME-- backplane (65 signals)
28 ----------------------------------------------------------------------------
29 --GEOADDR0: in std_logic; -- GeoAddr0
31 --VMEADDR: in std_logic_vector(23 downto 1); -- Address bus
55 --VMEDS_L: in std_logic; -- DS strobe VMEDS_L
57 --VMEWR_L: in std_logic; -- VME Write VMEWR_L
59 --VMERST_L: in std_logic; -- System reset VMERST_L
61 --VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA
62 OCB_D: inout (15 downto 0);
63 ----------------------------------------------------------------------------
493 --CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
494 --CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
503 --CLK_320MHz64_LHC_BF_LOGIC_DIR : in std_logic;
504 --CLK_320MHz64_LHC_BF_LOGIC_CMP : in std_logic;
761 --clk40 : in std_logic;
762 RXN_IN : in ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
763 RXP_IN : in ((num_GTX_per_group*num_GTX_groups)-1 downto 0)
773 attribute keep : ;
-- keep signals in synthesis
777 ------------------------------------------------------------------------------
778 -- VME interface component used in BSPT FPGA (Ian's vme_interface)
779 ------------------------------------------------------------------------------
782 clk40 :
IN ;
-- 40MHz Clk
791 -- signals for CMX_BASE_VME_INTERFACE component
792 signal ds: ;
-- board_ds output from VME (Ian model)
793 signal ncs: ;
-- brdsel_n output from VME (Ian model)
947 -- the first variable is
948 -- yet one more register
1005 P :
in mat_var (numactchan
-1 downto 0);
1010 ODATA :
out arr_4Xword (numactchan
-1 downto 0);
1034 --signal PAR_ERROR: std_logic;
1039 signal data_from_vme_REG_RW_QUIET_FORCE : (15 downto 0);
1040 signal data_to_vme_REG_RW_QUIET_FORCE : (15 downto 0);
1042 signal DATA96 : arr_4Xword (numactchan-1 downto 0);
--96 bit data at 40MHz
1043 signal ODATA_first_half : arr_2Xword(numactchan-1 downto 0);
1045 signal P : mat_var (numactchan-1 downto 0);
1047 signal BF_DEBUG : (9 downto 0);
1049 signal counter_enable_inputmod_sig: (numactchan-1 downto 0);
1063 end component CMX_Memory_spy_inhibit;
1065 signal spy_write_inhibit : ;
1086 Tobs_to_TOPO :
out copy_arr_TOB;
-- TOB arrays to load onto
1087 -- encoder; copied x3
1088 overflow :
out (num_copies
-1 downto 0);
1092 --tob rate counter contol
1103 end component decoder;
1106 signal Tobs_to_TOPO : copy_arr_TOB;
1107 signal overflow : (num_copies-1 downto 0);
1108 --signal tot_Et2 : std_logic_vector(et2_width*max_tobs_topo-1 downto 0);
1109 --signal tot_Et1 : std_logic_vector(et1_width*max_tobs_topo-1 downto 0);
1110 --signal tot_pos : std_logic_vector(pos_width*max_tobs_topo-1 downto 0);
1111 --signal overflow : std_logic;
1113 signal data_from_vme_REG_RW_JET_THRESHOLD_BLOCK : arr_16(1599 downto 0);
1114 signal data_to_vme_REG_RW_JET_THRESHOLD_BLOCK : arr_16(1599 downto 0);
1123 clk :
in T_SL;
-- clock
1124 thresholds :
in arr_16(max_jems*
25*
4-1 downto 0);
-- thresholds
1125 datai :
in arr_4Xword(max_jems
-1 downto 0);
-- input data
1126 din_cbl :
in T_SLV65;
-- remote input (multiplicty)
1127 din_cbl_ro :
in T_SL;
-- remote input (overflow)
1128 dout_lcl :
out (
59 downto 0);
-- local multiplicity
1130 dout :
out T_SLV62;
-- global output data (multiplicity), including parity
1131 dout_ro :
out T_SL;
-- global overflow
1132 dout_cbla_mux0 :
out (
33 downto 0);
-- cable output data (multiplicity), including parity
1133 dout_cbla_mux1 :
out (
33 downto 0);
-- cable output data (multiplicity), including parity
1134 dout_cblb_mux0 :
out (
33 downto 0);
-- cable output data (multiplicity), including parity
1135 dout_cblb_mux1 :
out (
33 downto 0);
-- cable output data (multiplicity), including parity
1146 par_err :
in T_SLV2;
-- parity error (input module - 0, RTM - 1)
1147 force :
in T_SL;
-- force
1152 end component adder_top;
1154 signal par_err : T_SLV2;
1156 signal thresholds : arr_16(max_jems*25*4-1 downto 0);
-- thresholds
1158 -- signal p_d : nx121_array(numactchan-1 downto 0); --120 bits + parity -
1159 -- --will be connected to
1160 -- --the decoder output
1161 -- --threshold mask 25
1162 -- --threshold times 4
1163 -- --TOBs + 5 bits position/TOB
1165 signal din_cbl : T_SLV65;
-- remote multiplicity
1166 signal din_cbl_ro : T_SL;
-- remote overflow
1167 signal dout_lcl : T_SLV60;
-- local multiplicity
1168 signal dout_lcl_ro : T_SL;
-- local overflow
1169 signal dout : T_SLV62;
-- data to CTP from adder
1170 signal dout_ro : T_SL;
-- global overflow
1174 datai :
in arr_4Xword(max_jems
-1 downto 0);
1184 end component daq_collector;
1204 signal sdr_data_out_CTP1 : (31 downto 0);
1205 signal sdr_data_out_CTP2 : (31 downto 0);
1206 --signal sdr_data_out : std_logic_vector(31 downto 0);
1209 signal ddr_data_in_RTM1 : (numbits_in_RTM_connector downto 0);
1210 signal ddr_data_in_RTM2 : (numbits_in_RTM_connector downto 0);
1211 signal sig_arr_RTM: arr_RTM(num_RTM_cables-1 downto 0);
1212 signal data_from_RTM : (numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1216 data :
out (numbits_in_RTM_connector*
2*num_RTM_cables
- 1 downto 0);
1218 ddr_data_in :
in arr_RTM(num_RTM_cables
-1 downto 0);
1233 end component CMX_system_cable_input_module;
1250 --signal forwarded_clock_CTP2 : std_logic;
1251 --signal data_CTP2 : std_logic_vector((numbits_in_CTP_connector*2)-1 downto 0);
1252 --signal parity_CTP2 : std_logic;
1253 --signal ddr_data_in_CTP2 : std_logic_vector(numbits_in_CTP_connector downto 0);
1255 --signal forwarded_clock_RTM3 : std_logic;
1256 --signal data_RTM3 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1257 --signal parity_RTM3 : std_logic;
1258 --signal ddr_data_in_RTM3 : std_logic_vector(numbits_in_RTM_connector downto 0);
1266 ncs :
in ;
--ports forwarded to the vme register instances
1274 signal BCID_counter_sig : (11 downto 0);
1275 signal BCID_delayed_decoder : (11 downto 0);
1276 signal BCID_delayed_daq : (11 downto 0);
1279 component PRNG_LFSR_BIG
is
1283 DATA_PRN :
out (
63 downto 0));
1284 end component PRNG_LFSR_BIG;
1285 signal DATA_PRN: arr_64((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1287 --component Topo_Data_TX
1289 -- MGTREFCLK_PAD_N_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1290 -- MGTREFCLK_PAD_P_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1291 -- GTXTXRESET_IN : in std_logic;
1292 -- GTXRXRESET_IN : in std_logic;
1293 -- GTX_TX_READY_OUT : out std_logic;
1294 -- GTX_RX_READY_OUT : out std_logic;
1295 -- RXN_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1296 -- RXP_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1297 -- TXN_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1298 -- TXP_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1299 -- clk40 : in std_logic;
1300 -- clk320 : in std_logic;
1301 -- pll_locked : in std_logic;
1302 -- send_align : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1303 -- BCID : in std_logic_vector(11 downto 0);
1304 -- indata : in std_logic_vector(TX_indata_length-1 downto 0);
1305 -- ext_trigger :in std_logic;
1306 -- ncs : in std_logic;
1307 -- rd_nwr : in std_logic;
1308 -- ds : in std_logic;
1309 -- addr_vme : in std_logic_vector (15 downto 0);
1310 -- data_vme : inout std_logic_vector (15 downto 0)
1324 RXN_IN :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1325 RXP_IN :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1326 TXN_OUT :
out ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1327 TXP_OUT :
out ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1331 send_align :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1332 BCID :
in (
11 downto 0);
1333 indata :
in (TX_indata_length
-1 downto 0);
1342 end component Topo_Data_TX;
1345 component CMX_Jet_Topo_Encoder
is
1347 Tobs_to_TOPO :
in copy_arr_TOB;
1348 overflow :
in (num_copies
-1 downto 0);
1349 send_align_out :
out (num_GTX_groups*num_GTX_per_group
- 1 downto 0);
1350 Data_out :
out (TX_indata_length
- 1 downto 0));
1351 --clk : in std_logic);
1352 end component CMX_Jet_Topo_Encoder;
1354 signal counter_fake_data_Topo_TX : arr_ctr_16bit(num_GTX_groups*num_GTX_per_group-1 downto 0);
1356 signal TXN_OUT : ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1357 signal TXP_OUT : ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1359 signal MGTREFCLK_PAD_N_IN : (num_GTX_groups-1 downto 0);
1360 signal MGTREFCLK_PAD_P_IN : (num_GTX_groups-1 downto 0);
1362 signal GTX_RX_READY_OUT : ;
1363 signal GTX_TX_READY_OUT : ;
1366 signal GTXTXRESET_IN : ;
1367 signal GTXRXRESET_IN : ;
1369 signal send_align : (23 downto 0);
1371 signal indata_Topo_TX : (TX_indata_length-1 downto 0);
1373 signal data_to_vme_REG_RW_TOPOTR_GTX_RESET : (15 downto 0);
1374 signal data_from_vme_REG_RW_TOPOTR_GTX_RESET : (15 downto 0);
1376 signal data_to_vme_REG_RO_TOPOTR_GTX_STATUS : (15 downto 0);
1378 signal data_from_vme_REG_RW_DAQ_ROI_RESET : (15 downto 0);
1379 signal data_to_vme_REG_RW_DAQ_ROI_RESET : (15 downto 0);
1381 signal data_to_vme_REG_RO_DAQ_ROI_STATUS : (15 downto 0);
1383 signal data_from_vme_REG_RW_DAQ_ROI_GTX_RESET: (15 downto 0);
1384 signal data_to_vme_REG_RW_DAQ_ROI_GTX_RESET: (15 downto 0);
1385 signal gtx_reset_SFP_DAQ, gtx_reset_SFP_ROI : ;
1387 signal BUF_TTC_L1_ACCEPT_r: ;
1388 signal l1a_synced: ;
1391 signal bc_reset_synced : ;
1392 signal BUF_TTC_BNCH_CNT_RES_r : ;
1406 end component CMX_rate_counter_inhibit;
1408 signal counter_inhibit : ;
1409 signal counter_reset : ;
1411 --WTF NO CS 20141112 --component chipscope_ila_CMX_top_inputmodclk
1412 --WTF NO CS 20141112 -- port (
1413 --WTF NO CS 20141112 -- CONTROL : inout std_logic_vector(35 downto 0);
1414 --WTF NO CS 20141112 -- CLK : in std_logic;
1415 --WTF NO CS 20141112 -- DATA : in std_logic_vector(2375 downto 0);
1416 --WTF NO CS 20141112 -- TRIG0 : in std_logic_vector(35 downto 0));
1417 --WTF NO CS 20141112 --end component;
1419 --WTF NO CS 20141112 --signal DATA_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(2375 downto 0);
1420 --WTF NO CS 20141112 --signal TRIG0_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(35 downto 0);
1421 --WTF NO CS 20141112 ----signal TRIG_forward_inputmodclk_outputmodclk : std_logic_vector(0 downto 0);
1423 --component chipscope_ila_IDELAY
1425 -- CONTROL : inout std_logic_vector(35 downto 0);
1426 -- CLK : in std_logic;
1427 -- DATA : in std_logic_vector(2000 downto 0);
1428 -- TRIG0 : in std_logic_vector(0 to 0));
1431 --signal DATA_chipscope_ila_IDELAY : std_logic_vector(2000 downto 0);
1434 --component chipscope_ila_CTP2
1436 -- CONTROL : inout std_logic_vector(35 downto 0);
1437 -- CLK : in std_logic;
1438 -- DATA : in std_logic_vector(64 downto 0);
1439 -- TRIG0 : in std_logic_vector(0 to 0));
1442 --component chipscope_ila_RTM
1444 -- CONTROL : inout std_logic_vector(35 downto 0);
1445 -- CLK : in std_logic;
1446 -- DATA : in std_logic_vector(52 downto 0);
1447 -- TRIG0 : in std_logic_vector(0 to 0));
1450 --component chipscope_ila_LVDS_TX_CTP_RTM
1452 -- CONTROL : inout std_logic_vector(35 downto 0);
1453 -- CLK : in std_logic;
1454 -- DATA : in std_logic_vector(117 downto 0);
1455 -- TRIG0 : in std_logic_vector(1 downto 0));
1481 end component CMX_clock_manager;
1484 signal buf_clk40 : ;
1485 signal buf_clk40_m180o : ;
1486 signal buf_clk40_90o : ;
1487 signal buf_clk40_m90o : ;
1489 signal buf_clk320 : ;
1490 signal buf_clk160 : ;
1491 signal buf_clk200 : ;
1492 signal pll_locked : ;
1494 signal buf_clk40_ds2 : ;
1495 signal pll_locked_ds2 : ;
1515 data :
in ((numbits_in_CTP_connector*
2)
-1 downto 0);
1530 end component CMX_CTP_output_module;
1532 signal sdr_data_CTP: arr_CTP;
1534 component CMX_CTP_out_tester
1536 sdr_data_out :
out (
31 downto 0);
1542 addr_vme :
in (
15 downto 0);
1543 data_vme :
inout (
15 downto 0));
1570 indata :
in (
7 downto 0);
1571 odata :
out (
7 downto 0);
1592 signal MGTREFCLK_Q118 : ;
1594 signal GTXTXRESET_IN_TX_SFP_DAQ : ;
1595 signal GTXRXRESET_IN_TX_SFP_DAQ : ;
1596 signal local_pll_lock_out_SFP_DAQ : ;
1597 signal GTX_TX_READY_OUT_TX_SFP_DAQ : ;
1598 signal GTX_RX_READY_OUT_TX_SFP_DAQ : ;
1599 signal PLLLKDET_diag_TX_SFP_DAQ : ;
1600 signal local_gtx_reset_diag_TX_SFP_DAQ : ;
1601 signal local_mmcm_reset_diag_TX_SFP_DAQ : ;
1602 signal GTXTEST_diag_TX_SFP_DAQ : ;
1603 signal RXN_IN_TX_SFP_DAQ : ;
1604 signal RXP_IN_TX_SFP_DAQ : ;
1605 signal TXN_OUT_TX_SFP_DAQ : ;
1606 signal TXP_OUT_TX_SFP_DAQ : ;
1607 signal clk40_out_TX_SFP_DAQ : ;
1608 signal clk120_out_TX_SFP_DAQ : ;
1609 signal clk40_in_TX_SFP_DAQ : ;
1610 signal clk120_in_TX_SFP_DAQ : ;
1611 signal indata_TX_SFP_DAQ : (7 downto 0);
1612 signal odata_TX_SFP_DAQ : (7 downto 0);
1613 signal TXPREEMPHASIS_IN_TX_SFP_DAQ : (3 downto 0);
1614 signal TXPOSTEMPHASIS_IN_TX_SFP_DAQ : (4 downto 0);
1615 signal TXDIFFCTRL_IN_TX_SFP_DAQ : (3 downto 0);
1616 signal RXEQMIX_IN_TX_SFP_DAQ : (2 downto 0);
1617 signal DFECLKDLYADJ_TX_SFP_DAQ : (5 downto 0);
1618 signal DFECLKDLYADJMON_TX_SFP_DAQ : (5 downto 0);
1619 signal DFEDLYOVRD_TX_SFP_DAQ : ;
1620 signal DFEEYEDACMON_TX_SFP_DAQ : (4 downto 0);
1621 signal DFESENSCAL_TX_SFP_DAQ : (2 downto 0);
1622 signal DFETAP1_TX_SFP_DAQ : (4 downto 0);
1623 signal DFETAP1MONITOR_TX_SFP_DAQ : (4 downto 0);
1624 signal DFETAP2_TX_SFP_DAQ : (4 downto 0);
1625 signal DFETAP2MONITOR_TX_SFP_DAQ : (4 downto 0);
1626 signal DFETAP3_TX_SFP_DAQ : (3 downto 0);
1627 signal DFETAP3MONITOR_TX_SFP_DAQ : (3 downto 0);
1628 signal DFETAP4_TX_SFP_DAQ : (3 downto 0);
1629 signal DFETAP4MONITOR_TX_SFP_DAQ : (3 downto 0);
1630 signal DFETAPOVRD_TX_SFP_DAQ : ;
1632 signal GTXTXRESET_IN_TX_SFP_ROI : ;
1633 signal GTXRXRESET_IN_TX_SFP_ROI : ;
1634 signal local_pll_lock_out_SFP_ROI : ;
1635 signal GTX_TX_READY_OUT_TX_SFP_ROI : ;
1636 signal GTX_RX_READY_OUT_TX_SFP_ROI : ;
1637 signal PLLLKDET_diag_TX_SFP_ROI : ;
1638 signal local_gtx_reset_diag_TX_SFP_ROI : ;
1639 signal local_mmcm_reset_diag_TX_SFP_ROI : ;
1640 signal GTXTEST_diag_TX_SFP_ROI : ;
1641 signal RXN_IN_TX_SFP_ROI : ;
1642 signal RXP_IN_TX_SFP_ROI : ;
1643 signal TXN_OUT_TX_SFP_ROI : ;
1644 signal TXP_OUT_TX_SFP_ROI : ;
1645 signal clk40_out_TX_SFP_ROI : ;
1646 signal clk120_out_TX_SFP_ROI : ;
1647 signal clk40_in_TX_SFP_ROI : ;
1648 signal clk120_in_TX_SFP_ROI : ;
1649 signal indata_TX_SFP_ROI : (7 downto 0);
1650 signal odata_TX_SFP_ROI : (7 downto 0);
1651 signal TXPREEMPHASIS_IN_TX_SFP_ROI : (3 downto 0);
1652 signal TXPOSTEMPHASIS_IN_TX_SFP_ROI : (4 downto 0);
1653 signal TXDIFFCTRL_IN_TX_SFP_ROI : (3 downto 0);
1654 signal RXEQMIX_IN_TX_SFP_ROI : (2 downto 0);
1655 signal DFECLKDLYADJ_TX_SFP_ROI : (5 downto 0);
1656 signal DFECLKDLYADJMON_TX_SFP_ROI : (5 downto 0);
1657 signal DFEDLYOVRD_TX_SFP_ROI : ;
1658 signal DFEEYEDACMON_TX_SFP_ROI : (4 downto 0);
1659 signal DFESENSCAL_TX_SFP_ROI : (2 downto 0);
1660 signal DFETAP1_TX_SFP_ROI : (4 downto 0);
1661 signal DFETAP1MONITOR_TX_SFP_ROI : (4 downto 0);
1662 signal DFETAP2_TX_SFP_ROI : (4 downto 0);
1663 signal DFETAP2MONITOR_TX_SFP_ROI : (4 downto 0);
1664 signal DFETAP3_TX_SFP_ROI : (3 downto 0);
1665 signal DFETAP3MONITOR_TX_SFP_ROI : (3 downto 0);
1666 signal DFETAP4_TX_SFP_ROI : (3 downto 0);
1667 signal DFETAP4MONITOR_TX_SFP_ROI : (3 downto 0);
1668 signal DFETAPOVRD_TX_SFP_ROI : ;
1678 DAQ_IN :
in (
19 DOWNTO 0);
1679 ROI_IN :
in (
19 DOWNTO 0);
1692 -- Glink emulator signals
1694 signal daq_in : (19 DOWNTO 0);
1695 signal roi_in : (19 DOWNTO 0);
1698 signal daq_byte : (7 downto 0);
1699 signal roi_byte : (7 downto 0);
1700 signal reset_daq : ;
1701 signal daq_encoded_diag : (23 downto 0);
1702 signal daq_byte_out : (1 downto 0);
1704 signal byte_pos_out : (5 downto 0);
1705 signal word_sel_out : (1 downto 0);
1706 signal readout_rst_out : ;
1708 --component chipscope_icon_u2_c3
1710 -- CONTROL0 : inout std_logic_vector(35 downto 0);
1711 -- CONTROL1 : inout std_logic_vector(35 downto 0);
1712 -- CONTROL2 : inout std_logic_vector(35 downto 0)
1716 --signal CONTROL0 : std_logic_vector(35 downto 0);
1717 --signal CONTROL1 : std_logic_vector(35 downto 0);
1718 --signal CONTROL2 : std_logic_vector(35 downto 0);
1720 --signal data_ila_daq : std_logic_vector (53 downto 0);
1721 --signal trig_ila_daq : std_logic_vector (33 downto 0);
1723 --signal data_ila_encoder : std_logic_vector (20 downto 0);
1724 --signal trig_ila_encoder : std_logic_vector (11 downto 0);
1726 --signal data_ila_gtx_start : std_logic_vector (12 downto 0);
1727 --signal trig_ila_gtx_start : std_logic_vector (2 downto 0);
1730 --signal data_ila_1 : std_logic_vector (16 downto 0);
1732 component glink_chipscope_analyzer
1734 CONTROL:
inout (
35 downto 0);
1736 DATA:
in (
53 downto 0);
1737 TRIG0:
in (
33 downto 0));
1740 component glink_chipscope_analyzer_encoder
1742 CONTROL:
inout (
35 downto 0);
1744 DATA:
in (
20 downto 0);
1745 TRIG0:
in (
11 downto 0));
1748 component glink_chipscope_analyzer_gtx_start
is
1750 CONTROL :
inout (
35 downto 0);
1752 DATA :
in (
10 downto 0);
1753 TRIG0 :
in (
0 to 0));
1754 end component glink_chipscope_analyzer_gtx_start;
1759 data_in :
in arr_96(
19 downto 0);
1770 end component daq_glink;
1772 signal RAM_global_offset : (7 downto 0);
1773 signal RAM_rel_offsets : arr_ctr_8bit(18 downto 0);
1774 signal nslices : (7 downto 0);
1776 signal data_in_daq: arr_96(19 downto 0);
1778 --control of daq delays
1779 signal data_from_vme_REG_RW_DAQ_SLICE: (15 downto 0);
1780 signal data_to_vme_REG_RW_DAQ_SLICE: (15 downto 0);
1781 signal data_from_vme_REG_RW_DAQ_RAM_OFFSET: (15 downto 0);
1782 signal data_to_vme_REG_RW_DAQ_RAM_OFFSET: (15 downto 0);
1784 signal data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1785 signal data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1788 attribute keep of start_playback_r1, BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r, send_align, counter_fake_data_Topo_TX : signal is "TRUE";
1789 attribute IOB of BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r : signal is "FORCE";
1791 --attribute IOB of BF_DOUT_CTP_00 : signal is "TRUE";
1792 --attribute IOB of BF_DOUT_CTP_01 : signal is "TRUE";
1793 --attribute IOB of BF_DOUT_CTP_02 : signal is "TRUE";
1794 --attribute IOB of BF_DOUT_CTP_03 : signal is "TRUE";
1795 --attribute IOB of BF_DOUT_CTP_04 : signal is "TRUE";
1796 --attribute IOB of BF_DOUT_CTP_05 : signal is "TRUE";
1797 --attribute IOB of BF_DOUT_CTP_06 : signal is "TRUE";
1798 --attribute IOB of BF_DOUT_CTP_07 : signal is "TRUE";
1799 --attribute IOB of BF_DOUT_CTP_08 : signal is "TRUE";
1800 --attribute IOB of BF_DOUT_CTP_09 : signal is "TRUE";
1801 --attribute IOB of BF_DOUT_CTP_10 : signal is "TRUE";
1802 --attribute IOB of BF_DOUT_CTP_11 : signal is "TRUE";
1803 --attribute IOB of BF_DOUT_CTP_12 : signal is "TRUE";
1804 --attribute IOB of BF_DOUT_CTP_13 : signal is "TRUE";
1805 --attribute IOB of BF_DOUT_CTP_14 : signal is "TRUE";
1806 --attribute IOB of BF_DOUT_CTP_15 : signal is "TRUE";
1807 --attribute IOB of BF_DOUT_CTP_16 : signal is "TRUE";
1808 --attribute IOB of BF_DOUT_CTP_17 : signal is "TRUE";
1809 --attribute IOB of BF_DOUT_CTP_18 : signal is "TRUE";
1810 --attribute IOB of BF_DOUT_CTP_19 : signal is "TRUE";
1811 --attribute IOB of BF_DOUT_CTP_20 : signal is "TRUE";
1812 --attribute IOB of BF_DOUT_CTP_21 : signal is "TRUE";
1813 --attribute IOB of BF_DOUT_CTP_22 : signal is "TRUE";
1814 --attribute IOB of BF_DOUT_CTP_23 : signal is "TRUE";
1815 --attribute IOB of BF_DOUT_CTP_24 : signal is "TRUE";
1816 --attribute IOB of BF_DOUT_CTP_25 : signal is "TRUE";
1817 --attribute IOB of BF_DOUT_CTP_26 : signal is "TRUE";
1818 --attribute IOB of BF_DOUT_CTP_27 : signal is "TRUE";
1819 --attribute IOB of BF_DOUT_CTP_28 : signal is "TRUE";
1820 --attribute IOB of BF_DOUT_CTP_29 : signal is "TRUE";
1821 --attribute IOB of BF_DOUT_CTP_64 : signal is "TRUE";
1823 --attribute IOB of BF_DOUT_CTP_32 : signal is "TRUE";
1824 --attribute IOB of BF_DOUT_CTP_33 : signal is "TRUE";
1825 --attribute IOB of BF_DOUT_CTP_34 : signal is "TRUE";
1826 --attribute IOB of BF_DOUT_CTP_35 : signal is "TRUE";
1827 --attribute IOB of BF_DOUT_CTP_36 : signal is "TRUE";
1828 --attribute IOB of BF_DOUT_CTP_37 : signal is "TRUE";
1829 --attribute IOB of BF_DOUT_CTP_38 : signal is "TRUE";
1830 --attribute IOB of BF_DOUT_CTP_39 : signal is "TRUE";
1831 --attribute IOB of BF_DOUT_CTP_40 : signal is "TRUE";
1832 --attribute IOB of BF_DOUT_CTP_41 : signal is "TRUE";
1833 --attribute IOB of BF_DOUT_CTP_42 : signal is "TRUE";
1834 --attribute IOB of BF_DOUT_CTP_43 : signal is "TRUE";
1835 --attribute IOB of BF_DOUT_CTP_44 : signal is "TRUE";
1836 --attribute IOB of BF_DOUT_CTP_45 : signal is "TRUE";
1837 --attribute IOB of BF_DOUT_CTP_46 : signal is "TRUE";
1838 --attribute IOB of BF_DOUT_CTP_47 : signal is "TRUE";
1839 --attribute IOB of BF_DOUT_CTP_48 : signal is "TRUE";
1840 --attribute IOB of BF_DOUT_CTP_49 : signal is "TRUE";
1841 --attribute IOB of BF_DOUT_CTP_50 : signal is "TRUE";
1842 --attribute IOB of BF_DOUT_CTP_51 : signal is "TRUE";
1843 --attribute IOB of BF_DOUT_CTP_52 : signal is "TRUE";
1844 --attribute IOB of BF_DOUT_CTP_53 : signal is "TRUE";
1845 --attribute IOB of BF_DOUT_CTP_54 : signal is "TRUE";
1846 --attribute IOB of BF_DOUT_CTP_55 : signal is "TRUE";
1847 --attribute IOB of BF_DOUT_CTP_56 : signal is "TRUE";
1848 --attribute IOB of BF_DOUT_CTP_57 : signal is "TRUE";
1849 --attribute IOB of BF_DOUT_CTP_58 : signal is "TRUE";
1850 --attribute IOB of BF_DOUT_CTP_59 : signal is "TRUE";
1851 --attribute IOB of BF_DOUT_CTP_60 : signal is "TRUE";
1852 --attribute IOB of BF_DOUT_CTP_61 : signal is "TRUE";
1875 --BF_TO_FROM_BSPT_0 <= '0';
1876 --BF_TO_FROM_BSPT_1 <= '0';
1961 --ddr_data_in_CTP2(0) <=BF_DOUT_CTP_32;
1962 --ddr_data_in_CTP2(1) <=BF_DOUT_CTP_33;
1963 --ddr_data_in_CTP2(2) <=BF_DOUT_CTP_34;
1964 --ddr_data_in_CTP2(3) <=BF_DOUT_CTP_35;
1965 --ddr_data_in_CTP2(4) <=BF_DOUT_CTP_36;
1966 --ddr_data_in_CTP2(5) <=BF_DOUT_CTP_37;
1967 --ddr_data_in_CTP2(6) <=BF_DOUT_CTP_38;
1968 --ddr_data_in_CTP2(7) <=BF_DOUT_CTP_39;
1969 --ddr_data_in_CTP2(8) <=BF_DOUT_CTP_40;
1970 --ddr_data_in_CTP2(9) <=BF_DOUT_CTP_41;
1971 --ddr_data_in_CTP2(10) <=BF_DOUT_CTP_42;
1972 --ddr_data_in_CTP2(11) <=BF_DOUT_CTP_43;
1973 --ddr_data_in_CTP2(12) <=BF_DOUT_CTP_44;
1974 --ddr_data_in_CTP2(13) <=BF_DOUT_CTP_45;
1975 --ddr_data_in_CTP2(14) <=BF_DOUT_CTP_46;
1976 --ddr_data_in_CTP2(15) <=BF_DOUT_CTP_47;
1977 --ddr_data_in_CTP2(16) <=BF_DOUT_CTP_48;
1978 --ddr_data_in_CTP2(17) <=BF_DOUT_CTP_49;
1979 --ddr_data_in_CTP2(18) <=BF_DOUT_CTP_50;
1980 --ddr_data_in_CTP2(19) <=BF_DOUT_CTP_51;
1981 --ddr_data_in_CTP2(20) <=BF_DOUT_CTP_52;
1982 --ddr_data_in_CTP2(21) <=BF_DOUT_CTP_53;
1983 --ddr_data_in_CTP2(22) <=BF_DOUT_CTP_54;
1984 --ddr_data_in_CTP2(23) <=BF_DOUT_CTP_55;
1985 --ddr_data_in_CTP2(24) <=BF_DOUT_CTP_56;
1986 --ddr_data_in_CTP2(25) <=BF_DOUT_CTP_57;
1987 --ddr_data_in_CTP2(26) <=BF_DOUT_CTP_58;
1988 --ddr_data_in_CTP2(27) <=BF_DOUT_CTP_59;
1989 --ddr_data_in_CTP2(28) <=BF_DOUT_CTP_60;
1990 --ddr_data_in_CTP2(29) <=BF_DOUT_CTP_61;
1991 --ddr_data_in_CTP2(30) <=BF_DOUT_CTP_62;
1992 --ddr_data_in_CTP2(31) <=BF_DOUT_CTP_65;
1993 --ddr_data_in_CTP2(32) <=BF_DOUT_CTP_63;
2054 sig_arr_RTM(0)<=ddr_data_in_RTM1;
2055 sig_arr_RTM(1)<=ddr_data_in_RTM2;
2057 --D_CBL_81_B <= '0';
2058 --D_CBL_82_B <= '0';
2060 --BF_TO_TP_DAQ_SLINK_RETURN_DIR ;--<= '0';
2061 --BF_TO_TP_DAQ_SLINK_RETURN_CMP ;--<= '0';
2062 --BF_TO_TP_ROI_SLINK_RETURN_DIR ;--<= '0';
2063 --BF_TO_TP_ROI_SLINK_RETURN_CMP ;--<= '0';
2066 --backplane bus assignment
2526 --debug pins bus assignment
2539 ODDR_inst_buf_clk_40 : ODDR
2541 DDR_CLK_EDGE =>
"SAME_EDGE",
-- "OPPOSITE_EDGE" or "SAME_EDGE"
2542 INIT => '0',
-- Initial value for Q port ('1' or '0')
2543 SRTYPE =>
"SYNC") -- Reset Type ("ASYNC" or "SYNC")
2545 Q => BF_DEBUG
(8),
-- 1-bit DDR output
2546 C => buf_clk40,
-- 1-bit clock input
2547 CE => '1',
-- 1-bit clock enable input
2548 D1 => '1',
-- 1-bit data input (positive edge)
2549 D2 => '0',
-- 1-bit data input (negative edge)
2550 R =>
(not pll_locked
),
-- 1-bit reset input
2551 S => '0'
-- 1-bit set input
2554 ODDR_inst_buf_clk_40_ds2 : ODDR
2556 DDR_CLK_EDGE =>
"SAME_EDGE",
-- "OPPOSITE_EDGE" or "SAME_EDGE"
2557 INIT => '0',
-- Initial value for Q port ('1' or '0')
2558 SRTYPE =>
"SYNC") -- Reset Type ("ASYNC" or "SYNC")
2560 Q => BF_DEBUG
(9),
-- 1-bit DDR output
2561 C => buf_clk40_ds2,
-- 1-bit clock input
2562 CE => '1',
-- 1-bit clock enable input
2563 D1 => '1',
-- 1-bit data input (positive edge)
2564 D2 => '0',
-- 1-bit data input (negative edge)
2565 R =>
(not pll_locked_ds2
),
-- 1-bit reset input
2566 S => '0'
-- 1-bit set input
2570 --BF_DEBUG(8) <= buf_clk40;
2571 --BF_DEBUG(9) <= DATA96(5)(0);--start_playback;--BF_TO_TP_DAQ_SLINK_RETURN_DIR;--send_align(0);-- BUF_TTC_BNCH_CNT_RES; --bunch counter reset
2573 BF_DEBUG(7 downto 0)<=(others=>'0');
2599 ------------------------------------------------------------------------------
2600 -- VME interface component used in BSPT FPGA (Ian's vme_interface)
2601 ------------------------------------------------------------------------------
2604 ----------------------------------------------------------------------------
2606 ----------------------------------------------------------------------------
2607 clk40 => buf_clk40 ,
2613 ----------------------------------------------------------------------------
2615 ----------------------------------------------------------------------------
2616 board_ds =>
ds,
-- board_ds output from VME (Ian model)
2617 brdsel_n =>
ncs -- brdsel_n output from VME (Ian model)
2640 clk40 => buf_clk40 ,
2690 if rising_edge(buf_clk40) then
2704 ia_vme => ADDR_REG_RO_test ,
2717 --vme_outreg_test: vme_outreg
2719 -- ia_vme => ADDR_REG_RO_test,
2722 -- clk => buf_clk40,
2723 -- addr_vme => vme_address(16 downto 1),
2725 -- rd_nwr => OCB_WRITE_B,
2727 -- data_to_vme => data_to_vme_test_r,
2728 -- read_detect => read_detect_outreg_test,
2729 -- data_vme => OCB_D);
2734 ia_vme => ADDR_REG_RW_test ,
2750 --vme_inreg_test: vme_inreg
2752 -- ia_vme => ADDR_REG_RW_test,
2755 -- clk => buf_clk40,
2757 -- rd_nwr => OCB_WRITE_B,
2759 -- data_from_vme => data_from_vme_test_rw,
2760 -- data_to_vme => data_to_vme_test_rw,
2761 -- addr_vme => vme_address(16 downto 1),
2762 -- read_detect => read_detect_inreg_test,
2763 -- write_detect => write_detect_inreg_test,
2764 -- data_vme => OCB_D);
2768 -- chipscope_icon_u2_c3_inst: chipscope_icon_u2_c3
2770 -- CONTROL0 => CONTROL0,
2771 -- CONTROL1 => CONTROL1,
2772 -- CONTROL2 => CONTROL2
2774 --WTF NO CS 20141112 --
2775 --WTF NO CS 20141112 -- chipscope_ila_CMX_top_inputmodclk_inst: chipscope_ila_CMX_top_inputmodclk
2776 --WTF NO CS 20141112 -- port map (
2777 --WTF NO CS 20141112 -- CONTROL => CONTROL0,
2778 --WTF NO CS 20141112 -- CLK => buf_clk40,
2779 --WTF NO CS 20141112 -- DATA => DATA_chipscope_ila_CMX_top_inputmodclk,
2780 --WTF NO CS 20141112 -- TRIG0 => TRIG0_chipscope_ila_CMX_top_inputmodclk);
2781 --WTF NO CS 20141112 --
2782 --WTF NO CS 20141112 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2783 --WTF NO CS 20141112 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(33)<=start_playback;
2784 --WTF NO CS 20141112 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(34)<=dout(0);
2785 --WTF NO CS 20141112 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(35)<=data_from_RTM(0);
2786 --WTF NO CS 20141112 --
2787 --WTF NO CS 20141112 --
2788 --WTF NO CS 20141112 -- DATA_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2789 --WTF NO CS 20141112 --
2790 --WTF NO CS 20141112 -- gen_data_chipscope_ila: for ichannel in numactchan-1 downto 0 generate
2791 --WTF NO CS 20141112 --
2792 --WTF NO CS 20141112 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(1+ichannel*2)<=PAR_ERROR(ichannel);
2793 --WTF NO CS 20141112 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(2+ichannel*2)<=counter_enable_inputmod_sig(ichannel);
2794 --WTF NO CS 20141112 --
2795 --WTF NO CS 20141112 -- DATA_chipscope_ila_CMX_top_inputmodclk(1+ichannel*98)<=PAR_ERROR(ichannel);
2796 --WTF NO CS 20141112 -- DATA_chipscope_ila_CMX_top_inputmodclk(2+ichannel*98)<=counter_enable_inputmod_sig(ichannel);
2797 --WTF NO CS 20141112 -- DATA_chipscope_ila_CMX_top_inputmodclk(95+3+ichannel*98 downto 3+ichannel*98)<=DATA96(ichannel);
2798 --WTF NO CS 20141112 --
2799 --WTF NO CS 20141112 -- end generate gen_data_chipscope_ila;
2800 --WTF NO CS 20141112 --
2801 --WTF NO CS 20141112 --
2802 --WTF NO CS 20141112 --
2803 --WTF NO CS 20141112 -- DATA_chipscope_ila_CMX_top_inputmodclk(1630 downto 1569)<=dout;
2804 --WTF NO CS 20141112 -- DATA_chipscope_ila_CMX_top_inputmodclk(1734 downto 1631)<=data_from_RTM;
2805 --WTF NO CS 20141112 -- DATA_chipscope_ila_CMX_top_inputmodclk(1735)<=start_playback;
2806 --WTF NO CS 20141112 -- DATA_chipscope_ila_CMX_top_inputmodclk(2055 downto 1736)<=tot_Et2;
2807 --WTF NO CS 20141112 -- DATA_chipscope_ila_CMX_top_inputmodclk(2375 downto 2056)<=(others=>'0');
2810 --chipscope_ila_IDELAY_1: chipscope_ila_IDELAY
2812 -- CONTROL => CONTROL1,
2813 -- CLK => buf_clk40,
2814 -- DATA => DATA_chipscope_ila_IDELAY,
2815 -- TRIG0(0) => upload_delays);
2817 --gen_chipscpe_data_idelay_ichan: for ichan in numactchan-1 downto 0 generate
2818 -- --no -1 because the clock adds one:
2819 -- gen_chipscpe_data_idelay_ibit: for ibit in numbitsinchan downto 0 generate
2820 -- DATA_chipscope_ila_IDELAY( (ichan*(numbitsinchan+1)+ibit)*5 + 4 downto (ichan*(numbitsinchan+1)+ibit)*5)<=
2821 -- del_register(ichan,ibit);
2822 -- end generate gen_chipscpe_data_idelay_ibit;
2823 --end generate gen_chipscpe_data_idelay_ichan;
2824 --DATA_chipscope_ila_IDELAY(2000)<=upload_delays;
2830 clk40 => buf_clk40 ,
2841 --upload_delays<='0';
2842 --del_register<=(others=>(others=>(others=>'0')));
2846 reset => bc_reset_synced ,
2861 if rising_edge(buf_clk40) then
2876 --ODATA_WORD0 => open,
2897 ia_vme => ADDR_REG_RW_QUIET_FORCE ,
2910 data_to_vme_REG_RW_QUIET_FORCE<=data_from_vme_REG_RW_QUIET_FORCE;
2911 quiet<=data_from_vme_REG_RW_QUIET_FORCE(1);
2912 force<=data_from_vme_REG_RW_QUIET_FORCE(0);
2927 gen_REG_RW_JET_THRESHOLD_BLOCK: for i_thr in 1599 downto 0 generate
2931 ia_vme => ADDR_REG_RW_JET_THRESHOLD_BLOCK+2*i_thr,
2941 data_from_vme => data_from_vme_REG_RW_JET_THRESHOLD_BLOCK
(i_thr
),
2942 data_to_vme => data_to_vme_REG_RW_JET_THRESHOLD_BLOCK
(i_thr
));
2945 --vme_inreg_async_REG_RW_JET_THRESHOLD_BLOCK: vme_inreg_async
2947 -- ia_vme => ADDR_REG_RW_JET_THRESHOLD_BLOCK+2*i_thr,
2951 -- rd_nwr => OCB_WRITE_B,
2953 -- addr_vme => vme_address(16 downto 1),
2954 -- data_vme => OCB_D,
2955 -- data_from_vme => data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr),
2956 -- data_to_vme => data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr));
2957 data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr)<=data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr);
2958 end generate gen_REG_RW_JET_THRESHOLD_BLOCK;
2961 thresholds<=data_from_vme_REG_RW_JET_THRESHOLD_BLOCK;
2983 --tot_Et2 => tot_Et2,
2984 --tot_Et1 => tot_Et1,
2985 --tot_pos => tot_pos,
3007 gen_system => '1'
-- '1' - system, '0' - crate.
3033 reset => counter_reset ,
3034 inhibit => counter_inhibit
3037 din_cbl(14 downto 0)<=data_from_RTM(14 downto 0);
3038 din_cbl(29 downto 15)<=data_from_RTM(40 downto 26);
3039 din_cbl(45 downto 30)<=data_from_RTM(67 downto 52);
3040 din_cbl(59 downto 46)<=data_from_RTM(91 downto 78);
3041 din_cbl(60)<=data_from_RTM(25);
3042 din_cbl(61)<=data_from_RTM(51);
3043 din_cbl(62)<=data_from_RTM(77);
3044 din_cbl(63)<=data_from_RTM(103);
3046 din_cbl_ro <= data_from_RTM(41);
-- overflow
3048 gen_dummy_loc_vme_bus: for i_dummy in 1640 to 1759 generate
3051 end generate gen_dummy_loc_vme_bus;
3076 data => data_from_RTM,
3095 --chipscope_ila_LVDS_TX_CTP_RTM_inst: chipscope_ila_LVDS_TX_CTP_RTM
3097 -- CONTROL => CONTROL1,
3098 -- CLK => buf_clk40,
3099 -- DATA(31 downto 0) => sdr_data_out,
3100 -- DATA(63 downto 32) => (others=>'0'),
3101 -- DATA(115 downto 64) => data_RTM,
3102 -- DATA(116) => '0',
3103 -- DATA(117) => '0',
3136 CMX_Jet_Topo_Encoder_inst: CMX_Jet_Topo_Encoder
3138 Tobs_to_TOPO => Tobs_to_TOPO,
3139 overflow => overflow,
3140 send_align_out => send_align,
3141 Data_out => indata_Topo_TX
);
--,
3142 --clk => buf_clk40);
3162 BCID => BCID_delayed_decoder,
3163 indata => indata_Topo_TX,
3176 -- --for the test make a fake data to send topo
3177 -- gen_indata_counter_fiber: for i_fiber in 0 to 23 generate
3178 -- process(buf_clk40)
3180 -- if rising_edge(buf_clk40) then
3181 -- if counter_fake_data_Topo_TX(i_fiber)(11 downto 0)=to_unsigned(0,12) then
3182 -- send_align(i_fiber)<='1';
3184 -- send_align(i_fiber)<='0';
3186 -- counter_fake_data_Topo_TX(i_fiber)<=counter_fake_data_Topo_TX(i_fiber)+1;
3191 -- PRNG_LFSR_BIG_inst: PRNG_LFSR_BIG
3193 -- clk => buf_clk40,
3194 -- rst => (not pll_locked),
3195 -- DATA_PRN => DATA_PRN(i_fiber) );
3197 -- --counter repeated twice for the msb words
3198 -- gen_data_counter_word: for i_word in 6 to 7 generate
3199 -- indata_Topo_TX(128*(i_fiber)+16*(i_word)+15 downto 128*(i_fiber)+16*(i_word))<=std_logic_vector(counter_fake_data_Topo_TX(i_fiber));
3200 -- end generate gen_data_counter_word;
3202 -- --then the 8 msb of the counter
3203 -- indata_Topo_TX(128*(i_fiber)+95 downto 128*(i_fiber)+88) <= std_logic_vector(counter_fake_data_Topo_TX(i_fiber)(15 downto 8));
3205 -- --then the mgt number
3206 -- indata_Topo_TX(128*(i_fiber)+87 downto 128*(i_fiber)+80) <= std_logic_vector(to_unsigned(i_fiber,8));
3208 -- --then the pseudo random number
3209 -- indata_Topo_TX(128*(i_fiber)+79 downto 128*(i_fiber)+16) <= DATA_PRN(i_fiber);
3212 -- --last 12 bits must be 0, four msb bits of the last word have the counter again
3213 -- indata_Topo_TX(128*(i_fiber)+15 downto 128*(i_fiber)+12) <= std_logic_vector(counter_fake_data_Topo_TX(i_fiber)(15 downto 12));
3214 -- indata_Topo_TX(128*(i_fiber)+11 downto 128*(i_fiber))<=(others=>'0');
3216 -- end generate gen_indata_counter_fiber;
3221 ia_vme => ADDR_REG_RW_TOPOTR_GTX_RESET ,
3232 data_to_vme => data_to_vme_REG_RW_TOPOTR_GTX_RESET
3235 GTXTXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(1);
3236 GTXRXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(0);
3238 data_to_vme_REG_RW_TOPOTR_GTX_RESET<=data_from_vme_REG_RW_TOPOTR_GTX_RESET;
3243 ia_vme => ADDR_REG_RO_TOPOTR_GTX_STATUS ,
3252 data_to_vme => data_to_vme_REG_RO_TOPOTR_GTX_STATUS
);
3254 data_to_vme_REG_RO_TOPOTR_GTX_STATUS(1)<=GTX_TX_READY_OUT;
3255 data_to_vme_REG_RO_TOPOTR_GTX_STATUS(0)<=GTX_RX_READY_OUT;
3257 data_to_vme_REG_RO_TOPOTR_GTX_STATUS(15 downto 2)<=(others=>'0');
3276 RXN_IN => RXN_IN_TX_SFP_DAQ ,
3277 RXP_IN => RXP_IN_TX_SFP_DAQ ,
3278 TXN_OUT => TXN_OUT_TX_SFP_DAQ,
3279 TXP_OUT => TXP_OUT_TX_SFP_DAQ,
3284 indata => indata_TX_SFP_DAQ ,
3285 odata => odata_TX_SFP_DAQ ,
3295 DFETAP1 => DFETAP1_TX_SFP_DAQ,
3297 DFETAP2 => DFETAP2_TX_SFP_DAQ,
3299 DFETAP3 => DFETAP3_TX_SFP_DAQ,
3301 DFETAP4 => DFETAP4_TX_SFP_DAQ,
3320 RXN_IN => RXN_IN_TX_SFP_ROI ,
3321 RXP_IN => RXP_IN_TX_SFP_ROI ,
3322 TXN_OUT => TXN_OUT_TX_SFP_ROI,
3323 TXP_OUT => TXP_OUT_TX_SFP_ROI,
3328 indata => indata_TX_SFP_ROI ,
3329 odata => odata_TX_SFP_ROI ,
3339 DFETAP1 => DFETAP1_TX_SFP_ROI,
3341 DFETAP2 => DFETAP2_TX_SFP_ROI,
3343 DFETAP3 => DFETAP3_TX_SFP_ROI,
3345 DFETAP4 => DFETAP4_TX_SFP_ROI,
3354 CLK_40MHz => clk40_in_TX_SFP_ROI,
-- clk40MHz
3355 CLK_120MHz => clk120_in_TX_SFP_ROI ,
-- clk120MHz
3356 RST => reset_daq ,
--not pll_locked, --reset(0), -- reset
3357 DAQ_IN => daq_in,
-- Input data (DAQ)
3358 ROI_IN => roi_in,
-- Input data (ROI)
3359 DAQ_DAV => daq_dav,
-- Control (DAQ)
3360 ROI_DAV => roi_dav,
-- Control (ROI)
3361 DAQ_BYTE => roi_byte,
-- Output Byte (DAQ)
3362 ROI_BYTE => daq_byte,
-- Output Byte (ROI)
3371 );
-- daq_encoded_DIAG
3373 MGT_118_clk0_ibufds_i : IBUFDS_GTXE1
3376 O => MGTREFCLK_Q118,
3389 clk40_in_TX_SFP_ROI<=clk40_out_TX_SFP_DAQ;
3390 clk120_in_TX_SFP_ROI<=clk120_out_TX_SFP_DAQ;
3392 indata_TX_SFP_DAQ<=daq_byte;
-- from GLINK emulator
3393 indata_TX_SFP_ROI<=roi_byte;
-- from GLINK emulator;
3397 --vio_data_i : diagn_module_vio
3399 -- CONTROL => control1,
3400 -- ASYNC_OUT => reset);
3404 ia_vme => ADDR_REG_RW_DAQ_ROI_RESET ,
3417 reset_daq<=data_from_vme_REG_RW_DAQ_ROI_RESET(0);
3418 data_to_vme_REG_RW_DAQ_ROI_RESET<=data_from_vme_REG_RW_DAQ_ROI_RESET;
3422 ia_vme => ADDR_REG_RW_DAQ_ROI_GTX_RESET ,
3433 data_to_vme => data_to_vme_REG_RW_DAQ_ROI_GTX_RESET
);
3435 gtx_reset_SFP_DAQ<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(0);
3436 gtx_reset_SFP_ROI<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(1);
3437 data_to_vme_REG_RW_DAQ_ROI_GTX_RESET<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET;
3442 ia_vme => ADDR_REG_RO_DAQ_ROI_STATUS ,
3451 data_to_vme => data_to_vme_REG_RO_DAQ_ROI_STATUS
);
3453 data_to_vme_REG_RO_DAQ_ROI_STATUS(0)<=local_pll_lock_out_SFP_DAQ;
3454 data_to_vme_REG_RO_DAQ_ROI_STATUS(1)<=GTX_TX_READY_OUT_TX_SFP_DAQ;
3455 data_to_vme_REG_RO_DAQ_ROI_STATUS(2)<=GTX_RX_READY_OUT_TX_SFP_DAQ;
3456 data_to_vme_REG_RO_DAQ_ROI_STATUS(3)<=PLLLKDET_diag_TX_SFP_DAQ;
3457 data_to_vme_REG_RO_DAQ_ROI_STATUS(4)<=local_pll_lock_out_SFP_ROI;
3458 data_to_vme_REG_RO_DAQ_ROI_STATUS(5)<=GTX_TX_READY_OUT_TX_SFP_ROI;
3459 data_to_vme_REG_RO_DAQ_ROI_STATUS(6)<=GTX_RX_READY_OUT_TX_SFP_ROI;
3460 data_to_vme_REG_RO_DAQ_ROI_STATUS(7)<=PLLLKDET_diag_TX_SFP_ROI;
3461 data_to_vme_REG_RO_DAQ_ROI_STATUS(8)<=readout_rst_out;
3463 data_to_vme_REG_RO_DAQ_ROI_STATUS(15 downto 9) <= (others=>'0');
3466 ---- Chipscope analyzer
3468 --ila_daq_glink : glink_chipscope_analyzer
3470 -- CONTROL => control0,
3471 -- CLK => clk40_in_TX_SFP_ROI,
3472 -- DATA => data_ila_daq,
3473 -- TRIG0 => trig_ila_daq);
3475 --ila_glink_encoder : glink_chipscope_analyzer_encoder
3477 -- CONTROL => control1,
3478 -- CLK => clk120_in_TX_SFP_ROI,
3479 -- DATA => data_ila_encoder,
3480 -- TRIG0 => trig_ila_encoder);
3482 --ila_gtx_start: entity work.glink_chipscope_analyzer_gtx_start
3484 -- CONTROL => CONTROL2,
3485 -- CLK => MGTREFCLK_Q118,
3486 -- DATA => data_ila_gtx_start,
3487 -- TRIG0 => trig_ila_gtx_start);
3489 --data_ila_daq <= daq_in &
3490 -- daq_encoded_diag &
3492 -- local_pll_lock_out_SFP_DAQ &
3493 -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3494 -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3495 -- local_pll_lock_out_SFP_ROI &
3496 -- GTX_TX_READY_OUT_TX_SFP_ROI &
3497 -- GTX_RX_READY_OUT_TX_SFP_ROI &
3503 --trig_ila_daq <= daq_encoded_diag &
3505 -- local_pll_lock_out_SFP_DAQ &
3506 -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3507 -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3508 -- local_pll_lock_out_SFP_ROI &
3509 -- GTX_TX_READY_OUT_TX_SFP_ROI &
3510 -- GTX_RX_READY_OUT_TX_SFP_ROI &
3517 --trig_ila_encoder <= GTX_TX_READY_OUT_TX_SFP_DAQ &
3523 --data_ila_encoder <= byte_pos_out &
3525 -- readout_rst_out &
3526 -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3532 --trig_ila_gtx_start(0)<=pll_locked;
3533 --trig_ila_gtx_start(1)<=gtx_reset_SFP_DAQ;
3534 --trig_ila_gtx_start(2)<=gtx_reset_SFP_ROI;
3538 --data_ila_gtx_start(0)<= pll_locked;
3539 --data_ila_gtx_start(1)<= gtx_reset_SFP_DAQ;
3540 --data_ila_gtx_start(2)<= gtx_reset_SFP_ROI;
3541 --data_ila_gtx_start(3)<= GTX_TX_READY_OUT_TX_SFP_DAQ;
3542 --data_ila_gtx_start(4)<= PLLLKDET_diag_TX_SFP_DAQ;
3543 --data_ila_gtx_start(5)<= local_gtx_reset_diag_TX_SFP_DAQ;
3544 --data_ila_gtx_start(6)<= local_mmcm_reset_diag_TX_SFP_DAQ;
3545 --data_ila_gtx_start(7)<= GTXTEST_diag_TX_SFP_DAQ;
3546 --data_ila_gtx_start(8)<= GTX_TX_READY_OUT_TX_SFP_ROI;
3547 --data_ila_gtx_start(9)<= PLLLKDET_diag_TX_SFP_ROI;
3548 --data_ila_gtx_start(10)<= local_gtx_reset_diag_TX_SFP_ROI;
3549 --data_ila_gtx_start(11)<= local_mmcm_reset_diag_TX_SFP_ROI;
3550 --data_ila_gtx_start(12)<= GTXTEST_diag_TX_SFP_ROI;
3556 if rising_edge(buf_clk40) then
3557 l1a_synced<=BUF_TTC_L1_ACCEPT_r;
3560 bc_reset_synced<=BUF_TTC_BNCH_CNT_RES_r;
3573 clk4000 => clk40_out_TX_SFP_DAQ ,
3575 reset => reset_daq ,
--not pll_locked,
3581 --in this flavor roi and daq have the same behavior
3585 --readout control registers
3588 ia_vme => ADDR_REG_RW_DAQ_SLICE,
3601 nslices(1 downto 0) <= (data_to_vme_REG_RW_DAQ_SLICE(1 downto 0));
3602 nslices(7 downto 2) <= (others=>'0');
3604 data_to_vme_REG_RW_DAQ_SLICE<=data_from_vme_REG_RW_DAQ_SLICE;
3609 ia_vme => ADDR_REG_RW_DAQ_RAM_OFFSET ,
3620 data_to_vme => data_to_vme_REG_RW_DAQ_RAM_OFFSET
);
3622 data_to_vme_REG_RW_DAQ_RAM_OFFSET<=data_from_vme_REG_RW_DAQ_RAM_OFFSET;
3623 RAM_global_offset <= (data_from_vme_REG_RW_DAQ_RAM_OFFSET(7 downto 0));
3626 rel_offset_gen: for i_row in 1 to 19 generate
3629 ia_vme =>
(ADDR_REG_RW_DAQ_RAM_RELATIVE_OFFSET+2*
(i_row-
1)),
3639 data_from_vme => data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET
(i_row-
1),
3640 data_to_vme => data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET
(i_row-
1));
3642 data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)<=data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1);
3643 RAM_rel_offsets(i_row-1)<=(data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)(7 downto 0));
3644 end generate rel_offset_gen;
out BF_DOUT_CTP_41std_logic
in BF_SYSMON_13_NSTD_LOGIC
out TXN_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
in BF_SYSMON_14_PSTD_LOGIC
out BF_DOUT_CTP_01std_logic
out BF_TO_FROM_BSPT_2std_logic
out BF_DAQ_DATA_OUT_CMPstd_logic
in CLK_120MHz000_XTAL_1_BF_TRNCV_DIRstd_logic
in BF_SYSMON_09_PSTD_LOGIC
out data_vme_outstd_logic_vector (15 downto 0)
in BF_TO_TP_ROI_SLINK_RETURN_CMPstd_logic
out BF_TO_FROM_BSPT_3std_logic
out MP1_F11_QUAD_111_TRN_1_CMPstd_logic
out write_detectstd_logic
std_logic read_detect_inreg_test
out BF_LED_REQ_4std_logic
in BF_TO_FROM_BSPT_0std_logic
thresholds_widthinteger :=10
out BF_DOUT_CTP_61std_logic
out data_in_daqarr_96 (19 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out data_vme_outstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_34std_logic
in MGTREFCLK_PAD_N_INstd_logic_vector (num_GTX_groups - 1 downto 0)
out MP1_F04_QUAD_112_TRN_0_DIRstd_logic
inout data_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_32std_logic
in data_inarr_96 (19 downto 0)
out data_vme_outstd_logic_vector (15 downto 0)
out Tobs_to_TOPOcopy_arr_TOB
in datai_first_halfarr_2Xword (max_jems - 1 downto 0)
out MP1_F07_QUAD_110_TRN_2_DIRstd_logic
out data_vmestd_logic_vector (15 downto 0)
out BF_TO_FROM_BSPT_6std_logic
out data_vme_outstd_logic_vector (15 downto 0)
out local_gtx_reset_diagstd_logic
out DFETAP2MONITORstd_logic_vector (4 downto 0)
in counter_inhibitstd_logic
out BF_LED_REQ_1std_logic
out MP2_F01_QUAD_113_TRN_0_CMPstd_logic
in data_vme_instd_logic_vector (15 downto 0)
out BF_DOUT_CTP_21std_logic
out MP1_F10_QUAD_111_TRN_2_DIRstd_logic
std_logic_vector (15 downto 0) data_to_vme_test_rw
out BF_DOUT_CTP_46std_logic
in start_playbackstd_logic
in addr_vmestd_logic_vector (15 downto 0)
in DFETAP4std_logic_vector (3 downto 0)
in BF_SYSMON_03_NSTD_LOGIC
out BF_DOUT_CTP_04std_logic
in BF_SYSMON_10_PSTD_LOGIC
out BF_DOUT_CTP_65std_logic
out BF_DOUT_CTP_55std_logic
in BF_SYSMON_13_NSTD_LOGIC
std_logic_vector (15 downto 0) data_vme_up_top
in BF_SYSMON_13_PSTD_LOGIC
out BF_DOUT_CTP_19std_logic
in BF_SYSMON_12_PSTD_LOGIC
in TXDIFFCTRL_INstd_logic_vector (3 downto 0)
out dout_cbla_mux0std_logic_vector (33 downto 0)
out BF_DOUT_CTP_14std_logic
out BF_DOUT_CTP_47std_logic
out dout_lclstd_logic_vector (59 downto 0)
in BF_SYSMON_01_NSTD_LOGIC
inout data_vmestd_logic_vector (15 downto 0)
the tri-stated port
in BF_SYSMON_10_NSTD_LOGIC
in addr_vmestd_logic_vector (15 downto 0)
out BF_LED_REQ_2std_logic
out dout_cblb_mux0std_logic_vector (33 downto 0)
in BF_TO_TP_DAQ_SLINK_RETURN_DIRstd_logic
in spy_write_inhibitstd_logic
out MP2_F11_QUAD_114_TRN_1_DIRstd_logic
out data_from_vmestd_logic_vector (width - 1 downto 0)
in RAM_rel_offsetsarr_ctr_8bit (18 downto 0)
out BF_LED_REQ_0std_logic
out BF_DOUT_CTP_00std_logic
out BCID_outstd_logic_vector (11 downto 0)
in TXPREEMPHASIS_INstd_logic_vector (3 downto 0)
out data_from_vmestd_logic_vector (width - 1 downto 0)
in CLK_320MHz64_LHC_BF_QUAD_114_DIRstd_logic
in BF_SYSMON_03_PSTD_LOGIC
std_logic_vector (15 downto 0) data_to_vme_outreg_test
out MP2_F07_QUAD_113_TRN_2_DIRstd_logic
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out del_registerdel_register_type
out BF_DOUT_CTP_49std_logic
in BF_SYSMON_09_NSTD_LOGIC
in BF_SYSMON_13_PSTD_LOGIC
out BF_DOUT_CTP_64std_logic
out MP1_F04_QUAD_112_TRN_0_CMPstd_logic
out DFECLKDLYADJMONstd_logic_vector (5 downto 0)
out BCID_delayedstd_logic_vector (11 downto 0)
in BF_SYSMON_15_PSTD_LOGIC
out data_vme_outstd_logic_vector (15 downto 0)
in BF_SYSMON_03_NSTD_LOGIC
out data_from_vmestd_logic_vector (width - 1 downto 0)
out BF_ROI_DATA_OUT_DIRstd_logic
in BF_SYSMON_11_NSTD_LOGIC
in data_vme_from_belowarr_16
--! inputs from local registers and from
out data_from_vmestd_logic_vector (width - 1 downto 0)
out GTXTEST_diagstd_logic
in bus_drive_from_belowstd_logic
--! a request to drive the outside
in addr_vmestd_logic_vector (15 downto 0)
out MP1_F01_QUAD_110_TRN_0_DIRstd_logic
in BF_SYSMON_07_NSTD_LOGIC
out BF_DOUT_CTP_05std_logic
in data_vme_instd_logic_vector (15 downto 0)
out BF_DOUT_CTP_50std_logic
in BCID_instd_logic_vector (11 downto 0)
in BF_SYSMON_14_NSTD_LOGIC
in BF_SYSMON_01_NSTD_LOGIC
out MP2_F04_QUAD_115_TRN_0_CMPstd_logic
out data_vme_outstd_logic_vector (15 downto 0)
out data_vmestd_logic_vector (15 downto 0)
in CLK_40MHz08_DSKW_2_BF_LOGIC_CMPstd_logic
in BF_SYSMON_04_NSTD_LOGIC
in data_vme_instd_logic_vector (15 downto 0)
out buf_clk40_m180ostd_logic
in BF_SYSMON_12_PSTD_LOGIC
out MP2_F04_QUAD_115_TRN_0_DIRstd_logic
in addr_vmestd_logic_vector (15 downto 0)
std_logic_vector (23 downto 1) vme_address
out BF_DOUT_CTP_57std_logic
out BF_DOUT_CTP_42std_logic
in addr_vmestd_logic_vector (15 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
in send_alignstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out BF_DOUT_CTP_51std_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
out BF_DOUT_CTP_54std_logic
out MP1_F02_QUAD_112_TRN_2_DIRstd_logic
in BF_TO_FROM_BSPT_1std_logic
out BF_DOUT_CTP_45std_logic
in BF_SYSMON_07_PSTD_LOGIC
out data_vme_outstd_logic_vector (15 downto 0)
out BCID_delayedstd_logic_vector (11 downto 0)
out write_detectstd_logic
out MP2_F08_QUAD_114_TRN_3_DIRstd_logic
arr_16 (1762 downto 0) data_vme_from_below_top
out BF_DOUT_CTP_60std_logic
std_logic bus_drive_up_top
out data_vme_outstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_07std_logic
out BF_TO_FROM_BSPT_5std_logic
out MP2_F01_QUAD_113_TRN_0_DIRstd_logic
out local_mmcm_reset_diagstd_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
in DFETAP3std_logic_vector (3 downto 0)
out MP1_F07_QUAD_110_TRN_2_CMPstd_logic
in addr_vmestd_logic_vector (15 downto 0)
in BF_SYSMON_09_PSTD_LOGIC
out DFEEYEDACMONstd_logic_vector (4 downto 0)
out BF_DOUT_CTP_17std_logic
in BF_SYSMON_01_PSTD_LOGIC
out BF_DOUT_CTP_31std_logic
out BF_DOUT_CTP_38std_logic
out BF_DOUT_CTP_37std_logic
out MP2_F08_QUAD_114_TRN_3_CMPstd_logic
in addr_vmestd_logic_vector (15 downto 0)
in del_arraycable_del_array_type (numbits_in_cable_connector downto 0)
out BF_DOUT_CTP_29std_logic
thresholds_numinteger :=25
out BF_REQ_CABLE_3_INPUTstd_logic
out BF_DOUT_CTP_35std_logic
in nslicesunsigned (7 downto 0)
out BF_DOUT_CTP_26std_logic
out BF_DOUT_CTP_39std_logic
out GTX_RX_READY_OUTstd_logic
out BF_DOUT_CTP_23std_logic
in DFECLKDLYADJstd_logic_vector (5 downto 0)
out MP2_F09_QUAD_114_TRN_0_DIRstd_logic
out BF_DOUT_CTP_16std_logic
out data_vme_outstd_logic_vector (15 downto 0)
out local_pll_lock_outstd_logic
std_logic_vector (numactchan - 1 downto 0) counter_values
out dout_cbla_mux1std_logic_vector (33 downto 0)
in BF_SYSMON_10_NSTD_LOGIC
out upload_delaysstd_logic
in clk40MHz_m90ostd_logic
out data_vme_going_belowstd_logic_vector (15 downto 0)
in TXPOSTEMPHASIS_INstd_logic_vector (4 downto 0)
in vme_addressstd_logic_vector (23 downto 1)
std_logic start_playback_r1
out data_vme_outstd_logic_vector (15 downto 0)
std_logic_vector (15 downto 0) data_vme_going_below
in data_to_vmestd_logic_vector (width - 1 downto 0)
out MP1_F00_QUAD_112_TRN_3_CMPstd_logic
in buf_clk40_centerstd_logic
out BF_DOUT_CTP_28std_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
in GTXRXRESET_INstd_logic
in MGTREFCLK_PAD_P_INstd_logic_vector (num_GTX_groups - 1 downto 0)
in BF_SYSMON_04_NSTD_LOGIC
in BF_SYSMON_14_PSTD_LOGIC
std_logic_vector (15 downto 0) data_from_vme_test_rw
out data_vme_upstd_logic_vector (15 downto 0)
--! connect this to
in addr_vmestd_logic_vector (15 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_24std_logic
in bc_counterunsigned (11 downto 0)
in BF_TO_TP_DAQ_SLINK_RETURN_CMPstd_logic
out GTX_TX_READY_OUTstd_logic
in BF_SYSMON_09_NSTD_LOGIC
out BF_DOUT_CTP_53std_logic
out MP2_F02_QUAD_115_TRN_2_DIRstd_logic
in datastd_logic_vector ((numbits_in_CTP_connector * 2) - 1 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out BF_REQ_CABLE_1_INPUTstd_logic
std_logic read_detect_outreg_test
del_register_type del_register
in addr_vmestd_logic_vector (15 downto 0)
out MP2_F09_QUAD_114_TRN_0_CMPstd_logic
in data_vme_instd_logic_vector (15 downto 0)
in CLK_120MHz000_XTAL_1_BF_TRNCV_CMPstd_logic
out BF_DOUT_CTP_18std_logic
out BF_DOUT_CTP_06std_logic
out ddr_data_outstd_logic_vector (numbits_in_cable_connector downto 0)
out BF_DOUT_CTP_27std_logic
out BF_DOUT_CTP_43std_logic
out MP2_F03_QUAD_113_TRN_1_DIRstd_logic
out data_vme_outstd_logic_vector (15 downto 0)
in BF_SYSMON_11_NSTD_LOGIC
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
std_logic_vector (15 downto 0) data_to_vme_test_r
out MP2_F11_QUAD_114_TRN_1_CMPstd_logic
in dataiarr_4Xword (max_jems - 1 downto 0)
out DFETAP3MONITORstd_logic_vector (3 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
out TXP_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out MP1_F00_QUAD_112_TRN_3_DIRstd_logic
out MP1_F06_QUAD_112_TRN_1_CMPstd_logic
in BF_SYSMON_11_PSTD_LOGIC
out GTX_RX_READY_OUTstd_logic
in BF_SYSMON_01_PSTD_LOGIC
out BF_DOUT_CTP_58std_logic
out BF_DOUT_CTP_10std_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
in OCB_SYS_RESET_Bstd_logic
numbits_in_cable_connectorinteger
in BCID_instd_logic_vector (11 downto 0)
in DFETAP1std_logic_vector (4 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out bus_drive_upstd_logic
or of all bus drive requests from below
out BF_DOUT_CTP_03std_logic
in BUF_TTC_BNCH_CNT_RESstd_logic
out MP2_F10_QUAD_114_TRN_2_CMPstd_logic
gen_systemstd_logic :='1'
in RAM_global_offsetunsigned (7 downto 0)
out MP1_F10_QUAD_111_TRN_2_CMPstd_logic
in BF_SYSMON_07_PSTD_LOGIC
in data_vme_instd_logic_vector (15 downto 0)
in BF_SYSMON_08_NSTD_LOGIC
out counter_inhibitstd_logic
out MP1_F09_QUAD_111_TRN_0_DIRstd_logic
out BF_REQ_CTP_1_INPUTstd_logic
out BF_LED_REQ_3std_logic
out data_vme_outstd_logic_vector (15 downto 0)
out BF_TO_FROM_BSPT_7std_logic
out BF_DOUT_CTP_25std_logic
in CLK_320MHz64_LHC_BF_QUAD_114_CMPstd_logic
in BF_SYSMON_14_NSTD_LOGIC
in data_vme_instd_logic_vector (15 downto 0)
in BF_SYSMON_07_NSTD_LOGIC
out ROI_BYTEstd_logic_vector (7 downto 0)
in BF_SYSMON_08_PSTD_LOGIC
in upload_delaysstd_logic
out DFETAP4MONITORstd_logic_vector (3 downto 0)
out MP1_F05_QUAD_110_TRN_3_DIRstd_logic
out BF_DOUT_CTP_20std_logic
in BF_SYSMON_15_NSTD_LOGIC
in data_vme_from_belowstd_logic_vector (15 downto 0)
--! input: ORed
out buf_clk40_m90ostd_logic
in ROI_INstd_logic_vector (19 downto 0)
out MP1_F06_QUAD_112_TRN_1_DIRstd_logic
out BF_DOUT_CTP_30std_logic
in BF_SYSMON_11_PSTD_LOGIC
out MP2_F05_QUAD_113_TRN_3_DIRstd_logic
in addr_vmestd_logic_vector (15 downto 0)
out MP1_F09_QUAD_111_TRN_0_CMPstd_logic
out MP1_F05_QUAD_110_TRN_3_CMPstd_logic
in BUF_TTC_L1_ACCEPTstd_logic
in addr_vmestd_logic_vector (15 downto 0)
in BF_SYSMON_08_NSTD_LOGIC
in BF_SYSMON_10_PSTD_LOGIC
in RXEQMIX_INstd_logic_vector (2 downto 0)
out BF_DAQ_DATA_OUT_DIRstd_logic
out BF_DOUT_CTP_22std_logic
in indatastd_logic_vector (7 downto 0)
out BF_DOUT_CTP_08std_logic
out daq_byte_outstd_logic_vector (1 downto 0)
in CLK_320MHz64_LHC_BF_QUAD_111_CMPstd_logic
ADDR_REG_RO_SYSMON_DATA_BLOCKinteger :=16#1364#
out counter_resetstd_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
out BF_TO_FROM_BSPT_4std_logic
out data_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_09std_logic
out odatastd_logic_vector (7 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out MP1_F08_QUAD_111_TRN_3_CMPstd_logic
out GTX_TX_READY_OUTstd_logic
in BF_SYSMON_15_PSTD_LOGIC
in CLK_320MHz64_LHC_BF_QUAD_111_DIRstd_logic
out MP1_F11_QUAD_111_TRN_1_DIRstd_logic
out MP1_F03_QUAD_110_TRN_1_CMPstd_logic
out BF_REQ_CABLE_2_INPUTstd_logic
out MP2_F03_QUAD_113_TRN_1_CMPstd_logic
out readout_rst_outstd_logic
out data_vme_outstd_logic_vector (15 downto 0)
out pll_locked_ds2std_logic
in OCB_GEO_ADRS_0std_logic
out spy_write_inhibitstd_logic
out DFETAP1MONITORstd_logic_vector (4 downto 0)
out MP2_F10_QUAD_114_TRN_2_DIRstd_logic
max_tobs_topointeger :=24
in data_vme_instd_logic_vector (15 downto 0)
in DFETAP2std_logic_vector (4 downto 0)
in indatastd_logic_vector (TX_indata_length - 1 downto 0)
out BF_DOUT_CTP_63std_logic
in BF_SYSMON_03_PSTD_LOGIC
in BF_SYSMON_04_PSTD_LOGIC
in BCIDstd_logic_vector (11 downto 0)
out BF_DOUT_CTP_40std_logic
in dataiarr_4Xword (max_jems - 1 downto 0)
out PLLLKDET_diagstd_logic
in BF_SYSMON_04_PSTD_LOGIC
out BF_ROI_DATA_OUT_CMPstd_logic
out BF_DOUT_CTP_15std_logic
out BF_DOUT_CTP_62std_logic
out byte_pos_outstd_logic_vector (5 downto 0)
out overflowstd_logic_vector (num_copies - 1 downto 0)
out BF_DOUT_CTP_33std_logic
in addr_vmestd_logic_vector (15 downto 0)
in BF_SYSMON_15_NSTD_LOGIC
out MP2_F00_QUAD_115_TRN_3_DIRstd_logic
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out word_sel_outstd_logic_vector (1 downto 0)
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
unsigned (15 downto 0) test_rw_counter
in DAQ_INstd_logic_vector (19 downto 0)
out DFESENSCALstd_logic_vector (2 downto 0)
in CLK_40MHz08_DSKW_1_BF_LOGIC_CMPstd_logic
out buf_clk40_90ostd_logic
out BF_DOUT_CTP_48std_logic
in dataiarr_4Xword (max_jems - 1 downto 0)
out BF_DOUT_CTP_44std_logic
in BF_SYSMON_08_PSTD_LOGIC
in buf_clk40_centerstd_logic
out BF_DOUT_CTP_52std_logic
std_logic_vector (1762 downto 0) bus_drive_from_below_top
out DAQ_ENCODED_DIAGstd_logic_vector (23 downto 0)
out BF_REQ_CTP_2_INPUTstd_logic
out DAQ_BYTEstd_logic_vector (7 downto 0)
out MP1_F02_QUAD_112_TRN_2_CMPstd_logic
in datastd_logic_vector ((numbits_in_cable_connector * 2) - 1 downto 0)
out MP2_F00_QUAD_115_TRN_3_CMPstd_logic
in BF_SYSMON_12_NSTD_LOGIC
in thresholdsarr_16 (max_jems * 25 * 4 - 1 downto 0)
out MP2_F05_QUAD_113_TRN_3_CMPstd_logic
out MP1_F08_QUAD_111_TRN_3_DIRstd_logic
std_logic write_detect_inreg_test
in clk40MHz_m180ostd_logic
in data_vme_instd_logic_vector (15 downto 0)
inout OCB_Dstd_logic_vector (15 downto 0)
out dout_cblb_mux1std_logic_vector (33 downto 0)
out BF_DOUT_CTP_02std_logic
out MP1_F01_QUAD_110_TRN_0_CMPstd_logic
inout data_vmestd_logic_vector (15 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
in data_to_vmestd_logic_vector (width - 1 downto 0)
in CLK_40MHz08_DSKW_1_BF_LOGIC_DIRstd_logic
out BF_DOUT_CTP_13std_logic
out MP2_F02_QUAD_115_TRN_2_CMPstd_logic
out MP2_F06_QUAD_115_TRN_1_CMPstd_logic
out buf_clk40_ds2std_logic
out BF_DOUT_CTP_59std_logic
in CLK_40MHz08_DSKW_2_BF_LOGIC_DIRstd_logic
in BF_TO_TP_ROI_SLINK_RETURN_DIRstd_logic
out BF_DOUT_CTP_56std_logic
in GTXTXRESET_INstd_logic
out MP2_F07_QUAD_113_TRN_2_CMPstd_logic
in addr_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_11std_logic
in counter_resetstd_logic
out BF_DOUT_CTP_36std_logic
out MP1_F03_QUAD_110_TRN_1_DIRstd_logic
out data_outstd_logic_vector (19 downto 0)
in bus_drive_from_belowstd_logic_vector
in BF_SYSMON_12_NSTD_LOGIC
ADDR_REG_RW_PIPELINE_DELAY_LENGTHinteger :=0
out MP2_F06_QUAD_115_TRN_1_DIRstd_logic
out BF_DOUT_CTP_12std_logic