CMX
CMX firmware code in-line documentation
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CMX_top_Base Entity Reference
Inheritance diagram for CMX_top_Base:
CMX_top_Base_tb

Entities

Behavioral  architecture
 

Libraries

IEEE 
UNISIM 
work 

Use Clauses

IEEE.STD_LOGIC_1164.all 
IEEE.NUMERIC_STD.all 
UNISIM.VComponents.all 
work.CMXpackage.all 
work.CMX_VME_defs.all 
work.CMX_local_package.all 
work.CMX_flavor_package.all 

Ports

OCB_GEO_ADRS_0   in std_logic
OCB_A01   in std_logic
OCB_A02   in std_logic
OCB_A03   in std_logic
OCB_A04   in std_logic
OCB_A05   in std_logic
OCB_A06   in std_logic
OCB_A07   in std_logic
OCB_A08   in std_logic
OCB_A09   in std_logic
OCB_A10   in std_logic
OCB_A11   in std_logic
OCB_A12   in std_logic
OCB_A13   in std_logic
OCB_A14   in std_logic
OCB_A15   in std_logic
OCB_A16   in std_logic
OCB_A17   in std_logic
OCB_A18   in std_logic
OCB_A19   in std_logic
OCB_A20   in std_logic
OCB_A21   in std_logic
OCB_A22   in std_logic
OCB_A23   in std_logic
OCB_DS_B   in std_logic
OCB_WRITE_B   in std_logic
OCB_SYS_RESET_B   in std_logic
OCB_D   inout std_logic_vector ( 15 downto 0 )
BF_SYSMON_01_P   in STD_LOGIC
BF_SYSMON_01_N   in STD_LOGIC
BF_SYSMON_03_P   in STD_LOGIC
BF_SYSMON_03_N   in STD_LOGIC
BF_SYSMON_04_P   in STD_LOGIC
BF_SYSMON_04_N   in STD_LOGIC
BF_SYSMON_07_P   in STD_LOGIC
BF_SYSMON_07_N   in STD_LOGIC
BF_SYSMON_08_P   in STD_LOGIC
BF_SYSMON_08_N   in STD_LOGIC
BF_SYSMON_09_P   in STD_LOGIC
BF_SYSMON_09_N   in STD_LOGIC
BF_SYSMON_10_P   in STD_LOGIC
BF_SYSMON_10_N   in STD_LOGIC
BF_SYSMON_11_P   in STD_LOGIC
BF_SYSMON_11_N   in STD_LOGIC
BF_SYSMON_12_P   in STD_LOGIC
BF_SYSMON_12_N   in STD_LOGIC
BF_SYSMON_13_P   in STD_LOGIC
BF_SYSMON_13_N   in STD_LOGIC
BF_SYSMON_14_P   in STD_LOGIC
BF_SYSMON_14_N   in STD_LOGIC
BF_SYSMON_15_P   in STD_LOGIC
BF_SYSMON_15_N   in STD_LOGIC
P0_0   in std_logic
P0_1   in std_logic
P0_2   in std_logic
P0_3   in std_logic
P0_4   in std_logic
P0_5   in std_logic
P0_6   in std_logic
P0_7   in std_logic
P0_8   in std_logic
P0_9   in std_logic
P0_10   in std_logic
P0_11   in std_logic
P0_12   in std_logic
P0_13   in std_logic
P0_14   in std_logic
P0_15   in std_logic
P0_16   in std_logic
P0_17   in std_logic
P0_18   in std_logic
P0_19   in std_logic
P0_20   in std_logic
P0_21   in std_logic
P0_22   in std_logic
P0_23   in std_logic
P0_24   in std_logic
P1_0   in std_logic
P1_1   in std_logic
P1_2   in std_logic
P1_3   in std_logic
P1_4   in std_logic
P1_5   in std_logic
P1_6   in std_logic
P1_7   in std_logic
P1_8   in std_logic
P1_9   in std_logic
P1_10   in std_logic
P1_11   in std_logic
P1_12   in std_logic
P1_13   in std_logic
P1_14   in std_logic
P1_15   in std_logic
P1_16   in std_logic
P1_17   in std_logic
P1_18   in std_logic
P1_19   in std_logic
P1_20   in std_logic
P1_21   in std_logic
P1_22   in std_logic
P1_23   in std_logic
P1_24   in std_logic
P2_0   in std_logic
P2_1   in std_logic
P2_2   in std_logic
P2_3   in std_logic
P2_4   in std_logic
P2_5   in std_logic
P2_6   in std_logic
P2_7   in std_logic
P2_8   in std_logic
P2_9   in std_logic
P2_10   in std_logic
P2_11   in std_logic
P2_12   in std_logic
P2_13   in std_logic
P2_14   in std_logic
P2_15   in std_logic
P2_16   in std_logic
P2_17   in std_logic
P2_18   in std_logic
P2_19   in std_logic
P2_20   in std_logic
P2_21   in std_logic
P2_22   in std_logic
P2_23   in std_logic
P2_24   in std_logic
P3_0   in std_logic
P3_1   in std_logic
P3_2   in std_logic
P3_3   in std_logic
P3_4   in std_logic
P3_5   in std_logic
P3_6   in std_logic
P3_7   in std_logic
P3_8   in std_logic
P3_9   in std_logic
P3_10   in std_logic
P3_11   in std_logic
P3_12   in std_logic
P3_13   in std_logic
P3_14   in std_logic
P3_15   in std_logic
P3_16   in std_logic
P3_17   in std_logic
P3_18   in std_logic
P3_19   in std_logic
P3_20   in std_logic
P3_21   in std_logic
P3_22   in std_logic
P3_23   in std_logic
P3_24   in std_logic
P4_0   in std_logic
P4_1   in std_logic
P4_2   in std_logic
P4_3   in std_logic
P4_4   in std_logic
P4_5   in std_logic
P4_6   in std_logic
P4_7   in std_logic
P4_8   in std_logic
P4_9   in std_logic
P4_10   in std_logic
P4_11   in std_logic
P4_12   in std_logic
P4_13   in std_logic
P4_14   in std_logic
P4_15   in std_logic
P4_16   in std_logic
P4_17   in std_logic
P4_18   in std_logic
P4_19   in std_logic
P4_20   in std_logic
P4_21   in std_logic
P4_22   in std_logic
P4_23   in std_logic
P4_24   in std_logic
P5_0   in std_logic
P5_1   in std_logic
P5_2   in std_logic
P5_3   in std_logic
P5_4   in std_logic
P5_5   in std_logic
P5_6   in std_logic
P5_7   in std_logic
P5_8   in std_logic
P5_9   in std_logic
P5_10   in std_logic
P5_11   in std_logic
P5_12   in std_logic
P5_13   in std_logic
P5_14   in std_logic
P5_15   in std_logic
P5_16   in std_logic
P5_17   in std_logic
P5_18   in std_logic
P5_19   in std_logic
P5_20   in std_logic
P5_21   in std_logic
P5_22   in std_logic
P5_23   in std_logic
P5_24   in std_logic
P6_0   in std_logic
P6_1   in std_logic
P6_2   in std_logic
P6_3   in std_logic
P6_4   in std_logic
P6_5   in std_logic
P6_6   in std_logic
P6_7   in std_logic
P6_8   in std_logic
P6_9   in std_logic
P6_10   in std_logic
P6_11   in std_logic
P6_12   in std_logic
P6_13   in std_logic
P6_14   in std_logic
P6_15   in std_logic
P6_16   in std_logic
P6_17   in std_logic
P6_18   in std_logic
P6_19   in std_logic
P6_20   in std_logic
P6_21   in std_logic
P6_22   in std_logic
P6_23   in std_logic
P6_24   in std_logic
P7_0   in std_logic
P7_1   in std_logic
P7_2   in std_logic
P7_3   in std_logic
P7_4   in std_logic
P7_5   in std_logic
P7_6   in std_logic
P7_7   in std_logic
P7_8   in std_logic
P7_9   in std_logic
P7_10   in std_logic
P7_11   in std_logic
P7_12   in std_logic
P7_13   in std_logic
P7_14   in std_logic
P7_15   in std_logic
P7_16   in std_logic
P7_17   in std_logic
P7_18   in std_logic
P7_19   in std_logic
P7_20   in std_logic
P7_21   in std_logic
P7_22   in std_logic
P7_23   in std_logic
P7_24   in std_logic
P8_0   in std_logic
P8_1   in std_logic
P8_2   in std_logic
P8_3   in std_logic
P8_4   in std_logic
P8_5   in std_logic
P8_6   in std_logic
P8_7   in std_logic
P8_8   in std_logic
P8_9   in std_logic
P8_10   in std_logic
P8_11   in std_logic
P8_12   in std_logic
P8_13   in std_logic
P8_14   in std_logic
P8_15   in std_logic
P8_16   in std_logic
P8_17   in std_logic
P8_18   in std_logic
P8_19   in std_logic
P8_20   in std_logic
P8_21   in std_logic
P8_22   in std_logic
P8_23   in std_logic
P8_24   in std_logic
P9_0   in std_logic
P9_1   in std_logic
P9_2   in std_logic
P9_3   in std_logic
P9_4   in std_logic
P9_5   in std_logic
P9_6   in std_logic
P9_7   in std_logic
P9_8   in std_logic
P9_9   in std_logic
P9_10   in std_logic
P9_11   in std_logic
P9_12   in std_logic
P9_13   in std_logic
P9_14   in std_logic
P9_15   in std_logic
P9_16   in std_logic
P9_17   in std_logic
P9_18   in std_logic
P9_19   in std_logic
P9_20   in std_logic
P9_21   in std_logic
P9_22   in std_logic
P9_23   in std_logic
P9_24   in std_logic
P10_0   in std_logic
P10_1   in std_logic
P10_2   in std_logic
P10_3   in std_logic
P10_4   in std_logic
P10_5   in std_logic
P10_6   in std_logic
P10_7   in std_logic
P10_8   in std_logic
P10_9   in std_logic
P10_10   in std_logic
P10_11   in std_logic
P10_12   in std_logic
P10_13   in std_logic
P10_14   in std_logic
P10_15   in std_logic
P10_16   in std_logic
P10_17   in std_logic
P10_18   in std_logic
P10_19   in std_logic
P10_20   in std_logic
P10_21   in std_logic
P10_22   in std_logic
P10_23   in std_logic
P10_24   in std_logic
P11_0   in std_logic
P11_1   in std_logic
P11_2   in std_logic
P11_3   in std_logic
P11_4   in std_logic
P11_5   in std_logic
P11_6   in std_logic
P11_7   in std_logic
P11_8   in std_logic
P11_9   in std_logic
P11_10   in std_logic
P11_11   in std_logic
P11_12   in std_logic
P11_13   in std_logic
P11_14   in std_logic
P11_15   in std_logic
P11_16   in std_logic
P11_17   in std_logic
P11_18   in std_logic
P11_19   in std_logic
P11_20   in std_logic
P11_21   in std_logic
P11_22   in std_logic
P11_23   in std_logic
P11_24   in std_logic
P12_0   in std_logic
P12_1   in std_logic
P12_2   in std_logic
P12_3   in std_logic
P12_4   in std_logic
P12_5   in std_logic
P12_6   in std_logic
P12_7   in std_logic
P12_8   in std_logic
P12_9   in std_logic
P12_10   in std_logic
P12_11   in std_logic
P12_12   in std_logic
P12_13   in std_logic
P12_14   in std_logic
P12_15   in std_logic
P12_16   in std_logic
P12_17   in std_logic
P12_18   in std_logic
P12_19   in std_logic
P12_20   in std_logic
P12_21   in std_logic
P12_22   in std_logic
P12_23   in std_logic
P12_24   in std_logic
P13_0   in std_logic
P13_1   in std_logic
P13_2   in std_logic
P13_3   in std_logic
P13_4   in std_logic
P13_5   in std_logic
P13_6   in std_logic
P13_7   in std_logic
P13_8   in std_logic
P13_9   in std_logic
P13_10   in std_logic
P13_11   in std_logic
P13_12   in std_logic
P13_13   in std_logic
P13_14   in std_logic
P13_15   in std_logic
P13_16   in std_logic
P13_17   in std_logic
P13_18   in std_logic
P13_19   in std_logic
P13_20   in std_logic
P13_21   in std_logic
P13_22   in std_logic
P13_23   in std_logic
P13_24   in std_logic
P14_0   in std_logic
P14_1   in std_logic
P14_2   in std_logic
P14_3   in std_logic
P14_4   in std_logic
P14_5   in std_logic
P14_6   in std_logic
P14_7   in std_logic
P14_8   in std_logic
P14_9   in std_logic
P14_10   in std_logic
P14_11   in std_logic
P14_12   in std_logic
P14_13   in std_logic
P14_14   in std_logic
P14_15   in std_logic
P14_16   in std_logic
P14_17   in std_logic
P14_18   in std_logic
P14_19   in std_logic
P14_20   in std_logic
P14_21   in std_logic
P14_22   in std_logic
P14_23   in std_logic
P14_24   in std_logic
P15_0   in std_logic
P15_1   in std_logic
P15_2   in std_logic
P15_3   in std_logic
P15_4   in std_logic
P15_5   in std_logic
P15_6   in std_logic
P15_7   in std_logic
P15_8   in std_logic
P15_9   in std_logic
P15_10   in std_logic
P15_11   in std_logic
P15_12   in std_logic
P15_13   in std_logic
P15_14   in std_logic
P15_15   in std_logic
P15_16   in std_logic
P15_17   in std_logic
P15_18   in std_logic
P15_19   in std_logic
P15_20   in std_logic
P15_21   in std_logic
P15_22   in std_logic
P15_23   in std_logic
P15_24   in std_logic
CLK_40MHz08_DSKW_1_BF_LOGIC_DIR   in std_logic
CLK_40MHz08_DSKW_1_BF_LOGIC_CMP   in std_logic
CLK_40MHz08_DSKW_2_BF_LOGIC_DIR   in std_logic
CLK_40MHz08_DSKW_2_BF_LOGIC_CMP   in std_logic
BF_DEBUG_0   out std_logic
BF_DEBUG_1   out std_logic
BF_DEBUG_2   out std_logic
BF_DEBUG_3   out std_logic
BF_DEBUG_4   out std_logic
BF_DEBUG_5   out std_logic
BF_DEBUG_6   out std_logic
BF_DEBUG_7   out std_logic
BF_DEBUG_8   out std_logic
BF_DEBUG_9   out std_logic
BF_REQ_CTP_1_INPUT   out std_logic
BF_REQ_CTP_2_INPUT   out std_logic
BF_REQ_CABLE_1_INPUT   out std_logic
BF_REQ_CABLE_2_INPUT   out std_logic
BF_REQ_CABLE_3_INPUT   out std_logic
BF_LED_REQ_0   out std_logic
BF_LED_REQ_1   out std_logic
BF_LED_REQ_2   out std_logic
BF_LED_REQ_3   out std_logic
BF_LED_REQ_4   out std_logic
BF_TO_FROM_BSPT_0   in std_logic
BF_TO_FROM_BSPT_1   in std_logic
BF_TO_FROM_BSPT_2   out std_logic
BF_TO_FROM_BSPT_3   out std_logic
BF_TO_FROM_BSPT_4   out std_logic
BF_TO_FROM_BSPT_5   out std_logic
BF_TO_FROM_BSPT_6   out std_logic
BF_TO_FROM_BSPT_7   out std_logic
BF_DOUT_CTP_00   out std_logic
BF_DOUT_CTP_01   out std_logic
BF_DOUT_CTP_02   out std_logic
BF_DOUT_CTP_03   out std_logic
BF_DOUT_CTP_04   out std_logic
BF_DOUT_CTP_05   out std_logic
BF_DOUT_CTP_06   out std_logic
BF_DOUT_CTP_07   out std_logic
BF_DOUT_CTP_08   out std_logic
BF_DOUT_CTP_09   out std_logic
BF_DOUT_CTP_10   out std_logic
BF_DOUT_CTP_11   out std_logic
BF_DOUT_CTP_12   out std_logic
BF_DOUT_CTP_13   out std_logic
BF_DOUT_CTP_14   out std_logic
BF_DOUT_CTP_15   out std_logic
BF_DOUT_CTP_16   out std_logic
BF_DOUT_CTP_17   out std_logic
BF_DOUT_CTP_18   out std_logic
BF_DOUT_CTP_19   out std_logic
BF_DOUT_CTP_20   out std_logic
BF_DOUT_CTP_21   out std_logic
BF_DOUT_CTP_22   out std_logic
BF_DOUT_CTP_23   out std_logic
BF_DOUT_CTP_24   out std_logic
BF_DOUT_CTP_25   out std_logic
BF_DOUT_CTP_26   out std_logic
BF_DOUT_CTP_27   out std_logic
BF_DOUT_CTP_28   out std_logic
BF_DOUT_CTP_29   out std_logic
BF_DOUT_CTP_30   out std_logic
BF_DOUT_CTP_31   out std_logic
BF_DOUT_CTP_64   out std_logic
BF_DOUT_CTP_32   out std_logic
BF_DOUT_CTP_33   out std_logic
BF_DOUT_CTP_34   out std_logic
BF_DOUT_CTP_35   out std_logic
BF_DOUT_CTP_36   out std_logic
BF_DOUT_CTP_37   out std_logic
BF_DOUT_CTP_38   out std_logic
BF_DOUT_CTP_39   out std_logic
BF_DOUT_CTP_40   out std_logic
BF_DOUT_CTP_41   out std_logic
BF_DOUT_CTP_42   out std_logic
BF_DOUT_CTP_43   out std_logic
BF_DOUT_CTP_44   out std_logic
BF_DOUT_CTP_45   out std_logic
BF_DOUT_CTP_46   out std_logic
BF_DOUT_CTP_47   out std_logic
BF_DOUT_CTP_48   out std_logic
BF_DOUT_CTP_49   out std_logic
BF_DOUT_CTP_50   out std_logic
BF_DOUT_CTP_51   out std_logic
BF_DOUT_CTP_52   out std_logic
BF_DOUT_CTP_53   out std_logic
BF_DOUT_CTP_54   out std_logic
BF_DOUT_CTP_55   out std_logic
BF_DOUT_CTP_56   out std_logic
BF_DOUT_CTP_57   out std_logic
BF_DOUT_CTP_58   out std_logic
BF_DOUT_CTP_59   out std_logic
BF_DOUT_CTP_60   out std_logic
BF_DOUT_CTP_61   out std_logic
BF_DOUT_CTP_62   out std_logic
BF_DOUT_CTP_63   out std_logic
BF_DOUT_CTP_65   out std_logic
D_CBL_00_B   out std_logic
D_CBL_01_B   out std_logic
D_CBL_02_B   out std_logic
D_CBL_03_B   out std_logic
D_CBL_04_B   out std_logic
D_CBL_05_B   out std_logic
D_CBL_06_B   out std_logic
D_CBL_07_B   out std_logic
D_CBL_08_B   out std_logic
D_CBL_09_B   out std_logic
D_CBL_10_B   out std_logic
D_CBL_11_B   out std_logic
D_CBL_12_B   out std_logic
D_CBL_13_B   out std_logic
D_CBL_14_B   out std_logic
D_CBL_15_B   out std_logic
D_CBL_16_B   out std_logic
D_CBL_17_B   out std_logic
D_CBL_18_B   out std_logic
D_CBL_19_B   out std_logic
D_CBL_20_B   out std_logic
D_CBL_21_B   out std_logic
D_CBL_22_B   out std_logic
D_CBL_23_B   out std_logic
D_CBL_24_B   out std_logic
D_CBL_25_B   out std_logic
D_CBL_26_B   out std_logic
D_CBL_81_B   out std_logic
D_CBL_27_B   out std_logic
D_CBL_28_B   out std_logic
D_CBL_29_B   out std_logic
D_CBL_30_B   out std_logic
D_CBL_31_B   out std_logic
D_CBL_32_B   out std_logic
D_CBL_33_B   out std_logic
D_CBL_34_B   out std_logic
D_CBL_35_B   out std_logic
D_CBL_36_B   out std_logic
D_CBL_37_B   out std_logic
D_CBL_38_B   out std_logic
D_CBL_39_B   out std_logic
D_CBL_40_B   out std_logic
D_CBL_41_B   out std_logic
D_CBL_42_B   out std_logic
D_CBL_43_B   out std_logic
D_CBL_44_B   out std_logic
D_CBL_45_B   out std_logic
D_CBL_46_B   out std_logic
D_CBL_47_B   out std_logic
D_CBL_48_B   out std_logic
D_CBL_49_B   out std_logic
D_CBL_50_B   out std_logic
D_CBL_51_B   out std_logic
D_CBL_52_B   out std_logic
D_CBL_53_B   out std_logic
D_CBL_82_B   out std_logic
D_CBL_54_B   out std_logic
D_CBL_55_B   out std_logic
D_CBL_56_B   out std_logic
D_CBL_57_B   out std_logic
D_CBL_58_B   out std_logic
D_CBL_59_B   out std_logic
D_CBL_60_B   out std_logic
D_CBL_61_B   out std_logic
D_CBL_62_B   out std_logic
D_CBL_63_B   out std_logic
D_CBL_64_B   out std_logic
D_CBL_65_B   out std_logic
D_CBL_66_B   out std_logic
D_CBL_67_B   out std_logic
D_CBL_68_B   out std_logic
D_CBL_69_B   out std_logic
D_CBL_70_B   out std_logic
D_CBL_71_B   out std_logic
D_CBL_72_B   out std_logic
D_CBL_73_B   out std_logic
D_CBL_74_B   out std_logic
D_CBL_75_B   out std_logic
D_CBL_76_B   out std_logic
D_CBL_77_B   out std_logic
D_CBL_78_B   out std_logic
D_CBL_79_B   out std_logic
D_CBL_80_B   out std_logic
D_CBL_83_B   out std_logic
BF_TO_TP_DAQ_SLINK_RETURN_DIR   in std_logic
BF_TO_TP_DAQ_SLINK_RETURN_CMP   in std_logic
BF_TO_TP_ROI_SLINK_RETURN_DIR   in std_logic
BF_TO_TP_ROI_SLINK_RETURN_CMP   in std_logic
BUF_TTC_L1_ACCEPT   in std_logic
BUF_TTC_BNCH_CNT_RES   in std_logic
CLK_120MHz000_XTAL_1_BF_TRNCV_DIR   in std_logic
CLK_120MHz000_XTAL_1_BF_TRNCV_CMP   in std_logic
BF_DAQ_DATA_OUT_DIR   out std_logic
BF_DAQ_DATA_OUT_CMP   out std_logic
BF_ROI_DATA_OUT_DIR   out std_logic
BF_ROI_DATA_OUT_CMP   out std_logic
MP1_F01_QUAD_110_TRN_0_DIR   out std_logic
MP1_F01_QUAD_110_TRN_0_CMP   out std_logic
MP1_F03_QUAD_110_TRN_1_DIR   out std_logic
MP1_F03_QUAD_110_TRN_1_CMP   out std_logic
MP1_F07_QUAD_110_TRN_2_DIR   out std_logic
MP1_F07_QUAD_110_TRN_2_CMP   out std_logic
MP1_F05_QUAD_110_TRN_3_DIR   out std_logic
MP1_F05_QUAD_110_TRN_3_CMP   out std_logic
MP1_F09_QUAD_111_TRN_0_DIR   out std_logic
MP1_F09_QUAD_111_TRN_0_CMP   out std_logic
MP1_F11_QUAD_111_TRN_1_DIR   out std_logic
MP1_F11_QUAD_111_TRN_1_CMP   out std_logic
MP1_F10_QUAD_111_TRN_2_DIR   out std_logic
MP1_F10_QUAD_111_TRN_2_CMP   out std_logic
MP1_F08_QUAD_111_TRN_3_DIR   out std_logic
MP1_F08_QUAD_111_TRN_3_CMP   out std_logic
MP1_F04_QUAD_112_TRN_0_DIR   out std_logic
MP1_F04_QUAD_112_TRN_0_CMP   out std_logic
MP1_F06_QUAD_112_TRN_1_DIR   out std_logic
MP1_F06_QUAD_112_TRN_1_CMP   out std_logic
MP1_F02_QUAD_112_TRN_2_DIR   out std_logic
MP1_F02_QUAD_112_TRN_2_CMP   out std_logic
MP1_F00_QUAD_112_TRN_3_DIR   out std_logic
MP1_F00_QUAD_112_TRN_3_CMP   out std_logic
MP2_F01_QUAD_113_TRN_0_DIR   out std_logic
MP2_F01_QUAD_113_TRN_0_CMP   out std_logic
MP2_F03_QUAD_113_TRN_1_DIR   out std_logic
MP2_F03_QUAD_113_TRN_1_CMP   out std_logic
MP2_F07_QUAD_113_TRN_2_DIR   out std_logic
MP2_F07_QUAD_113_TRN_2_CMP   out std_logic
MP2_F05_QUAD_113_TRN_3_DIR   out std_logic
MP2_F05_QUAD_113_TRN_3_CMP   out std_logic
MP2_F09_QUAD_114_TRN_0_DIR   out std_logic
MP2_F09_QUAD_114_TRN_0_CMP   out std_logic
MP2_F11_QUAD_114_TRN_1_DIR   out std_logic
MP2_F11_QUAD_114_TRN_1_CMP   out std_logic
MP2_F10_QUAD_114_TRN_2_DIR   out std_logic
MP2_F10_QUAD_114_TRN_2_CMP   out std_logic
MP2_F08_QUAD_114_TRN_3_DIR   out std_logic
MP2_F08_QUAD_114_TRN_3_CMP   out std_logic
MP2_F04_QUAD_115_TRN_0_DIR   out std_logic
MP2_F04_QUAD_115_TRN_0_CMP   out std_logic
MP2_F06_QUAD_115_TRN_1_DIR   out std_logic
MP2_F06_QUAD_115_TRN_1_CMP   out std_logic
MP2_F02_QUAD_115_TRN_2_DIR   out std_logic
MP2_F02_QUAD_115_TRN_2_CMP   out std_logic
MP2_F00_QUAD_115_TRN_3_DIR   out std_logic
MP2_F00_QUAD_115_TRN_3_CMP   out std_logic
CLK_320MHz64_LHC_BF_QUAD_111_DIR   in std_logic
CLK_320MHz64_LHC_BF_QUAD_111_CMP   in std_logic
CLK_320MHz64_LHC_BF_QUAD_114_DIR   in std_logic
CLK_320MHz64_LHC_BF_QUAD_114_CMP   in std_logic
RXN_IN   in std_logic_vector ( ( num_GTX_per_group * num_GTX_groups ) - 1 downto 0 )
RXP_IN   in std_logic_vector ( ( num_GTX_per_group * num_GTX_groups ) - 1 downto 0 )
D_CBL_00_B   in std_logic
D_CBL_01_B   in std_logic
D_CBL_02_B   in std_logic
D_CBL_03_B   in std_logic
D_CBL_04_B   in std_logic
D_CBL_05_B   in std_logic
D_CBL_06_B   in std_logic
D_CBL_07_B   in std_logic
D_CBL_08_B   in std_logic
D_CBL_09_B   in std_logic
D_CBL_10_B   in std_logic
D_CBL_11_B   in std_logic
D_CBL_12_B   in std_logic
D_CBL_13_B   in std_logic
D_CBL_14_B   in std_logic
D_CBL_15_B   in std_logic
D_CBL_16_B   in std_logic
D_CBL_17_B   in std_logic
D_CBL_18_B   in std_logic
D_CBL_19_B   in std_logic
D_CBL_20_B   in std_logic
D_CBL_21_B   in std_logic
D_CBL_22_B   in std_logic
D_CBL_23_B   in std_logic
D_CBL_24_B   in std_logic
D_CBL_25_B   in std_logic
D_CBL_26_B   in std_logic
D_CBL_81_B   in std_logic
D_CBL_27_B   in std_logic
D_CBL_28_B   in std_logic
D_CBL_29_B   in std_logic
D_CBL_30_B   in std_logic
D_CBL_31_B   in std_logic
D_CBL_32_B   in std_logic
D_CBL_33_B   in std_logic
D_CBL_34_B   in std_logic
D_CBL_35_B   in std_logic
D_CBL_36_B   in std_logic
D_CBL_37_B   in std_logic
D_CBL_38_B   in std_logic
D_CBL_39_B   in std_logic
D_CBL_40_B   in std_logic
D_CBL_41_B   in std_logic
D_CBL_42_B   in std_logic
D_CBL_43_B   in std_logic
D_CBL_44_B   in std_logic
D_CBL_45_B   in std_logic
D_CBL_46_B   in std_logic
D_CBL_47_B   in std_logic
D_CBL_48_B   in std_logic
D_CBL_49_B   in std_logic
D_CBL_50_B   in std_logic
D_CBL_51_B   in std_logic
D_CBL_52_B   in std_logic
D_CBL_53_B   in std_logic
D_CBL_82_B   in std_logic
D_CBL_54_B   in std_logic
D_CBL_55_B   in std_logic
D_CBL_56_B   in std_logic
D_CBL_57_B   in std_logic
D_CBL_58_B   in std_logic
D_CBL_59_B   in std_logic
D_CBL_60_B   in std_logic
D_CBL_61_B   in std_logic
D_CBL_62_B   in std_logic
D_CBL_63_B   in std_logic
D_CBL_64_B   in std_logic
D_CBL_65_B   in std_logic
D_CBL_66_B   in std_logic
D_CBL_67_B   in std_logic
D_CBL_68_B   in std_logic
D_CBL_69_B   in std_logic
D_CBL_70_B   in std_logic
D_CBL_71_B   in std_logic
D_CBL_72_B   in std_logic
D_CBL_73_B   in std_logic
D_CBL_74_B   in std_logic
D_CBL_75_B   in std_logic
D_CBL_76_B   in std_logic
D_CBL_77_B   in std_logic
D_CBL_78_B   in std_logic
D_CBL_79_B   in std_logic
D_CBL_80_B   in std_logic
D_CBL_83_B   in std_logic

Detailed Description

Definition at line 23 of file CMX_top_Base.vhd.

Member Data Documentation

BF_DAQ_DATA_OUT_CMP out std_logic
Port

Definition at line 705 of file CMX_top_Base.vhd.

BF_DAQ_DATA_OUT_DIR out std_logic
Port

Definition at line 704 of file CMX_top_Base.vhd.

BF_DEBUG_0 out std_logic
Port

Definition at line 506 of file CMX_top_Base.vhd.

BF_DEBUG_1 out std_logic
Port

Definition at line 507 of file CMX_top_Base.vhd.

BF_DEBUG_2 out std_logic
Port

Definition at line 508 of file CMX_top_Base.vhd.

BF_DEBUG_3 out std_logic
Port

Definition at line 509 of file CMX_top_Base.vhd.

BF_DEBUG_4 out std_logic
Port

Definition at line 510 of file CMX_top_Base.vhd.

BF_DEBUG_5 out std_logic
Port

Definition at line 511 of file CMX_top_Base.vhd.

BF_DEBUG_6 out std_logic
Port

Definition at line 512 of file CMX_top_Base.vhd.

BF_DEBUG_7 out std_logic
Port

Definition at line 513 of file CMX_top_Base.vhd.

BF_DEBUG_8 out std_logic
Port

Definition at line 514 of file CMX_top_Base.vhd.

BF_DEBUG_9 out std_logic
Port

Definition at line 515 of file CMX_top_Base.vhd.

BF_DOUT_CTP_00 out std_logic
Port

Definition at line 538 of file CMX_top_Base.vhd.

BF_DOUT_CTP_01 out std_logic
Port

Definition at line 539 of file CMX_top_Base.vhd.

BF_DOUT_CTP_02 out std_logic
Port

Definition at line 540 of file CMX_top_Base.vhd.

BF_DOUT_CTP_03 out std_logic
Port

Definition at line 541 of file CMX_top_Base.vhd.

BF_DOUT_CTP_04 out std_logic
Port

Definition at line 542 of file CMX_top_Base.vhd.

BF_DOUT_CTP_05 out std_logic
Port

Definition at line 543 of file CMX_top_Base.vhd.

BF_DOUT_CTP_06 out std_logic
Port

Definition at line 544 of file CMX_top_Base.vhd.

BF_DOUT_CTP_07 out std_logic
Port

Definition at line 545 of file CMX_top_Base.vhd.

BF_DOUT_CTP_08 out std_logic
Port

Definition at line 546 of file CMX_top_Base.vhd.

BF_DOUT_CTP_09 out std_logic
Port

Definition at line 547 of file CMX_top_Base.vhd.

BF_DOUT_CTP_10 out std_logic
Port

Definition at line 548 of file CMX_top_Base.vhd.

BF_DOUT_CTP_11 out std_logic
Port

Definition at line 549 of file CMX_top_Base.vhd.

BF_DOUT_CTP_12 out std_logic
Port

Definition at line 550 of file CMX_top_Base.vhd.

BF_DOUT_CTP_13 out std_logic
Port

Definition at line 551 of file CMX_top_Base.vhd.

BF_DOUT_CTP_14 out std_logic
Port

Definition at line 552 of file CMX_top_Base.vhd.

BF_DOUT_CTP_15 out std_logic
Port

Definition at line 553 of file CMX_top_Base.vhd.

BF_DOUT_CTP_16 out std_logic
Port

Definition at line 554 of file CMX_top_Base.vhd.

BF_DOUT_CTP_17 out std_logic
Port

Definition at line 555 of file CMX_top_Base.vhd.

BF_DOUT_CTP_18 out std_logic
Port

Definition at line 556 of file CMX_top_Base.vhd.

BF_DOUT_CTP_19 out std_logic
Port

Definition at line 557 of file CMX_top_Base.vhd.

BF_DOUT_CTP_20 out std_logic
Port

Definition at line 558 of file CMX_top_Base.vhd.

BF_DOUT_CTP_21 out std_logic
Port

Definition at line 559 of file CMX_top_Base.vhd.

BF_DOUT_CTP_22 out std_logic
Port

Definition at line 560 of file CMX_top_Base.vhd.

BF_DOUT_CTP_23 out std_logic
Port

Definition at line 561 of file CMX_top_Base.vhd.

BF_DOUT_CTP_24 out std_logic
Port

Definition at line 562 of file CMX_top_Base.vhd.

BF_DOUT_CTP_25 out std_logic
Port

Definition at line 563 of file CMX_top_Base.vhd.

BF_DOUT_CTP_26 out std_logic
Port

Definition at line 564 of file CMX_top_Base.vhd.

BF_DOUT_CTP_27 out std_logic
Port

Definition at line 565 of file CMX_top_Base.vhd.

BF_DOUT_CTP_28 out std_logic
Port

Definition at line 566 of file CMX_top_Base.vhd.

BF_DOUT_CTP_29 out std_logic
Port

Definition at line 567 of file CMX_top_Base.vhd.

BF_DOUT_CTP_30 out std_logic
Port

Definition at line 568 of file CMX_top_Base.vhd.

BF_DOUT_CTP_31 out std_logic
Port

Definition at line 569 of file CMX_top_Base.vhd.

BF_DOUT_CTP_32 out std_logic
Port

Definition at line 572 of file CMX_top_Base.vhd.

BF_DOUT_CTP_33 out std_logic
Port

Definition at line 573 of file CMX_top_Base.vhd.

BF_DOUT_CTP_34 out std_logic
Port

Definition at line 574 of file CMX_top_Base.vhd.

BF_DOUT_CTP_35 out std_logic
Port

Definition at line 575 of file CMX_top_Base.vhd.

BF_DOUT_CTP_36 out std_logic
Port

Definition at line 576 of file CMX_top_Base.vhd.

BF_DOUT_CTP_37 out std_logic
Port

Definition at line 577 of file CMX_top_Base.vhd.

BF_DOUT_CTP_38 out std_logic
Port

Definition at line 578 of file CMX_top_Base.vhd.

BF_DOUT_CTP_39 out std_logic
Port

Definition at line 579 of file CMX_top_Base.vhd.

BF_DOUT_CTP_40 out std_logic
Port

Definition at line 580 of file CMX_top_Base.vhd.

BF_DOUT_CTP_41 out std_logic
Port

Definition at line 581 of file CMX_top_Base.vhd.

BF_DOUT_CTP_42 out std_logic
Port

Definition at line 582 of file CMX_top_Base.vhd.

BF_DOUT_CTP_43 out std_logic
Port

Definition at line 583 of file CMX_top_Base.vhd.

BF_DOUT_CTP_44 out std_logic
Port

Definition at line 584 of file CMX_top_Base.vhd.

BF_DOUT_CTP_45 out std_logic
Port

Definition at line 585 of file CMX_top_Base.vhd.

BF_DOUT_CTP_46 out std_logic
Port

Definition at line 586 of file CMX_top_Base.vhd.

BF_DOUT_CTP_47 out std_logic
Port

Definition at line 587 of file CMX_top_Base.vhd.

BF_DOUT_CTP_48 out std_logic
Port

Definition at line 588 of file CMX_top_Base.vhd.

BF_DOUT_CTP_49 out std_logic
Port

Definition at line 589 of file CMX_top_Base.vhd.

BF_DOUT_CTP_50 out std_logic
Port

Definition at line 590 of file CMX_top_Base.vhd.

BF_DOUT_CTP_51 out std_logic
Port

Definition at line 591 of file CMX_top_Base.vhd.

BF_DOUT_CTP_52 out std_logic
Port

Definition at line 592 of file CMX_top_Base.vhd.

BF_DOUT_CTP_53 out std_logic
Port

Definition at line 593 of file CMX_top_Base.vhd.

BF_DOUT_CTP_54 out std_logic
Port

Definition at line 594 of file CMX_top_Base.vhd.

BF_DOUT_CTP_55 out std_logic
Port

Definition at line 595 of file CMX_top_Base.vhd.

BF_DOUT_CTP_56 out std_logic
Port

Definition at line 596 of file CMX_top_Base.vhd.

BF_DOUT_CTP_57 out std_logic
Port

Definition at line 597 of file CMX_top_Base.vhd.

BF_DOUT_CTP_58 out std_logic
Port

Definition at line 598 of file CMX_top_Base.vhd.

BF_DOUT_CTP_59 out std_logic
Port

Definition at line 599 of file CMX_top_Base.vhd.

BF_DOUT_CTP_60 out std_logic
Port

Definition at line 600 of file CMX_top_Base.vhd.

BF_DOUT_CTP_61 out std_logic
Port

Definition at line 601 of file CMX_top_Base.vhd.

BF_DOUT_CTP_62 out std_logic
Port

Definition at line 602 of file CMX_top_Base.vhd.

BF_DOUT_CTP_63 out std_logic
Port

Definition at line 603 of file CMX_top_Base.vhd.

BF_DOUT_CTP_64 out std_logic
Port

Definition at line 570 of file CMX_top_Base.vhd.

BF_DOUT_CTP_65 out std_logic
Port

Definition at line 604 of file CMX_top_Base.vhd.

BF_LED_REQ_0 out std_logic
Port

Definition at line 523 of file CMX_top_Base.vhd.

BF_LED_REQ_1 out std_logic
Port

Definition at line 524 of file CMX_top_Base.vhd.

BF_LED_REQ_2 out std_logic
Port

Definition at line 525 of file CMX_top_Base.vhd.

BF_LED_REQ_3 out std_logic
Port

Definition at line 526 of file CMX_top_Base.vhd.

BF_LED_REQ_4 out std_logic
Port

Definition at line 527 of file CMX_top_Base.vhd.

BF_REQ_CABLE_1_INPUT out std_logic
Port

Definition at line 520 of file CMX_top_Base.vhd.

BF_REQ_CABLE_2_INPUT out std_logic
Port

Definition at line 521 of file CMX_top_Base.vhd.

BF_REQ_CABLE_3_INPUT out std_logic
Port

Definition at line 522 of file CMX_top_Base.vhd.

BF_REQ_CTP_1_INPUT out std_logic
Port

Definition at line 518 of file CMX_top_Base.vhd.

BF_REQ_CTP_2_INPUT out std_logic
Port

Definition at line 519 of file CMX_top_Base.vhd.

BF_ROI_DATA_OUT_CMP out std_logic
Port

Definition at line 707 of file CMX_top_Base.vhd.

BF_ROI_DATA_OUT_DIR out std_logic
Port

Definition at line 706 of file CMX_top_Base.vhd.

BF_SYSMON_01_N in STD_LOGIC
Port

Definition at line 66 of file CMX_top_Base.vhd.

BF_SYSMON_01_P in STD_LOGIC
Port

Definition at line 65 of file CMX_top_Base.vhd.

BF_SYSMON_03_N in STD_LOGIC
Port

Definition at line 68 of file CMX_top_Base.vhd.

BF_SYSMON_03_P in STD_LOGIC
Port

Definition at line 67 of file CMX_top_Base.vhd.

BF_SYSMON_04_N in STD_LOGIC
Port

Definition at line 70 of file CMX_top_Base.vhd.

BF_SYSMON_04_P in STD_LOGIC
Port

Definition at line 69 of file CMX_top_Base.vhd.

BF_SYSMON_07_N in STD_LOGIC
Port

Definition at line 72 of file CMX_top_Base.vhd.

BF_SYSMON_07_P in STD_LOGIC
Port

Definition at line 71 of file CMX_top_Base.vhd.

BF_SYSMON_08_N in STD_LOGIC
Port

Definition at line 74 of file CMX_top_Base.vhd.

BF_SYSMON_08_P in STD_LOGIC
Port

Definition at line 73 of file CMX_top_Base.vhd.

BF_SYSMON_09_N in STD_LOGIC
Port

Definition at line 76 of file CMX_top_Base.vhd.

BF_SYSMON_09_P in STD_LOGIC
Port

Definition at line 75 of file CMX_top_Base.vhd.

BF_SYSMON_10_N in STD_LOGIC
Port

Definition at line 78 of file CMX_top_Base.vhd.

BF_SYSMON_10_P in STD_LOGIC
Port

Definition at line 77 of file CMX_top_Base.vhd.

BF_SYSMON_11_N in STD_LOGIC
Port

Definition at line 80 of file CMX_top_Base.vhd.

BF_SYSMON_11_P in STD_LOGIC
Port

Definition at line 79 of file CMX_top_Base.vhd.

BF_SYSMON_12_N in STD_LOGIC
Port

Definition at line 82 of file CMX_top_Base.vhd.

BF_SYSMON_12_P in STD_LOGIC
Port

Definition at line 81 of file CMX_top_Base.vhd.

BF_SYSMON_13_N in STD_LOGIC
Port

Definition at line 84 of file CMX_top_Base.vhd.

BF_SYSMON_13_P in STD_LOGIC
Port

Definition at line 83 of file CMX_top_Base.vhd.

BF_SYSMON_14_N in STD_LOGIC
Port

Definition at line 86 of file CMX_top_Base.vhd.

BF_SYSMON_14_P in STD_LOGIC
Port

Definition at line 85 of file CMX_top_Base.vhd.

BF_SYSMON_15_N in STD_LOGIC
Port

Definition at line 88 of file CMX_top_Base.vhd.

BF_SYSMON_15_P in STD_LOGIC
Port

Definition at line 87 of file CMX_top_Base.vhd.

BF_TO_FROM_BSPT_0 in std_logic
Port

Definition at line 528 of file CMX_top_Base.vhd.

BF_TO_FROM_BSPT_1 in std_logic
Port

Definition at line 529 of file CMX_top_Base.vhd.

BF_TO_FROM_BSPT_2 out std_logic
Port

Definition at line 530 of file CMX_top_Base.vhd.

BF_TO_FROM_BSPT_3 out std_logic
Port

Definition at line 531 of file CMX_top_Base.vhd.

BF_TO_FROM_BSPT_4 out std_logic
Port

Definition at line 532 of file CMX_top_Base.vhd.

BF_TO_FROM_BSPT_5 out std_logic
Port

Definition at line 533 of file CMX_top_Base.vhd.

BF_TO_FROM_BSPT_6 out std_logic
Port

Definition at line 534 of file CMX_top_Base.vhd.

BF_TO_FROM_BSPT_7 out std_logic
Port

Definition at line 535 of file CMX_top_Base.vhd.

BF_TO_TP_DAQ_SLINK_RETURN_CMP in std_logic
Port

Definition at line 694 of file CMX_top_Base.vhd.

BF_TO_TP_DAQ_SLINK_RETURN_DIR in std_logic
Port

Definition at line 693 of file CMX_top_Base.vhd.

BF_TO_TP_ROI_SLINK_RETURN_CMP in std_logic
Port

Definition at line 696 of file CMX_top_Base.vhd.

BF_TO_TP_ROI_SLINK_RETURN_DIR in std_logic
Port

Definition at line 695 of file CMX_top_Base.vhd.

BUF_TTC_BNCH_CNT_RES in std_logic
Port

Definition at line 699 of file CMX_top_Base.vhd.

BUF_TTC_L1_ACCEPT in std_logic
Port

Definition at line 698 of file CMX_top_Base.vhd.

Definition at line 703 of file CMX_top_Base.vhd.

Definition at line 702 of file CMX_top_Base.vhd.

Definition at line 758 of file CMX_top_Base.vhd.

Definition at line 757 of file CMX_top_Base.vhd.

Definition at line 760 of file CMX_top_Base.vhd.

Definition at line 759 of file CMX_top_Base.vhd.

Definition at line 497 of file CMX_top_Base.vhd.

Definition at line 496 of file CMX_top_Base.vhd.

Definition at line 500 of file CMX_top_Base.vhd.

Definition at line 499 of file CMX_top_Base.vhd.

D_CBL_00_B out std_logic
Port

Definition at line 606 of file CMX_top_Base.vhd.

D_CBL_00_B in std_logic
Port

Definition at line 606 of file CMX_top_Base.vhd.

D_CBL_01_B out std_logic
Port

Definition at line 607 of file CMX_top_Base.vhd.

D_CBL_01_B in std_logic
Port

Definition at line 607 of file CMX_top_Base.vhd.

D_CBL_02_B out std_logic
Port

Definition at line 608 of file CMX_top_Base.vhd.

D_CBL_02_B in std_logic
Port

Definition at line 608 of file CMX_top_Base.vhd.

D_CBL_03_B out std_logic
Port

Definition at line 609 of file CMX_top_Base.vhd.

D_CBL_03_B in std_logic
Port

Definition at line 609 of file CMX_top_Base.vhd.

D_CBL_04_B out std_logic
Port

Definition at line 610 of file CMX_top_Base.vhd.

D_CBL_04_B in std_logic
Port

Definition at line 610 of file CMX_top_Base.vhd.

D_CBL_05_B out std_logic
Port

Definition at line 611 of file CMX_top_Base.vhd.

D_CBL_05_B in std_logic
Port

Definition at line 611 of file CMX_top_Base.vhd.

D_CBL_06_B out std_logic
Port

Definition at line 612 of file CMX_top_Base.vhd.

D_CBL_06_B in std_logic
Port

Definition at line 612 of file CMX_top_Base.vhd.

D_CBL_07_B out std_logic
Port

Definition at line 613 of file CMX_top_Base.vhd.

D_CBL_07_B in std_logic
Port

Definition at line 613 of file CMX_top_Base.vhd.

D_CBL_08_B in std_logic
Port

Definition at line 614 of file CMX_top_Base.vhd.

D_CBL_08_B out std_logic
Port

Definition at line 614 of file CMX_top_Base.vhd.

D_CBL_09_B out std_logic
Port

Definition at line 615 of file CMX_top_Base.vhd.

D_CBL_09_B in std_logic
Port

Definition at line 615 of file CMX_top_Base.vhd.

D_CBL_10_B out std_logic
Port

Definition at line 616 of file CMX_top_Base.vhd.

D_CBL_10_B in std_logic
Port

Definition at line 616 of file CMX_top_Base.vhd.

D_CBL_11_B out std_logic
Port

Definition at line 617 of file CMX_top_Base.vhd.

D_CBL_11_B in std_logic
Port

Definition at line 617 of file CMX_top_Base.vhd.

D_CBL_12_B out std_logic
Port

Definition at line 618 of file CMX_top_Base.vhd.

D_CBL_12_B in std_logic
Port

Definition at line 618 of file CMX_top_Base.vhd.

D_CBL_13_B out std_logic
Port

Definition at line 619 of file CMX_top_Base.vhd.

D_CBL_13_B in std_logic
Port

Definition at line 619 of file CMX_top_Base.vhd.

D_CBL_14_B out std_logic
Port

Definition at line 620 of file CMX_top_Base.vhd.

D_CBL_14_B in std_logic
Port

Definition at line 620 of file CMX_top_Base.vhd.

D_CBL_15_B out std_logic
Port

Definition at line 621 of file CMX_top_Base.vhd.

D_CBL_15_B in std_logic
Port

Definition at line 621 of file CMX_top_Base.vhd.

D_CBL_16_B in std_logic
Port

Definition at line 622 of file CMX_top_Base.vhd.

D_CBL_16_B out std_logic
Port

Definition at line 622 of file CMX_top_Base.vhd.

D_CBL_17_B out std_logic
Port

Definition at line 623 of file CMX_top_Base.vhd.

D_CBL_17_B in std_logic
Port

Definition at line 623 of file CMX_top_Base.vhd.

D_CBL_18_B out std_logic
Port

Definition at line 624 of file CMX_top_Base.vhd.

D_CBL_18_B in std_logic
Port

Definition at line 624 of file CMX_top_Base.vhd.

D_CBL_19_B out std_logic
Port

Definition at line 625 of file CMX_top_Base.vhd.

D_CBL_19_B in std_logic
Port

Definition at line 625 of file CMX_top_Base.vhd.

D_CBL_20_B in std_logic
Port

Definition at line 626 of file CMX_top_Base.vhd.

D_CBL_20_B out std_logic
Port

Definition at line 626 of file CMX_top_Base.vhd.

D_CBL_21_B out std_logic
Port

Definition at line 627 of file CMX_top_Base.vhd.

D_CBL_21_B in std_logic
Port

Definition at line 627 of file CMX_top_Base.vhd.

D_CBL_22_B out std_logic
Port

Definition at line 628 of file CMX_top_Base.vhd.

D_CBL_22_B in std_logic
Port

Definition at line 628 of file CMX_top_Base.vhd.

D_CBL_23_B out std_logic
Port

Definition at line 629 of file CMX_top_Base.vhd.

D_CBL_23_B in std_logic
Port

Definition at line 629 of file CMX_top_Base.vhd.

D_CBL_24_B in std_logic
Port

Definition at line 630 of file CMX_top_Base.vhd.

D_CBL_24_B out std_logic
Port

Definition at line 630 of file CMX_top_Base.vhd.

D_CBL_25_B out std_logic
Port

Definition at line 631 of file CMX_top_Base.vhd.

D_CBL_25_B in std_logic
Port

Definition at line 631 of file CMX_top_Base.vhd.

D_CBL_26_B out std_logic
Port

Definition at line 632 of file CMX_top_Base.vhd.

D_CBL_26_B in std_logic
Port

Definition at line 632 of file CMX_top_Base.vhd.

D_CBL_27_B out std_logic
Port

Definition at line 635 of file CMX_top_Base.vhd.

D_CBL_27_B in std_logic
Port

Definition at line 635 of file CMX_top_Base.vhd.

D_CBL_28_B out std_logic
Port

Definition at line 636 of file CMX_top_Base.vhd.

D_CBL_28_B in std_logic
Port

Definition at line 636 of file CMX_top_Base.vhd.

D_CBL_29_B out std_logic
Port

Definition at line 637 of file CMX_top_Base.vhd.

D_CBL_29_B in std_logic
Port

Definition at line 637 of file CMX_top_Base.vhd.

D_CBL_30_B out std_logic
Port

Definition at line 638 of file CMX_top_Base.vhd.

D_CBL_30_B in std_logic
Port

Definition at line 638 of file CMX_top_Base.vhd.

D_CBL_31_B in std_logic
Port

Definition at line 639 of file CMX_top_Base.vhd.

D_CBL_31_B out std_logic
Port

Definition at line 639 of file CMX_top_Base.vhd.

D_CBL_32_B out std_logic
Port

Definition at line 640 of file CMX_top_Base.vhd.

D_CBL_32_B in std_logic
Port

Definition at line 640 of file CMX_top_Base.vhd.

D_CBL_33_B out std_logic
Port

Definition at line 641 of file CMX_top_Base.vhd.

D_CBL_33_B in std_logic
Port

Definition at line 641 of file CMX_top_Base.vhd.

D_CBL_34_B out std_logic
Port

Definition at line 642 of file CMX_top_Base.vhd.

D_CBL_34_B in std_logic
Port

Definition at line 642 of file CMX_top_Base.vhd.

D_CBL_35_B in std_logic
Port

Definition at line 643 of file CMX_top_Base.vhd.

D_CBL_35_B out std_logic
Port

Definition at line 643 of file CMX_top_Base.vhd.

D_CBL_36_B out std_logic
Port

Definition at line 644 of file CMX_top_Base.vhd.

D_CBL_36_B in std_logic
Port

Definition at line 644 of file CMX_top_Base.vhd.

D_CBL_37_B out std_logic
Port

Definition at line 645 of file CMX_top_Base.vhd.

D_CBL_37_B in std_logic
Port

Definition at line 645 of file CMX_top_Base.vhd.

D_CBL_38_B out std_logic
Port

Definition at line 646 of file CMX_top_Base.vhd.

D_CBL_38_B in std_logic
Port

Definition at line 646 of file CMX_top_Base.vhd.

D_CBL_39_B in std_logic
Port

Definition at line 647 of file CMX_top_Base.vhd.

D_CBL_39_B out std_logic
Port

Definition at line 647 of file CMX_top_Base.vhd.

D_CBL_40_B out std_logic
Port

Definition at line 648 of file CMX_top_Base.vhd.

D_CBL_40_B in std_logic
Port

Definition at line 648 of file CMX_top_Base.vhd.

D_CBL_41_B out std_logic
Port

Definition at line 649 of file CMX_top_Base.vhd.

D_CBL_41_B in std_logic
Port

Definition at line 649 of file CMX_top_Base.vhd.

D_CBL_42_B out std_logic
Port

Definition at line 650 of file CMX_top_Base.vhd.

D_CBL_42_B in std_logic
Port

Definition at line 650 of file CMX_top_Base.vhd.

D_CBL_43_B in std_logic
Port

Definition at line 651 of file CMX_top_Base.vhd.

D_CBL_43_B out std_logic
Port

Definition at line 651 of file CMX_top_Base.vhd.

D_CBL_44_B out std_logic
Port

Definition at line 652 of file CMX_top_Base.vhd.

D_CBL_44_B in std_logic
Port

Definition at line 652 of file CMX_top_Base.vhd.

D_CBL_45_B out std_logic
Port

Definition at line 653 of file CMX_top_Base.vhd.

D_CBL_45_B in std_logic
Port

Definition at line 653 of file CMX_top_Base.vhd.

D_CBL_46_B out std_logic
Port

Definition at line 654 of file CMX_top_Base.vhd.

D_CBL_46_B in std_logic
Port

Definition at line 654 of file CMX_top_Base.vhd.

D_CBL_47_B out std_logic
Port

Definition at line 655 of file CMX_top_Base.vhd.

D_CBL_47_B in std_logic
Port

Definition at line 655 of file CMX_top_Base.vhd.

D_CBL_48_B out std_logic
Port

Definition at line 656 of file CMX_top_Base.vhd.

D_CBL_48_B in std_logic
Port

Definition at line 656 of file CMX_top_Base.vhd.

D_CBL_49_B out std_logic
Port

Definition at line 657 of file CMX_top_Base.vhd.

D_CBL_49_B in std_logic
Port

Definition at line 657 of file CMX_top_Base.vhd.

D_CBL_50_B out std_logic
Port

Definition at line 658 of file CMX_top_Base.vhd.

D_CBL_50_B in std_logic
Port

Definition at line 658 of file CMX_top_Base.vhd.

D_CBL_51_B out std_logic
Port

Definition at line 659 of file CMX_top_Base.vhd.

D_CBL_51_B in std_logic
Port

Definition at line 659 of file CMX_top_Base.vhd.

D_CBL_52_B out std_logic
Port

Definition at line 660 of file CMX_top_Base.vhd.

D_CBL_52_B in std_logic
Port

Definition at line 660 of file CMX_top_Base.vhd.

D_CBL_53_B out std_logic
Port

Definition at line 661 of file CMX_top_Base.vhd.

D_CBL_53_B in std_logic
Port

Definition at line 661 of file CMX_top_Base.vhd.

D_CBL_54_B out std_logic
Port

Definition at line 664 of file CMX_top_Base.vhd.

D_CBL_54_B in std_logic
Port

Definition at line 664 of file CMX_top_Base.vhd.

D_CBL_55_B out std_logic
Port

Definition at line 665 of file CMX_top_Base.vhd.

D_CBL_55_B in std_logic
Port

Definition at line 665 of file CMX_top_Base.vhd.

D_CBL_56_B out std_logic
Port

Definition at line 666 of file CMX_top_Base.vhd.

D_CBL_56_B in std_logic
Port

Definition at line 666 of file CMX_top_Base.vhd.

D_CBL_57_B out std_logic
Port

Definition at line 667 of file CMX_top_Base.vhd.

D_CBL_57_B in std_logic
Port

Definition at line 667 of file CMX_top_Base.vhd.

D_CBL_58_B out std_logic
Port

Definition at line 668 of file CMX_top_Base.vhd.

D_CBL_58_B in std_logic
Port

Definition at line 668 of file CMX_top_Base.vhd.

D_CBL_59_B out std_logic
Port

Definition at line 669 of file CMX_top_Base.vhd.

D_CBL_59_B in std_logic
Port

Definition at line 669 of file CMX_top_Base.vhd.

D_CBL_60_B out std_logic
Port

Definition at line 670 of file CMX_top_Base.vhd.

D_CBL_60_B in std_logic
Port

Definition at line 670 of file CMX_top_Base.vhd.

D_CBL_61_B out std_logic
Port

Definition at line 671 of file CMX_top_Base.vhd.

D_CBL_61_B in std_logic
Port

Definition at line 671 of file CMX_top_Base.vhd.

D_CBL_62_B out std_logic
Port

Definition at line 672 of file CMX_top_Base.vhd.

D_CBL_62_B in std_logic
Port

Definition at line 672 of file CMX_top_Base.vhd.

D_CBL_63_B out std_logic
Port

Definition at line 673 of file CMX_top_Base.vhd.

D_CBL_63_B in std_logic
Port

Definition at line 673 of file CMX_top_Base.vhd.

D_CBL_64_B out std_logic
Port

Definition at line 674 of file CMX_top_Base.vhd.

D_CBL_64_B in std_logic
Port

Definition at line 674 of file CMX_top_Base.vhd.

D_CBL_65_B out std_logic
Port

Definition at line 675 of file CMX_top_Base.vhd.

D_CBL_65_B in std_logic
Port

Definition at line 675 of file CMX_top_Base.vhd.

D_CBL_66_B out std_logic
Port

Definition at line 676 of file CMX_top_Base.vhd.

D_CBL_66_B in std_logic
Port

Definition at line 676 of file CMX_top_Base.vhd.

D_CBL_67_B out std_logic
Port

Definition at line 677 of file CMX_top_Base.vhd.

D_CBL_67_B in std_logic
Port

Definition at line 677 of file CMX_top_Base.vhd.

D_CBL_68_B out std_logic
Port

Definition at line 678 of file CMX_top_Base.vhd.

D_CBL_68_B in std_logic
Port

Definition at line 678 of file CMX_top_Base.vhd.

D_CBL_69_B out std_logic
Port

Definition at line 679 of file CMX_top_Base.vhd.

D_CBL_69_B in std_logic
Port

Definition at line 679 of file CMX_top_Base.vhd.

D_CBL_70_B out std_logic
Port

Definition at line 680 of file CMX_top_Base.vhd.

D_CBL_70_B in std_logic
Port

Definition at line 680 of file CMX_top_Base.vhd.

D_CBL_71_B out std_logic
Port

Definition at line 681 of file CMX_top_Base.vhd.

D_CBL_71_B in std_logic
Port

Definition at line 681 of file CMX_top_Base.vhd.

D_CBL_72_B out std_logic
Port

Definition at line 682 of file CMX_top_Base.vhd.

D_CBL_72_B in std_logic
Port

Definition at line 682 of file CMX_top_Base.vhd.

D_CBL_73_B out std_logic
Port

Definition at line 683 of file CMX_top_Base.vhd.

D_CBL_73_B in std_logic
Port

Definition at line 683 of file CMX_top_Base.vhd.

D_CBL_74_B out std_logic
Port

Definition at line 684 of file CMX_top_Base.vhd.

D_CBL_74_B in std_logic
Port

Definition at line 684 of file CMX_top_Base.vhd.

D_CBL_75_B out std_logic
Port

Definition at line 685 of file CMX_top_Base.vhd.

D_CBL_75_B in std_logic
Port

Definition at line 685 of file CMX_top_Base.vhd.

D_CBL_76_B out std_logic
Port

Definition at line 686 of file CMX_top_Base.vhd.

D_CBL_76_B in std_logic
Port

Definition at line 686 of file CMX_top_Base.vhd.

D_CBL_77_B out std_logic
Port

Definition at line 687 of file CMX_top_Base.vhd.

D_CBL_77_B in std_logic
Port

Definition at line 687 of file CMX_top_Base.vhd.

D_CBL_78_B out std_logic
Port

Definition at line 688 of file CMX_top_Base.vhd.

D_CBL_78_B in std_logic
Port

Definition at line 688 of file CMX_top_Base.vhd.

D_CBL_79_B out std_logic
Port

Definition at line 689 of file CMX_top_Base.vhd.

D_CBL_79_B in std_logic
Port

Definition at line 689 of file CMX_top_Base.vhd.

D_CBL_80_B out std_logic
Port

Definition at line 690 of file CMX_top_Base.vhd.

D_CBL_80_B in std_logic
Port

Definition at line 690 of file CMX_top_Base.vhd.

D_CBL_81_B out std_logic
Port

Definition at line 633 of file CMX_top_Base.vhd.

D_CBL_81_B in std_logic
Port

Definition at line 633 of file CMX_top_Base.vhd.

D_CBL_82_B out std_logic
Port

Definition at line 662 of file CMX_top_Base.vhd.

D_CBL_82_B in std_logic
Port

Definition at line 662 of file CMX_top_Base.vhd.

D_CBL_83_B out std_logic
Port

Definition at line 691 of file CMX_top_Base.vhd.

D_CBL_83_B in std_logic
Port

Definition at line 691 of file CMX_top_Base.vhd.

IEEE
Library

Definition at line 8 of file CMX_top_Base.vhd.

Definition at line 10 of file CMX_top_Base.vhd.

Definition at line 9 of file CMX_top_Base.vhd.

MP1_F00_QUAD_112_TRN_3_CMP out std_logic
Port

Definition at line 732 of file CMX_top_Base.vhd.

MP1_F00_QUAD_112_TRN_3_DIR out std_logic
Port

Definition at line 731 of file CMX_top_Base.vhd.

MP1_F01_QUAD_110_TRN_0_CMP out std_logic
Port

Definition at line 710 of file CMX_top_Base.vhd.

MP1_F01_QUAD_110_TRN_0_DIR out std_logic
Port

Definition at line 709 of file CMX_top_Base.vhd.

MP1_F02_QUAD_112_TRN_2_CMP out std_logic
Port

Definition at line 730 of file CMX_top_Base.vhd.

MP1_F02_QUAD_112_TRN_2_DIR out std_logic
Port

Definition at line 729 of file CMX_top_Base.vhd.

MP1_F03_QUAD_110_TRN_1_CMP out std_logic
Port

Definition at line 712 of file CMX_top_Base.vhd.

MP1_F03_QUAD_110_TRN_1_DIR out std_logic
Port

Definition at line 711 of file CMX_top_Base.vhd.

MP1_F04_QUAD_112_TRN_0_CMP out std_logic
Port

Definition at line 726 of file CMX_top_Base.vhd.

MP1_F04_QUAD_112_TRN_0_DIR out std_logic
Port

Definition at line 725 of file CMX_top_Base.vhd.

MP1_F05_QUAD_110_TRN_3_CMP out std_logic
Port

Definition at line 716 of file CMX_top_Base.vhd.

MP1_F05_QUAD_110_TRN_3_DIR out std_logic
Port

Definition at line 715 of file CMX_top_Base.vhd.

MP1_F06_QUAD_112_TRN_1_CMP out std_logic
Port

Definition at line 728 of file CMX_top_Base.vhd.

MP1_F06_QUAD_112_TRN_1_DIR out std_logic
Port

Definition at line 727 of file CMX_top_Base.vhd.

MP1_F07_QUAD_110_TRN_2_CMP out std_logic
Port

Definition at line 714 of file CMX_top_Base.vhd.

MP1_F07_QUAD_110_TRN_2_DIR out std_logic
Port

Definition at line 713 of file CMX_top_Base.vhd.

MP1_F08_QUAD_111_TRN_3_CMP out std_logic
Port

Definition at line 724 of file CMX_top_Base.vhd.

MP1_F08_QUAD_111_TRN_3_DIR out std_logic
Port

Definition at line 723 of file CMX_top_Base.vhd.

MP1_F09_QUAD_111_TRN_0_CMP out std_logic
Port

Definition at line 718 of file CMX_top_Base.vhd.

MP1_F09_QUAD_111_TRN_0_DIR out std_logic
Port

Definition at line 717 of file CMX_top_Base.vhd.

MP1_F10_QUAD_111_TRN_2_CMP out std_logic
Port

Definition at line 722 of file CMX_top_Base.vhd.

MP1_F10_QUAD_111_TRN_2_DIR out std_logic
Port

Definition at line 721 of file CMX_top_Base.vhd.

MP1_F11_QUAD_111_TRN_1_CMP out std_logic
Port

Definition at line 720 of file CMX_top_Base.vhd.

MP1_F11_QUAD_111_TRN_1_DIR out std_logic
Port

Definition at line 719 of file CMX_top_Base.vhd.

MP2_F00_QUAD_115_TRN_3_CMP out std_logic
Port

Definition at line 756 of file CMX_top_Base.vhd.

MP2_F00_QUAD_115_TRN_3_DIR out std_logic
Port

Definition at line 755 of file CMX_top_Base.vhd.

MP2_F01_QUAD_113_TRN_0_CMP out std_logic
Port

Definition at line 734 of file CMX_top_Base.vhd.

MP2_F01_QUAD_113_TRN_0_DIR out std_logic
Port

Definition at line 733 of file CMX_top_Base.vhd.

MP2_F02_QUAD_115_TRN_2_CMP out std_logic
Port

Definition at line 754 of file CMX_top_Base.vhd.

MP2_F02_QUAD_115_TRN_2_DIR out std_logic
Port

Definition at line 753 of file CMX_top_Base.vhd.

MP2_F03_QUAD_113_TRN_1_CMP out std_logic
Port

Definition at line 736 of file CMX_top_Base.vhd.

MP2_F03_QUAD_113_TRN_1_DIR out std_logic
Port

Definition at line 735 of file CMX_top_Base.vhd.

MP2_F04_QUAD_115_TRN_0_CMP out std_logic
Port

Definition at line 750 of file CMX_top_Base.vhd.

MP2_F04_QUAD_115_TRN_0_DIR out std_logic
Port

Definition at line 749 of file CMX_top_Base.vhd.

MP2_F05_QUAD_113_TRN_3_CMP out std_logic
Port

Definition at line 740 of file CMX_top_Base.vhd.

MP2_F05_QUAD_113_TRN_3_DIR out std_logic
Port

Definition at line 739 of file CMX_top_Base.vhd.

MP2_F06_QUAD_115_TRN_1_CMP out std_logic
Port

Definition at line 752 of file CMX_top_Base.vhd.

MP2_F06_QUAD_115_TRN_1_DIR out std_logic
Port

Definition at line 751 of file CMX_top_Base.vhd.

MP2_F07_QUAD_113_TRN_2_CMP out std_logic
Port

Definition at line 738 of file CMX_top_Base.vhd.

MP2_F07_QUAD_113_TRN_2_DIR out std_logic
Port

Definition at line 737 of file CMX_top_Base.vhd.

MP2_F08_QUAD_114_TRN_3_CMP out std_logic
Port

Definition at line 748 of file CMX_top_Base.vhd.

MP2_F08_QUAD_114_TRN_3_DIR out std_logic
Port

Definition at line 747 of file CMX_top_Base.vhd.

MP2_F09_QUAD_114_TRN_0_CMP out std_logic
Port

Definition at line 742 of file CMX_top_Base.vhd.

MP2_F09_QUAD_114_TRN_0_DIR out std_logic
Port

Definition at line 741 of file CMX_top_Base.vhd.

MP2_F10_QUAD_114_TRN_2_CMP out std_logic
Port

Definition at line 746 of file CMX_top_Base.vhd.

MP2_F10_QUAD_114_TRN_2_DIR out std_logic
Port

Definition at line 745 of file CMX_top_Base.vhd.

MP2_F11_QUAD_114_TRN_1_CMP out std_logic
Port

Definition at line 744 of file CMX_top_Base.vhd.

MP2_F11_QUAD_114_TRN_1_DIR out std_logic
Port

Definition at line 743 of file CMX_top_Base.vhd.

OCB_A01 in std_logic
Port

Definition at line 32 of file CMX_top_Base.vhd.

OCB_A02 in std_logic
Port

Definition at line 33 of file CMX_top_Base.vhd.

OCB_A03 in std_logic
Port

Definition at line 34 of file CMX_top_Base.vhd.

OCB_A04 in std_logic
Port

Definition at line 35 of file CMX_top_Base.vhd.

OCB_A05 in std_logic
Port

Definition at line 36 of file CMX_top_Base.vhd.

OCB_A06 in std_logic
Port

Definition at line 37 of file CMX_top_Base.vhd.

OCB_A07 in std_logic
Port

Definition at line 38 of file CMX_top_Base.vhd.

OCB_A08 in std_logic
Port

Definition at line 39 of file CMX_top_Base.vhd.

OCB_A09 in std_logic
Port

Definition at line 40 of file CMX_top_Base.vhd.

OCB_A10 in std_logic
Port

Definition at line 41 of file CMX_top_Base.vhd.

OCB_A11 in std_logic
Port

Definition at line 42 of file CMX_top_Base.vhd.

OCB_A12 in std_logic
Port

Definition at line 43 of file CMX_top_Base.vhd.

OCB_A13 in std_logic
Port

Definition at line 44 of file CMX_top_Base.vhd.

OCB_A14 in std_logic
Port

Definition at line 45 of file CMX_top_Base.vhd.

OCB_A15 in std_logic
Port

Definition at line 46 of file CMX_top_Base.vhd.

OCB_A16 in std_logic
Port

Definition at line 47 of file CMX_top_Base.vhd.

OCB_A17 in std_logic
Port

Definition at line 48 of file CMX_top_Base.vhd.

OCB_A18 in std_logic
Port

Definition at line 49 of file CMX_top_Base.vhd.

OCB_A19 in std_logic
Port

Definition at line 50 of file CMX_top_Base.vhd.

OCB_A20 in std_logic
Port

Definition at line 51 of file CMX_top_Base.vhd.

OCB_A21 in std_logic
Port

Definition at line 52 of file CMX_top_Base.vhd.

OCB_A22 in std_logic
Port

Definition at line 53 of file CMX_top_Base.vhd.

OCB_A23 in std_logic
Port

Definition at line 54 of file CMX_top_Base.vhd.

OCB_D inout std_logic_vector ( 15 downto 0 )
Port

Definition at line 62 of file CMX_top_Base.vhd.

OCB_DS_B in std_logic
Port

Definition at line 56 of file CMX_top_Base.vhd.

OCB_GEO_ADRS_0 in std_logic
Port

Definition at line 30 of file CMX_top_Base.vhd.

OCB_SYS_RESET_B in std_logic
Port

Definition at line 60 of file CMX_top_Base.vhd.

OCB_WRITE_B in std_logic
Port

Definition at line 58 of file CMX_top_Base.vhd.

P0_0 in std_logic
Port

Definition at line 91 of file CMX_top_Base.vhd.

P0_1 in std_logic
Port

Definition at line 92 of file CMX_top_Base.vhd.

P0_10 in std_logic
Port

Definition at line 101 of file CMX_top_Base.vhd.

P0_11 in std_logic
Port

Definition at line 102 of file CMX_top_Base.vhd.

P0_12 in std_logic
Port

Definition at line 103 of file CMX_top_Base.vhd.

P0_13 in std_logic
Port

Definition at line 104 of file CMX_top_Base.vhd.

P0_14 in std_logic
Port

Definition at line 105 of file CMX_top_Base.vhd.

P0_15 in std_logic
Port

Definition at line 106 of file CMX_top_Base.vhd.

P0_16 in std_logic
Port

Definition at line 107 of file CMX_top_Base.vhd.

P0_17 in std_logic
Port

Definition at line 108 of file CMX_top_Base.vhd.

P0_18 in std_logic
Port

Definition at line 109 of file CMX_top_Base.vhd.

P0_19 in std_logic
Port

Definition at line 110 of file CMX_top_Base.vhd.

P0_2 in std_logic
Port

Definition at line 93 of file CMX_top_Base.vhd.

P0_20 in std_logic
Port

Definition at line 111 of file CMX_top_Base.vhd.

P0_21 in std_logic
Port

Definition at line 112 of file CMX_top_Base.vhd.

P0_22 in std_logic
Port

Definition at line 113 of file CMX_top_Base.vhd.

P0_23 in std_logic
Port

Definition at line 114 of file CMX_top_Base.vhd.

P0_24 in std_logic
Port

Definition at line 115 of file CMX_top_Base.vhd.

P0_3 in std_logic
Port

Definition at line 94 of file CMX_top_Base.vhd.

P0_4 in std_logic
Port

Definition at line 95 of file CMX_top_Base.vhd.

P0_5 in std_logic
Port

Definition at line 96 of file CMX_top_Base.vhd.

P0_6 in std_logic
Port

Definition at line 97 of file CMX_top_Base.vhd.

P0_7 in std_logic
Port

Definition at line 98 of file CMX_top_Base.vhd.

P0_8 in std_logic
Port

Definition at line 99 of file CMX_top_Base.vhd.

P0_9 in std_logic
Port

Definition at line 100 of file CMX_top_Base.vhd.

P10_0 in std_logic
Port

Definition at line 341 of file CMX_top_Base.vhd.

P10_1 in std_logic
Port

Definition at line 342 of file CMX_top_Base.vhd.

P10_10 in std_logic
Port

Definition at line 351 of file CMX_top_Base.vhd.

P10_11 in std_logic
Port

Definition at line 352 of file CMX_top_Base.vhd.

P10_12 in std_logic
Port

Definition at line 353 of file CMX_top_Base.vhd.

P10_13 in std_logic
Port

Definition at line 354 of file CMX_top_Base.vhd.

P10_14 in std_logic
Port

Definition at line 355 of file CMX_top_Base.vhd.

P10_15 in std_logic
Port

Definition at line 356 of file CMX_top_Base.vhd.

P10_16 in std_logic
Port

Definition at line 357 of file CMX_top_Base.vhd.

P10_17 in std_logic
Port

Definition at line 358 of file CMX_top_Base.vhd.

P10_18 in std_logic
Port

Definition at line 359 of file CMX_top_Base.vhd.

P10_19 in std_logic
Port

Definition at line 360 of file CMX_top_Base.vhd.

P10_2 in std_logic
Port

Definition at line 343 of file CMX_top_Base.vhd.

P10_20 in std_logic
Port

Definition at line 361 of file CMX_top_Base.vhd.

P10_21 in std_logic
Port

Definition at line 362 of file CMX_top_Base.vhd.

P10_22 in std_logic
Port

Definition at line 363 of file CMX_top_Base.vhd.

P10_23 in std_logic
Port

Definition at line 364 of file CMX_top_Base.vhd.

P10_24 in std_logic
Port

Definition at line 365 of file CMX_top_Base.vhd.

P10_3 in std_logic
Port

Definition at line 344 of file CMX_top_Base.vhd.

P10_4 in std_logic
Port

Definition at line 345 of file CMX_top_Base.vhd.

P10_5 in std_logic
Port

Definition at line 346 of file CMX_top_Base.vhd.

P10_6 in std_logic
Port

Definition at line 347 of file CMX_top_Base.vhd.

P10_7 in std_logic
Port

Definition at line 348 of file CMX_top_Base.vhd.

P10_8 in std_logic
Port

Definition at line 349 of file CMX_top_Base.vhd.

P10_9 in std_logic
Port

Definition at line 350 of file CMX_top_Base.vhd.

P11_0 in std_logic
Port

Definition at line 366 of file CMX_top_Base.vhd.

P11_1 in std_logic
Port

Definition at line 367 of file CMX_top_Base.vhd.

P11_10 in std_logic
Port

Definition at line 376 of file CMX_top_Base.vhd.

P11_11 in std_logic
Port

Definition at line 377 of file CMX_top_Base.vhd.

P11_12 in std_logic
Port

Definition at line 378 of file CMX_top_Base.vhd.

P11_13 in std_logic
Port

Definition at line 379 of file CMX_top_Base.vhd.

P11_14 in std_logic
Port

Definition at line 380 of file CMX_top_Base.vhd.

P11_15 in std_logic
Port

Definition at line 381 of file CMX_top_Base.vhd.

P11_16 in std_logic
Port

Definition at line 382 of file CMX_top_Base.vhd.

P11_17 in std_logic
Port

Definition at line 383 of file CMX_top_Base.vhd.

P11_18 in std_logic
Port

Definition at line 384 of file CMX_top_Base.vhd.

P11_19 in std_logic
Port

Definition at line 385 of file CMX_top_Base.vhd.

P11_2 in std_logic
Port

Definition at line 368 of file CMX_top_Base.vhd.

P11_20 in std_logic
Port

Definition at line 386 of file CMX_top_Base.vhd.

P11_21 in std_logic
Port

Definition at line 387 of file CMX_top_Base.vhd.

P11_22 in std_logic
Port

Definition at line 388 of file CMX_top_Base.vhd.

P11_23 in std_logic
Port

Definition at line 389 of file CMX_top_Base.vhd.

P11_24 in std_logic
Port

Definition at line 390 of file CMX_top_Base.vhd.

P11_3 in std_logic
Port

Definition at line 369 of file CMX_top_Base.vhd.

P11_4 in std_logic
Port

Definition at line 370 of file CMX_top_Base.vhd.

P11_5 in std_logic
Port

Definition at line 371 of file CMX_top_Base.vhd.

P11_6 in std_logic
Port

Definition at line 372 of file CMX_top_Base.vhd.

P11_7 in std_logic
Port

Definition at line 373 of file CMX_top_Base.vhd.

P11_8 in std_logic
Port

Definition at line 374 of file CMX_top_Base.vhd.

P11_9 in std_logic
Port

Definition at line 375 of file CMX_top_Base.vhd.

P12_0 in std_logic
Port

Definition at line 391 of file CMX_top_Base.vhd.

P12_1 in std_logic
Port

Definition at line 392 of file CMX_top_Base.vhd.

P12_10 in std_logic
Port

Definition at line 401 of file CMX_top_Base.vhd.

P12_11 in std_logic
Port

Definition at line 402 of file CMX_top_Base.vhd.

P12_12 in std_logic
Port

Definition at line 403 of file CMX_top_Base.vhd.

P12_13 in std_logic
Port

Definition at line 404 of file CMX_top_Base.vhd.

P12_14 in std_logic
Port

Definition at line 405 of file CMX_top_Base.vhd.

P12_15 in std_logic
Port

Definition at line 406 of file CMX_top_Base.vhd.

P12_16 in std_logic
Port

Definition at line 407 of file CMX_top_Base.vhd.

P12_17 in std_logic
Port

Definition at line 408 of file CMX_top_Base.vhd.

P12_18 in std_logic
Port

Definition at line 409 of file CMX_top_Base.vhd.

P12_19 in std_logic
Port

Definition at line 410 of file CMX_top_Base.vhd.

P12_2 in std_logic
Port

Definition at line 393 of file CMX_top_Base.vhd.

P12_20 in std_logic
Port

Definition at line 411 of file CMX_top_Base.vhd.

P12_21 in std_logic
Port

Definition at line 412 of file CMX_top_Base.vhd.

P12_22 in std_logic
Port

Definition at line 413 of file CMX_top_Base.vhd.

P12_23 in std_logic
Port

Definition at line 414 of file CMX_top_Base.vhd.

P12_24 in std_logic
Port

Definition at line 415 of file CMX_top_Base.vhd.

P12_3 in std_logic
Port

Definition at line 394 of file CMX_top_Base.vhd.

P12_4 in std_logic
Port

Definition at line 395 of file CMX_top_Base.vhd.

P12_5 in std_logic
Port

Definition at line 396 of file CMX_top_Base.vhd.

P12_6 in std_logic
Port

Definition at line 397 of file CMX_top_Base.vhd.

P12_7 in std_logic
Port

Definition at line 398 of file CMX_top_Base.vhd.

P12_8 in std_logic
Port

Definition at line 399 of file CMX_top_Base.vhd.

P12_9 in std_logic
Port

Definition at line 400 of file CMX_top_Base.vhd.

P13_0 in std_logic
Port

Definition at line 416 of file CMX_top_Base.vhd.

P13_1 in std_logic
Port

Definition at line 417 of file CMX_top_Base.vhd.

P13_10 in std_logic
Port

Definition at line 426 of file CMX_top_Base.vhd.

P13_11 in std_logic
Port

Definition at line 427 of file CMX_top_Base.vhd.

P13_12 in std_logic
Port

Definition at line 428 of file CMX_top_Base.vhd.

P13_13 in std_logic
Port

Definition at line 429 of file CMX_top_Base.vhd.

P13_14 in std_logic
Port

Definition at line 430 of file CMX_top_Base.vhd.

P13_15 in std_logic
Port

Definition at line 431 of file CMX_top_Base.vhd.

P13_16 in std_logic
Port

Definition at line 432 of file CMX_top_Base.vhd.

P13_17 in std_logic
Port

Definition at line 433 of file CMX_top_Base.vhd.

P13_18 in std_logic
Port

Definition at line 434 of file CMX_top_Base.vhd.

P13_19 in std_logic
Port

Definition at line 435 of file CMX_top_Base.vhd.

P13_2 in std_logic
Port

Definition at line 418 of file CMX_top_Base.vhd.

P13_20 in std_logic
Port

Definition at line 436 of file CMX_top_Base.vhd.

P13_21 in std_logic
Port

Definition at line 437 of file CMX_top_Base.vhd.

P13_22 in std_logic
Port

Definition at line 438 of file CMX_top_Base.vhd.

P13_23 in std_logic
Port

Definition at line 439 of file CMX_top_Base.vhd.

P13_24 in std_logic
Port

Definition at line 440 of file CMX_top_Base.vhd.

P13_3 in std_logic
Port

Definition at line 419 of file CMX_top_Base.vhd.

P13_4 in std_logic
Port

Definition at line 420 of file CMX_top_Base.vhd.

P13_5 in std_logic
Port

Definition at line 421 of file CMX_top_Base.vhd.

P13_6 in std_logic
Port

Definition at line 422 of file CMX_top_Base.vhd.

P13_7 in std_logic
Port

Definition at line 423 of file CMX_top_Base.vhd.

P13_8 in std_logic
Port

Definition at line 424 of file CMX_top_Base.vhd.

P13_9 in std_logic
Port

Definition at line 425 of file CMX_top_Base.vhd.

P14_0 in std_logic
Port

Definition at line 441 of file CMX_top_Base.vhd.

P14_1 in std_logic
Port

Definition at line 442 of file CMX_top_Base.vhd.

P14_10 in std_logic
Port

Definition at line 451 of file CMX_top_Base.vhd.

P14_11 in std_logic
Port

Definition at line 452 of file CMX_top_Base.vhd.

P14_12 in std_logic
Port

Definition at line 453 of file CMX_top_Base.vhd.

P14_13 in std_logic
Port

Definition at line 454 of file CMX_top_Base.vhd.

P14_14 in std_logic
Port

Definition at line 455 of file CMX_top_Base.vhd.

P14_15 in std_logic
Port

Definition at line 456 of file CMX_top_Base.vhd.

P14_16 in std_logic
Port

Definition at line 457 of file CMX_top_Base.vhd.

P14_17 in std_logic
Port

Definition at line 458 of file CMX_top_Base.vhd.

P14_18 in std_logic
Port

Definition at line 459 of file CMX_top_Base.vhd.

P14_19 in std_logic
Port

Definition at line 460 of file CMX_top_Base.vhd.

P14_2 in std_logic
Port

Definition at line 443 of file CMX_top_Base.vhd.

P14_20 in std_logic
Port

Definition at line 461 of file CMX_top_Base.vhd.

P14_21 in std_logic
Port

Definition at line 462 of file CMX_top_Base.vhd.

P14_22 in std_logic
Port

Definition at line 463 of file CMX_top_Base.vhd.

P14_23 in std_logic
Port

Definition at line 464 of file CMX_top_Base.vhd.

P14_24 in std_logic
Port

Definition at line 465 of file CMX_top_Base.vhd.

P14_3 in std_logic
Port

Definition at line 444 of file CMX_top_Base.vhd.

P14_4 in std_logic
Port

Definition at line 445 of file CMX_top_Base.vhd.

P14_5 in std_logic
Port

Definition at line 446 of file CMX_top_Base.vhd.

P14_6 in std_logic
Port

Definition at line 447 of file CMX_top_Base.vhd.

P14_7 in std_logic
Port

Definition at line 448 of file CMX_top_Base.vhd.

P14_8 in std_logic
Port

Definition at line 449 of file CMX_top_Base.vhd.

P14_9 in std_logic
Port

Definition at line 450 of file CMX_top_Base.vhd.

P15_0 in std_logic
Port

Definition at line 466 of file CMX_top_Base.vhd.

P15_1 in std_logic
Port

Definition at line 467 of file CMX_top_Base.vhd.

P15_10 in std_logic
Port

Definition at line 476 of file CMX_top_Base.vhd.

P15_11 in std_logic
Port

Definition at line 477 of file CMX_top_Base.vhd.

P15_12 in std_logic
Port

Definition at line 478 of file CMX_top_Base.vhd.

P15_13 in std_logic
Port

Definition at line 479 of file CMX_top_Base.vhd.

P15_14 in std_logic
Port

Definition at line 480 of file CMX_top_Base.vhd.

P15_15 in std_logic
Port

Definition at line 481 of file CMX_top_Base.vhd.

P15_16 in std_logic
Port

Definition at line 482 of file CMX_top_Base.vhd.

P15_17 in std_logic
Port

Definition at line 483 of file CMX_top_Base.vhd.

P15_18 in std_logic
Port

Definition at line 484 of file CMX_top_Base.vhd.

P15_19 in std_logic
Port

Definition at line 485 of file CMX_top_Base.vhd.

P15_2 in std_logic
Port

Definition at line 468 of file CMX_top_Base.vhd.

P15_20 in std_logic
Port

Definition at line 486 of file CMX_top_Base.vhd.

P15_21 in std_logic
Port

Definition at line 487 of file CMX_top_Base.vhd.

P15_22 in std_logic
Port

Definition at line 488 of file CMX_top_Base.vhd.

P15_23 in std_logic
Port

Definition at line 489 of file CMX_top_Base.vhd.

P15_24 in std_logic
Port

Definition at line 490 of file CMX_top_Base.vhd.

P15_3 in std_logic
Port

Definition at line 469 of file CMX_top_Base.vhd.

P15_4 in std_logic
Port

Definition at line 470 of file CMX_top_Base.vhd.

P15_5 in std_logic
Port

Definition at line 471 of file CMX_top_Base.vhd.

P15_6 in std_logic
Port

Definition at line 472 of file CMX_top_Base.vhd.

P15_7 in std_logic
Port

Definition at line 473 of file CMX_top_Base.vhd.

P15_8 in std_logic
Port

Definition at line 474 of file CMX_top_Base.vhd.

P15_9 in std_logic
Port

Definition at line 475 of file CMX_top_Base.vhd.

P1_0 in std_logic
Port

Definition at line 116 of file CMX_top_Base.vhd.

P1_1 in std_logic
Port

Definition at line 117 of file CMX_top_Base.vhd.

P1_10 in std_logic
Port

Definition at line 126 of file CMX_top_Base.vhd.

P1_11 in std_logic
Port

Definition at line 127 of file CMX_top_Base.vhd.

P1_12 in std_logic
Port

Definition at line 128 of file CMX_top_Base.vhd.

P1_13 in std_logic
Port

Definition at line 129 of file CMX_top_Base.vhd.

P1_14 in std_logic
Port

Definition at line 130 of file CMX_top_Base.vhd.

P1_15 in std_logic
Port

Definition at line 131 of file CMX_top_Base.vhd.

P1_16 in std_logic
Port

Definition at line 132 of file CMX_top_Base.vhd.

P1_17 in std_logic
Port

Definition at line 133 of file CMX_top_Base.vhd.

P1_18 in std_logic
Port

Definition at line 134 of file CMX_top_Base.vhd.

P1_19 in std_logic
Port

Definition at line 135 of file CMX_top_Base.vhd.

P1_2 in std_logic
Port

Definition at line 118 of file CMX_top_Base.vhd.

P1_20 in std_logic
Port

Definition at line 136 of file CMX_top_Base.vhd.

P1_21 in std_logic
Port

Definition at line 137 of file CMX_top_Base.vhd.

P1_22 in std_logic
Port

Definition at line 138 of file CMX_top_Base.vhd.

P1_23 in std_logic
Port

Definition at line 139 of file CMX_top_Base.vhd.

P1_24 in std_logic
Port

Definition at line 140 of file CMX_top_Base.vhd.

P1_3 in std_logic
Port

Definition at line 119 of file CMX_top_Base.vhd.

P1_4 in std_logic
Port

Definition at line 120 of file CMX_top_Base.vhd.

P1_5 in std_logic
Port

Definition at line 121 of file CMX_top_Base.vhd.

P1_6 in std_logic
Port

Definition at line 122 of file CMX_top_Base.vhd.

P1_7 in std_logic
Port

Definition at line 123 of file CMX_top_Base.vhd.

P1_8 in std_logic
Port

Definition at line 124 of file CMX_top_Base.vhd.

P1_9 in std_logic
Port

Definition at line 125 of file CMX_top_Base.vhd.

P2_0 in std_logic
Port

Definition at line 141 of file CMX_top_Base.vhd.

P2_1 in std_logic
Port

Definition at line 142 of file CMX_top_Base.vhd.

P2_10 in std_logic
Port

Definition at line 151 of file CMX_top_Base.vhd.

P2_11 in std_logic
Port

Definition at line 152 of file CMX_top_Base.vhd.

P2_12 in std_logic
Port

Definition at line 153 of file CMX_top_Base.vhd.

P2_13 in std_logic
Port

Definition at line 154 of file CMX_top_Base.vhd.

P2_14 in std_logic
Port

Definition at line 155 of file CMX_top_Base.vhd.

P2_15 in std_logic
Port

Definition at line 156 of file CMX_top_Base.vhd.

P2_16 in std_logic
Port

Definition at line 157 of file CMX_top_Base.vhd.

P2_17 in std_logic
Port

Definition at line 158 of file CMX_top_Base.vhd.

P2_18 in std_logic
Port

Definition at line 159 of file CMX_top_Base.vhd.

P2_19 in std_logic
Port

Definition at line 160 of file CMX_top_Base.vhd.

P2_2 in std_logic
Port

Definition at line 143 of file CMX_top_Base.vhd.

P2_20 in std_logic
Port

Definition at line 161 of file CMX_top_Base.vhd.

P2_21 in std_logic
Port

Definition at line 162 of file CMX_top_Base.vhd.

P2_22 in std_logic
Port

Definition at line 163 of file CMX_top_Base.vhd.

P2_23 in std_logic
Port

Definition at line 164 of file CMX_top_Base.vhd.

P2_24 in std_logic
Port

Definition at line 165 of file CMX_top_Base.vhd.

P2_3 in std_logic
Port

Definition at line 144 of file CMX_top_Base.vhd.

P2_4 in std_logic
Port

Definition at line 145 of file CMX_top_Base.vhd.

P2_5 in std_logic
Port

Definition at line 146 of file CMX_top_Base.vhd.

P2_6 in std_logic
Port

Definition at line 147 of file CMX_top_Base.vhd.

P2_7 in std_logic
Port

Definition at line 148 of file CMX_top_Base.vhd.

P2_8 in std_logic
Port

Definition at line 149 of file CMX_top_Base.vhd.

P2_9 in std_logic
Port

Definition at line 150 of file CMX_top_Base.vhd.

P3_0 in std_logic
Port

Definition at line 166 of file CMX_top_Base.vhd.

P3_1 in std_logic
Port

Definition at line 167 of file CMX_top_Base.vhd.

P3_10 in std_logic
Port

Definition at line 176 of file CMX_top_Base.vhd.

P3_11 in std_logic
Port

Definition at line 177 of file CMX_top_Base.vhd.

P3_12 in std_logic
Port

Definition at line 178 of file CMX_top_Base.vhd.

P3_13 in std_logic
Port

Definition at line 179 of file CMX_top_Base.vhd.

P3_14 in std_logic
Port

Definition at line 180 of file CMX_top_Base.vhd.

P3_15 in std_logic
Port

Definition at line 181 of file CMX_top_Base.vhd.

P3_16 in std_logic
Port

Definition at line 182 of file CMX_top_Base.vhd.

P3_17 in std_logic
Port

Definition at line 183 of file CMX_top_Base.vhd.

P3_18 in std_logic
Port

Definition at line 184 of file CMX_top_Base.vhd.

P3_19 in std_logic
Port

Definition at line 185 of file CMX_top_Base.vhd.

P3_2 in std_logic
Port

Definition at line 168 of file CMX_top_Base.vhd.

P3_20 in std_logic
Port

Definition at line 186 of file CMX_top_Base.vhd.

P3_21 in std_logic
Port

Definition at line 187 of file CMX_top_Base.vhd.

P3_22 in std_logic
Port

Definition at line 188 of file CMX_top_Base.vhd.

P3_23 in std_logic
Port

Definition at line 189 of file CMX_top_Base.vhd.

P3_24 in std_logic
Port

Definition at line 190 of file CMX_top_Base.vhd.

P3_3 in std_logic
Port

Definition at line 169 of file CMX_top_Base.vhd.

P3_4 in std_logic
Port

Definition at line 170 of file CMX_top_Base.vhd.

P3_5 in std_logic
Port

Definition at line 171 of file CMX_top_Base.vhd.

P3_6 in std_logic
Port

Definition at line 172 of file CMX_top_Base.vhd.

P3_7 in std_logic
Port

Definition at line 173 of file CMX_top_Base.vhd.

P3_8 in std_logic
Port

Definition at line 174 of file CMX_top_Base.vhd.

P3_9 in std_logic
Port

Definition at line 175 of file CMX_top_Base.vhd.

P4_0 in std_logic
Port

Definition at line 191 of file CMX_top_Base.vhd.

P4_1 in std_logic
Port

Definition at line 192 of file CMX_top_Base.vhd.

P4_10 in std_logic
Port

Definition at line 201 of file CMX_top_Base.vhd.

P4_11 in std_logic
Port

Definition at line 202 of file CMX_top_Base.vhd.

P4_12 in std_logic
Port

Definition at line 203 of file CMX_top_Base.vhd.

P4_13 in std_logic
Port

Definition at line 204 of file CMX_top_Base.vhd.

P4_14 in std_logic
Port

Definition at line 205 of file CMX_top_Base.vhd.

P4_15 in std_logic
Port

Definition at line 206 of file CMX_top_Base.vhd.

P4_16 in std_logic
Port

Definition at line 207 of file CMX_top_Base.vhd.

P4_17 in std_logic
Port

Definition at line 208 of file CMX_top_Base.vhd.

P4_18 in std_logic
Port

Definition at line 209 of file CMX_top_Base.vhd.

P4_19 in std_logic
Port

Definition at line 210 of file CMX_top_Base.vhd.

P4_2 in std_logic
Port

Definition at line 193 of file CMX_top_Base.vhd.

P4_20 in std_logic
Port

Definition at line 211 of file CMX_top_Base.vhd.

P4_21 in std_logic
Port

Definition at line 212 of file CMX_top_Base.vhd.

P4_22 in std_logic
Port

Definition at line 213 of file CMX_top_Base.vhd.

P4_23 in std_logic
Port

Definition at line 214 of file CMX_top_Base.vhd.

P4_24 in std_logic
Port

Definition at line 215 of file CMX_top_Base.vhd.

P4_3 in std_logic
Port

Definition at line 194 of file CMX_top_Base.vhd.

P4_4 in std_logic
Port

Definition at line 195 of file CMX_top_Base.vhd.

P4_5 in std_logic
Port

Definition at line 196 of file CMX_top_Base.vhd.

P4_6 in std_logic
Port

Definition at line 197 of file CMX_top_Base.vhd.

P4_7 in std_logic
Port

Definition at line 198 of file CMX_top_Base.vhd.

P4_8 in std_logic
Port

Definition at line 199 of file CMX_top_Base.vhd.

P4_9 in std_logic
Port

Definition at line 200 of file CMX_top_Base.vhd.

P5_0 in std_logic
Port

Definition at line 216 of file CMX_top_Base.vhd.

P5_1 in std_logic
Port

Definition at line 217 of file CMX_top_Base.vhd.

P5_10 in std_logic
Port

Definition at line 226 of file CMX_top_Base.vhd.

P5_11 in std_logic
Port

Definition at line 227 of file CMX_top_Base.vhd.

P5_12 in std_logic
Port

Definition at line 228 of file CMX_top_Base.vhd.

P5_13 in std_logic
Port

Definition at line 229 of file CMX_top_Base.vhd.

P5_14 in std_logic
Port

Definition at line 230 of file CMX_top_Base.vhd.

P5_15 in std_logic
Port

Definition at line 231 of file CMX_top_Base.vhd.

P5_16 in std_logic
Port

Definition at line 232 of file CMX_top_Base.vhd.

P5_17 in std_logic
Port

Definition at line 233 of file CMX_top_Base.vhd.

P5_18 in std_logic
Port

Definition at line 234 of file CMX_top_Base.vhd.

P5_19 in std_logic
Port

Definition at line 235 of file CMX_top_Base.vhd.

P5_2 in std_logic
Port

Definition at line 218 of file CMX_top_Base.vhd.

P5_20 in std_logic
Port

Definition at line 236 of file CMX_top_Base.vhd.

P5_21 in std_logic
Port

Definition at line 237 of file CMX_top_Base.vhd.

P5_22 in std_logic
Port

Definition at line 238 of file CMX_top_Base.vhd.

P5_23 in std_logic
Port

Definition at line 239 of file CMX_top_Base.vhd.

P5_24 in std_logic
Port

Definition at line 240 of file CMX_top_Base.vhd.

P5_3 in std_logic
Port

Definition at line 219 of file CMX_top_Base.vhd.

P5_4 in std_logic
Port

Definition at line 220 of file CMX_top_Base.vhd.

P5_5 in std_logic
Port

Definition at line 221 of file CMX_top_Base.vhd.

P5_6 in std_logic
Port

Definition at line 222 of file CMX_top_Base.vhd.

P5_7 in std_logic
Port

Definition at line 223 of file CMX_top_Base.vhd.

P5_8 in std_logic
Port

Definition at line 224 of file CMX_top_Base.vhd.

P5_9 in std_logic
Port

Definition at line 225 of file CMX_top_Base.vhd.

P6_0 in std_logic
Port

Definition at line 241 of file CMX_top_Base.vhd.

P6_1 in std_logic
Port

Definition at line 242 of file CMX_top_Base.vhd.

P6_10 in std_logic
Port

Definition at line 251 of file CMX_top_Base.vhd.

P6_11 in std_logic
Port

Definition at line 252 of file CMX_top_Base.vhd.

P6_12 in std_logic
Port

Definition at line 253 of file CMX_top_Base.vhd.

P6_13 in std_logic
Port

Definition at line 254 of file CMX_top_Base.vhd.

P6_14 in std_logic
Port

Definition at line 255 of file CMX_top_Base.vhd.

P6_15 in std_logic
Port

Definition at line 256 of file CMX_top_Base.vhd.

P6_16 in std_logic
Port

Definition at line 257 of file CMX_top_Base.vhd.

P6_17 in std_logic
Port

Definition at line 258 of file CMX_top_Base.vhd.

P6_18 in std_logic
Port

Definition at line 259 of file CMX_top_Base.vhd.

P6_19 in std_logic
Port

Definition at line 260 of file CMX_top_Base.vhd.

P6_2 in std_logic
Port

Definition at line 243 of file CMX_top_Base.vhd.

P6_20 in std_logic
Port

Definition at line 261 of file CMX_top_Base.vhd.

P6_21 in std_logic
Port

Definition at line 262 of file CMX_top_Base.vhd.

P6_22 in std_logic
Port

Definition at line 263 of file CMX_top_Base.vhd.

P6_23 in std_logic
Port

Definition at line 264 of file CMX_top_Base.vhd.

P6_24 in std_logic
Port

Definition at line 265 of file CMX_top_Base.vhd.

P6_3 in std_logic
Port

Definition at line 244 of file CMX_top_Base.vhd.

P6_4 in std_logic
Port

Definition at line 245 of file CMX_top_Base.vhd.

P6_5 in std_logic
Port

Definition at line 246 of file CMX_top_Base.vhd.

P6_6 in std_logic
Port

Definition at line 247 of file CMX_top_Base.vhd.

P6_7 in std_logic
Port

Definition at line 248 of file CMX_top_Base.vhd.

P6_8 in std_logic
Port

Definition at line 249 of file CMX_top_Base.vhd.

P6_9 in std_logic
Port

Definition at line 250 of file CMX_top_Base.vhd.

P7_0 in std_logic
Port

Definition at line 266 of file CMX_top_Base.vhd.

P7_1 in std_logic
Port

Definition at line 267 of file CMX_top_Base.vhd.

P7_10 in std_logic
Port

Definition at line 276 of file CMX_top_Base.vhd.

P7_11 in std_logic
Port

Definition at line 277 of file CMX_top_Base.vhd.

P7_12 in std_logic
Port

Definition at line 278 of file CMX_top_Base.vhd.

P7_13 in std_logic
Port

Definition at line 279 of file CMX_top_Base.vhd.

P7_14 in std_logic
Port

Definition at line 280 of file CMX_top_Base.vhd.

P7_15 in std_logic
Port

Definition at line 281 of file CMX_top_Base.vhd.

P7_16 in std_logic
Port

Definition at line 282 of file CMX_top_Base.vhd.

P7_17 in std_logic
Port

Definition at line 283 of file CMX_top_Base.vhd.

P7_18 in std_logic
Port

Definition at line 284 of file CMX_top_Base.vhd.

P7_19 in std_logic
Port

Definition at line 285 of file CMX_top_Base.vhd.

P7_2 in std_logic
Port

Definition at line 268 of file CMX_top_Base.vhd.

P7_20 in std_logic
Port

Definition at line 286 of file CMX_top_Base.vhd.

P7_21 in std_logic
Port

Definition at line 287 of file CMX_top_Base.vhd.

P7_22 in std_logic
Port

Definition at line 288 of file CMX_top_Base.vhd.

P7_23 in std_logic
Port

Definition at line 289 of file CMX_top_Base.vhd.

P7_24 in std_logic
Port

Definition at line 290 of file CMX_top_Base.vhd.

P7_3 in std_logic
Port

Definition at line 269 of file CMX_top_Base.vhd.

P7_4 in std_logic
Port

Definition at line 270 of file CMX_top_Base.vhd.

P7_5 in std_logic
Port

Definition at line 271 of file CMX_top_Base.vhd.

P7_6 in std_logic
Port

Definition at line 272 of file CMX_top_Base.vhd.

P7_7 in std_logic
Port

Definition at line 273 of file CMX_top_Base.vhd.

P7_8 in std_logic
Port

Definition at line 274 of file CMX_top_Base.vhd.

P7_9 in std_logic
Port

Definition at line 275 of file CMX_top_Base.vhd.

P8_0 in std_logic
Port

Definition at line 291 of file CMX_top_Base.vhd.

P8_1 in std_logic
Port

Definition at line 292 of file CMX_top_Base.vhd.

P8_10 in std_logic
Port

Definition at line 301 of file CMX_top_Base.vhd.

P8_11 in std_logic
Port

Definition at line 302 of file CMX_top_Base.vhd.

P8_12 in std_logic
Port

Definition at line 303 of file CMX_top_Base.vhd.

P8_13 in std_logic
Port

Definition at line 304 of file CMX_top_Base.vhd.

P8_14 in std_logic
Port

Definition at line 305 of file CMX_top_Base.vhd.

P8_15 in std_logic
Port

Definition at line 306 of file CMX_top_Base.vhd.

P8_16 in std_logic
Port

Definition at line 307 of file CMX_top_Base.vhd.

P8_17 in std_logic
Port

Definition at line 308 of file CMX_top_Base.vhd.

P8_18 in std_logic
Port

Definition at line 309 of file CMX_top_Base.vhd.

P8_19 in std_logic
Port

Definition at line 310 of file CMX_top_Base.vhd.

P8_2 in std_logic
Port

Definition at line 293 of file CMX_top_Base.vhd.

P8_20 in std_logic
Port

Definition at line 311 of file CMX_top_Base.vhd.

P8_21 in std_logic
Port

Definition at line 312 of file CMX_top_Base.vhd.

P8_22 in std_logic
Port

Definition at line 313 of file CMX_top_Base.vhd.

P8_23 in std_logic
Port

Definition at line 314 of file CMX_top_Base.vhd.

P8_24 in std_logic
Port

Definition at line 315 of file CMX_top_Base.vhd.

P8_3 in std_logic
Port

Definition at line 294 of file CMX_top_Base.vhd.

P8_4 in std_logic
Port

Definition at line 295 of file CMX_top_Base.vhd.

P8_5 in std_logic
Port

Definition at line 296 of file CMX_top_Base.vhd.

P8_6 in std_logic
Port

Definition at line 297 of file CMX_top_Base.vhd.

P8_7 in std_logic
Port

Definition at line 298 of file CMX_top_Base.vhd.

P8_8 in std_logic
Port

Definition at line 299 of file CMX_top_Base.vhd.

P8_9 in std_logic
Port

Definition at line 300 of file CMX_top_Base.vhd.

P9_0 in std_logic
Port

Definition at line 316 of file CMX_top_Base.vhd.

P9_1 in std_logic
Port

Definition at line 317 of file CMX_top_Base.vhd.

P9_10 in std_logic
Port

Definition at line 326 of file CMX_top_Base.vhd.

P9_11 in std_logic
Port

Definition at line 327 of file CMX_top_Base.vhd.

P9_12 in std_logic
Port

Definition at line 328 of file CMX_top_Base.vhd.

P9_13 in std_logic
Port

Definition at line 329 of file CMX_top_Base.vhd.

P9_14 in std_logic
Port

Definition at line 330 of file CMX_top_Base.vhd.

P9_15 in std_logic
Port

Definition at line 331 of file CMX_top_Base.vhd.

P9_16 in std_logic
Port

Definition at line 332 of file CMX_top_Base.vhd.

P9_17 in std_logic
Port

Definition at line 333 of file CMX_top_Base.vhd.

P9_18 in std_logic
Port

Definition at line 334 of file CMX_top_Base.vhd.

P9_19 in std_logic
Port

Definition at line 335 of file CMX_top_Base.vhd.

P9_2 in std_logic
Port

Definition at line 318 of file CMX_top_Base.vhd.

P9_20 in std_logic
Port

Definition at line 336 of file CMX_top_Base.vhd.

P9_21 in std_logic
Port

Definition at line 337 of file CMX_top_Base.vhd.

P9_22 in std_logic
Port

Definition at line 338 of file CMX_top_Base.vhd.

P9_23 in std_logic
Port

Definition at line 339 of file CMX_top_Base.vhd.

P9_24 in std_logic
Port

Definition at line 340 of file CMX_top_Base.vhd.

P9_3 in std_logic
Port

Definition at line 319 of file CMX_top_Base.vhd.

P9_4 in std_logic
Port

Definition at line 320 of file CMX_top_Base.vhd.

P9_5 in std_logic
Port

Definition at line 321 of file CMX_top_Base.vhd.

P9_6 in std_logic
Port

Definition at line 322 of file CMX_top_Base.vhd.

P9_7 in std_logic
Port

Definition at line 323 of file CMX_top_Base.vhd.

P9_8 in std_logic
Port

Definition at line 324 of file CMX_top_Base.vhd.

P9_9 in std_logic
Port

Definition at line 325 of file CMX_top_Base.vhd.

RXN_IN in std_logic_vector ( ( num_GTX_per_group * num_GTX_groups ) - 1 downto 0 )
Port

Definition at line 762 of file CMX_top_Base.vhd.

RXP_IN in std_logic_vector ( ( num_GTX_per_group * num_GTX_groups ) - 1 downto 0 )
Port

Definition at line 763 of file CMX_top_Base.vhd.

UNISIM
Library

Definition at line 12 of file CMX_top_Base.vhd.

Definition at line 13 of file CMX_top_Base.vhd.

work
Library

Definition at line 15 of file CMX_top_Base.vhd.

Definition at line 19 of file CMX_top_Base.vhd.

Definition at line 18 of file CMX_top_Base.vhd.

Definition at line 17 of file CMX_top_Base.vhd.

Definition at line 16 of file CMX_top_Base.vhd.


The documentation for this class was generated from the following file: