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CMX_top_Base.vhd
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1 ----------------------------------------------------------------------------------
7 ----------------------------------------------------------------------------------
8 library IEEE;
9 use IEEE.STD_LOGIC_1164.ALL;
10 use IEEE.NUMERIC_STD.ALL;
11 
12 library UNISIM;
13 use UNISIM.VComponents.all;
14 
15 library work;
16 use work.CMXpackage.all;
17 use work.CMX_VME_defs.all;
18 use work.CMX_local_package.all;
19 use work.CMX_flavor_package.all;
20 
21 
22 
23 entity CMX_top_Base is
24  port (
25 
26  ----------------------------------------------------------------------------
27  -- VME-- backplane (65 signals)
28  ----------------------------------------------------------------------------
29  --GEOADDR0: in std_logic; -- GeoAddr0
30  OCB_GEO_ADRS_0: in std_logic;
31  --VMEADDR: in std_logic_vector(23 downto 1); -- Address bus
32  OCB_A01: in std_logic;
33  OCB_A02: in std_logic;
34  OCB_A03: in std_logic;
35  OCB_A04: in std_logic;
36  OCB_A05: in std_logic;
37  OCB_A06: in std_logic;
38  OCB_A07: in std_logic;
39  OCB_A08: in std_logic;
40  OCB_A09: in std_logic;
41  OCB_A10: in std_logic;
42  OCB_A11: in std_logic;
43  OCB_A12: in std_logic;
44  OCB_A13: in std_logic;
45  OCB_A14: in std_logic;
46  OCB_A15: in std_logic;
47  OCB_A16: in std_logic;
48  OCB_A17: in std_logic;
49  OCB_A18: in std_logic;
50  OCB_A19: in std_logic;
51  OCB_A20: in std_logic;
52  OCB_A21: in std_logic;
53  OCB_A22: in std_logic;
54  OCB_A23: in std_logic;
55  --VMEDS_L: in std_logic; -- DS strobe VMEDS_L
56  OCB_DS_B: in std_logic;
57  --VMEWR_L: in std_logic; -- VME Write VMEWR_L
58  OCB_WRITE_B: in std_logic;
59  --VMERST_L: in std_logic; -- System reset VMERST_L
60  OCB_SYS_RESET_B: in std_logic;
61  --VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA
62  OCB_D: inout std_logic_vector(15 downto 0);
63  ----------------------------------------------------------------------------
64  --system monitor
65  BF_SYSMON_01_P : in STD_LOGIC; -- Auxiliary Channel 1
66  BF_SYSMON_01_N : in STD_LOGIC;
67  BF_SYSMON_03_P : in STD_LOGIC; -- Auxiliary Channel 3
68  BF_SYSMON_03_N : in STD_LOGIC;
69  BF_SYSMON_04_P : in STD_LOGIC; -- Auxiliary Channel 4
70  BF_SYSMON_04_N : in STD_LOGIC;
71  BF_SYSMON_07_P : in STD_LOGIC; -- Auxiliary Channel 7
72  BF_SYSMON_07_N : in STD_LOGIC;
73  BF_SYSMON_08_P : in STD_LOGIC; -- Auxiliary Channel 8
74  BF_SYSMON_08_N : in STD_LOGIC;
75  BF_SYSMON_09_P : in STD_LOGIC; -- Auxiliary Channel 9
76  BF_SYSMON_09_N : in STD_LOGIC;
77  BF_SYSMON_10_P : in STD_LOGIC; -- Auxiliary Channel 10
78  BF_SYSMON_10_N : in STD_LOGIC;
79  BF_SYSMON_11_P : in STD_LOGIC; -- Auxiliary Channel 11
80  BF_SYSMON_11_N : in STD_LOGIC;
81  BF_SYSMON_12_P : in STD_LOGIC; -- Auxiliary Channel 12
82  BF_SYSMON_12_N : in STD_LOGIC;
83  BF_SYSMON_13_P : in STD_LOGIC; -- Auxiliary Channel 13
84  BF_SYSMON_13_N : in STD_LOGIC;
85  BF_SYSMON_14_P : in STD_LOGIC; -- Auxiliary Channel 14
86  BF_SYSMON_14_N : in STD_LOGIC;
87  BF_SYSMON_15_P : in STD_LOGIC; -- Auxiliary Channel 15
88  BF_SYSMON_15_N : in STD_LOGIC;
89 
90  --backplane
91  P0_0 : in std_logic;
92  P0_1 : in std_logic;
93  P0_2 : in std_logic;
94  P0_3 : in std_logic;
95  P0_4 : in std_logic;
96  P0_5 : in std_logic;
97  P0_6 : in std_logic;
98  P0_7 : in std_logic;
99  P0_8 : in std_logic;
100  P0_9 : in std_logic;
101  P0_10 : in std_logic;
102  P0_11 : in std_logic;
103  P0_12 : in std_logic;
104  P0_13 : in std_logic;
105  P0_14 : in std_logic;
106  P0_15 : in std_logic;
107  P0_16 : in std_logic;
108  P0_17 : in std_logic;
109  P0_18 : in std_logic;
110  P0_19 : in std_logic;
111  P0_20 : in std_logic;
112  P0_21 : in std_logic;
113  P0_22 : in std_logic;
114  P0_23 : in std_logic;
115  P0_24 : in std_logic;
116  P1_0 : in std_logic;
117  P1_1 : in std_logic;
118  P1_2 : in std_logic;
119  P1_3 : in std_logic;
120  P1_4 : in std_logic;
121  P1_5 : in std_logic;
122  P1_6 : in std_logic;
123  P1_7 : in std_logic;
124  P1_8 : in std_logic;
125  P1_9 : in std_logic;
126  P1_10 : in std_logic;
127  P1_11 : in std_logic;
128  P1_12 : in std_logic;
129  P1_13 : in std_logic;
130  P1_14 : in std_logic;
131  P1_15 : in std_logic;
132  P1_16 : in std_logic;
133  P1_17 : in std_logic;
134  P1_18 : in std_logic;
135  P1_19 : in std_logic;
136  P1_20 : in std_logic;
137  P1_21 : in std_logic;
138  P1_22 : in std_logic;
139  P1_23 : in std_logic;
140  P1_24 : in std_logic;
141  P2_0 : in std_logic;
142  P2_1 : in std_logic;
143  P2_2 : in std_logic;
144  P2_3 : in std_logic;
145  P2_4 : in std_logic;
146  P2_5 : in std_logic;
147  P2_6 : in std_logic;
148  P2_7 : in std_logic;
149  P2_8 : in std_logic;
150  P2_9 : in std_logic;
151  P2_10 : in std_logic;
152  P2_11 : in std_logic;
153  P2_12 : in std_logic;
154  P2_13 : in std_logic;
155  P2_14 : in std_logic;
156  P2_15 : in std_logic;
157  P2_16 : in std_logic;
158  P2_17 : in std_logic;
159  P2_18 : in std_logic;
160  P2_19 : in std_logic;
161  P2_20 : in std_logic;
162  P2_21 : in std_logic;
163  P2_22 : in std_logic;
164  P2_23 : in std_logic;
165  P2_24 : in std_logic;
166  P3_0 : in std_logic;
167  P3_1 : in std_logic;
168  P3_2 : in std_logic;
169  P3_3 : in std_logic;
170  P3_4 : in std_logic;
171  P3_5 : in std_logic;
172  P3_6 : in std_logic;
173  P3_7 : in std_logic;
174  P3_8 : in std_logic;
175  P3_9 : in std_logic;
176  P3_10 : in std_logic;
177  P3_11 : in std_logic;
178  P3_12 : in std_logic;
179  P3_13 : in std_logic;
180  P3_14 : in std_logic;
181  P3_15 : in std_logic;
182  P3_16 : in std_logic;
183  P3_17 : in std_logic;
184  P3_18 : in std_logic;
185  P3_19 : in std_logic;
186  P3_20 : in std_logic;
187  P3_21 : in std_logic;
188  P3_22 : in std_logic;
189  P3_23 : in std_logic;
190  P3_24 : in std_logic;
191  P4_0 : in std_logic;
192  P4_1 : in std_logic;
193  P4_2 : in std_logic;
194  P4_3 : in std_logic;
195  P4_4 : in std_logic;
196  P4_5 : in std_logic;
197  P4_6 : in std_logic;
198  P4_7 : in std_logic;
199  P4_8 : in std_logic;
200  P4_9 : in std_logic;
201  P4_10 : in std_logic;
202  P4_11 : in std_logic;
203  P4_12 : in std_logic;
204  P4_13 : in std_logic;
205  P4_14 : in std_logic;
206  P4_15 : in std_logic;
207  P4_16 : in std_logic;
208  P4_17 : in std_logic;
209  P4_18 : in std_logic;
210  P4_19 : in std_logic;
211  P4_20 : in std_logic;
212  P4_21 : in std_logic;
213  P4_22 : in std_logic;
214  P4_23 : in std_logic;
215  P4_24 : in std_logic;
216  P5_0 : in std_logic;
217  P5_1 : in std_logic;
218  P5_2 : in std_logic;
219  P5_3 : in std_logic;
220  P5_4 : in std_logic;
221  P5_5 : in std_logic;
222  P5_6 : in std_logic;
223  P5_7 : in std_logic;
224  P5_8 : in std_logic;
225  P5_9 : in std_logic;
226  P5_10 : in std_logic;
227  P5_11 : in std_logic;
228  P5_12 : in std_logic;
229  P5_13 : in std_logic;
230  P5_14 : in std_logic;
231  P5_15 : in std_logic;
232  P5_16 : in std_logic;
233  P5_17 : in std_logic;
234  P5_18 : in std_logic;
235  P5_19 : in std_logic;
236  P5_20 : in std_logic;
237  P5_21 : in std_logic;
238  P5_22 : in std_logic;
239  P5_23 : in std_logic;
240  P5_24 : in std_logic;
241  P6_0 : in std_logic;
242  P6_1 : in std_logic;
243  P6_2 : in std_logic;
244  P6_3 : in std_logic;
245  P6_4 : in std_logic;
246  P6_5 : in std_logic;
247  P6_6 : in std_logic;
248  P6_7 : in std_logic;
249  P6_8 : in std_logic;
250  P6_9 : in std_logic;
251  P6_10 : in std_logic;
252  P6_11 : in std_logic;
253  P6_12 : in std_logic;
254  P6_13 : in std_logic;
255  P6_14 : in std_logic;
256  P6_15 : in std_logic;
257  P6_16 : in std_logic;
258  P6_17 : in std_logic;
259  P6_18 : in std_logic;
260  P6_19 : in std_logic;
261  P6_20 : in std_logic;
262  P6_21 : in std_logic;
263  P6_22 : in std_logic;
264  P6_23 : in std_logic;
265  P6_24 : in std_logic;
266  P7_0 : in std_logic;
267  P7_1 : in std_logic;
268  P7_2 : in std_logic;
269  P7_3 : in std_logic;
270  P7_4 : in std_logic;
271  P7_5 : in std_logic;
272  P7_6 : in std_logic;
273  P7_7 : in std_logic;
274  P7_8 : in std_logic;
275  P7_9 : in std_logic;
276  P7_10 : in std_logic;
277  P7_11 : in std_logic;
278  P7_12 : in std_logic;
279  P7_13 : in std_logic;
280  P7_14 : in std_logic;
281  P7_15 : in std_logic;
282  P7_16 : in std_logic;
283  P7_17 : in std_logic;
284  P7_18 : in std_logic;
285  P7_19 : in std_logic;
286  P7_20 : in std_logic;
287  P7_21 : in std_logic;
288  P7_22 : in std_logic;
289  P7_23 : in std_logic;
290  P7_24 : in std_logic;
291  P8_0 : in std_logic;
292  P8_1 : in std_logic;
293  P8_2 : in std_logic;
294  P8_3 : in std_logic;
295  P8_4 : in std_logic;
296  P8_5 : in std_logic;
297  P8_6 : in std_logic;
298  P8_7 : in std_logic;
299  P8_8 : in std_logic;
300  P8_9 : in std_logic;
301  P8_10 : in std_logic;
302  P8_11 : in std_logic;
303  P8_12 : in std_logic;
304  P8_13 : in std_logic;
305  P8_14 : in std_logic;
306  P8_15 : in std_logic;
307  P8_16 : in std_logic;
308  P8_17 : in std_logic;
309  P8_18 : in std_logic;
310  P8_19 : in std_logic;
311  P8_20 : in std_logic;
312  P8_21 : in std_logic;
313  P8_22 : in std_logic;
314  P8_23 : in std_logic;
315  P8_24 : in std_logic;
316  P9_0 : in std_logic;
317  P9_1 : in std_logic;
318  P9_2 : in std_logic;
319  P9_3 : in std_logic;
320  P9_4 : in std_logic;
321  P9_5 : in std_logic;
322  P9_6 : in std_logic;
323  P9_7 : in std_logic;
324  P9_8 : in std_logic;
325  P9_9 : in std_logic;
326  P9_10 : in std_logic;
327  P9_11 : in std_logic;
328  P9_12 : in std_logic;
329  P9_13 : in std_logic;
330  P9_14 : in std_logic;
331  P9_15 : in std_logic;
332  P9_16 : in std_logic;
333  P9_17 : in std_logic;
334  P9_18 : in std_logic;
335  P9_19 : in std_logic;
336  P9_20 : in std_logic;
337  P9_21 : in std_logic;
338  P9_22 : in std_logic;
339  P9_23 : in std_logic;
340  P9_24 : in std_logic;
341  P10_0 : in std_logic;
342  P10_1 : in std_logic;
343  P10_2 : in std_logic;
344  P10_3 : in std_logic;
345  P10_4 : in std_logic;
346  P10_5 : in std_logic;
347  P10_6 : in std_logic;
348  P10_7 : in std_logic;
349  P10_8 : in std_logic;
350  P10_9 : in std_logic;
351  P10_10 : in std_logic;
352  P10_11 : in std_logic;
353  P10_12 : in std_logic;
354  P10_13 : in std_logic;
355  P10_14 : in std_logic;
356  P10_15 : in std_logic;
357  P10_16 : in std_logic;
358  P10_17 : in std_logic;
359  P10_18 : in std_logic;
360  P10_19 : in std_logic;
361  P10_20 : in std_logic;
362  P10_21 : in std_logic;
363  P10_22 : in std_logic;
364  P10_23 : in std_logic;
365  P10_24 : in std_logic;
366  P11_0 : in std_logic;
367  P11_1 : in std_logic;
368  P11_2 : in std_logic;
369  P11_3 : in std_logic;
370  P11_4 : in std_logic;
371  P11_5 : in std_logic;
372  P11_6 : in std_logic;
373  P11_7 : in std_logic;
374  P11_8 : in std_logic;
375  P11_9 : in std_logic;
376  P11_10 : in std_logic;
377  P11_11 : in std_logic;
378  P11_12 : in std_logic;
379  P11_13 : in std_logic;
380  P11_14 : in std_logic;
381  P11_15 : in std_logic;
382  P11_16 : in std_logic;
383  P11_17 : in std_logic;
384  P11_18 : in std_logic;
385  P11_19 : in std_logic;
386  P11_20 : in std_logic;
387  P11_21 : in std_logic;
388  P11_22 : in std_logic;
389  P11_23 : in std_logic;
390  P11_24 : in std_logic;
391  P12_0 : in std_logic;
392  P12_1 : in std_logic;
393  P12_2 : in std_logic;
394  P12_3 : in std_logic;
395  P12_4 : in std_logic;
396  P12_5 : in std_logic;
397  P12_6 : in std_logic;
398  P12_7 : in std_logic;
399  P12_8 : in std_logic;
400  P12_9 : in std_logic;
401  P12_10 : in std_logic;
402  P12_11 : in std_logic;
403  P12_12 : in std_logic;
404  P12_13 : in std_logic;
405  P12_14 : in std_logic;
406  P12_15 : in std_logic;
407  P12_16 : in std_logic;
408  P12_17 : in std_logic;
409  P12_18 : in std_logic;
410  P12_19 : in std_logic;
411  P12_20 : in std_logic;
412  P12_21 : in std_logic;
413  P12_22 : in std_logic;
414  P12_23 : in std_logic;
415  P12_24 : in std_logic;
416  P13_0 : in std_logic;
417  P13_1 : in std_logic;
418  P13_2 : in std_logic;
419  P13_3 : in std_logic;
420  P13_4 : in std_logic;
421  P13_5 : in std_logic;
422  P13_6 : in std_logic;
423  P13_7 : in std_logic;
424  P13_8 : in std_logic;
425  P13_9 : in std_logic;
426  P13_10 : in std_logic;
427  P13_11 : in std_logic;
428  P13_12 : in std_logic;
429  P13_13 : in std_logic;
430  P13_14 : in std_logic;
431  P13_15 : in std_logic;
432  P13_16 : in std_logic;
433  P13_17 : in std_logic;
434  P13_18 : in std_logic;
435  P13_19 : in std_logic;
436  P13_20 : in std_logic;
437  P13_21 : in std_logic;
438  P13_22 : in std_logic;
439  P13_23 : in std_logic;
440  P13_24 : in std_logic;
441  P14_0 : in std_logic;
442  P14_1 : in std_logic;
443  P14_2 : in std_logic;
444  P14_3 : in std_logic;
445  P14_4 : in std_logic;
446  P14_5 : in std_logic;
447  P14_6 : in std_logic;
448  P14_7 : in std_logic;
449  P14_8 : in std_logic;
450  P14_9 : in std_logic;
451  P14_10 : in std_logic;
452  P14_11 : in std_logic;
453  P14_12 : in std_logic;
454  P14_13 : in std_logic;
455  P14_14 : in std_logic;
456  P14_15 : in std_logic;
457  P14_16 : in std_logic;
458  P14_17 : in std_logic;
459  P14_18 : in std_logic;
460  P14_19 : in std_logic;
461  P14_20 : in std_logic;
462  P14_21 : in std_logic;
463  P14_22 : in std_logic;
464  P14_23 : in std_logic;
465  P14_24 : in std_logic;
466  P15_0 : in std_logic;
467  P15_1 : in std_logic;
468  P15_2 : in std_logic;
469  P15_3 : in std_logic;
470  P15_4 : in std_logic;
471  P15_5 : in std_logic;
472  P15_6 : in std_logic;
473  P15_7 : in std_logic;
474  P15_8 : in std_logic;
475  P15_9 : in std_logic;
476  P15_10 : in std_logic;
477  P15_11 : in std_logic;
478  P15_12 : in std_logic;
479  P15_13 : in std_logic;
480  P15_14 : in std_logic;
481  P15_15 : in std_logic;
482  P15_16 : in std_logic;
483  P15_17 : in std_logic;
484  P15_18 : in std_logic;
485  P15_19 : in std_logic;
486  P15_20 : in std_logic;
487  P15_21 : in std_logic;
488  P15_22 : in std_logic;
489  P15_23 : in std_logic;
490  P15_24 : in std_logic;
491 
492 
493  --CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
494  --CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
495 
496  CLK_40MHz08_DSKW_1_BF_LOGIC_DIR : in std_logic;
497  CLK_40MHz08_DSKW_1_BF_LOGIC_CMP : in std_logic;
498 
499  CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
500  CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
501 
502 
503  --CLK_320MHz64_LHC_BF_LOGIC_DIR : in std_logic;
504  --CLK_320MHz64_LHC_BF_LOGIC_CMP : in std_logic;
505 
506  BF_DEBUG_0 : out std_logic;
507  BF_DEBUG_1 : out std_logic;
508  BF_DEBUG_2 : out std_logic;
509  BF_DEBUG_3 : out std_logic;
510  BF_DEBUG_4 : out std_logic;
511  BF_DEBUG_5 : out std_logic;
512  BF_DEBUG_6 : out std_logic;
513  BF_DEBUG_7 : out std_logic;
514  BF_DEBUG_8 : out std_logic;
515  BF_DEBUG_9 : out std_logic;
516 
517 
518  BF_REQ_CTP_1_INPUT : out std_logic;
519  BF_REQ_CTP_2_INPUT : out std_logic;
520  BF_REQ_CABLE_1_INPUT: out std_logic;
521  BF_REQ_CABLE_2_INPUT: out std_logic;
522  BF_REQ_CABLE_3_INPUT: out std_logic;
523  BF_LED_REQ_0 : out std_logic;
524  BF_LED_REQ_1 : out std_logic;
525  BF_LED_REQ_2 : out std_logic;
526  BF_LED_REQ_3 : out std_logic;
527  BF_LED_REQ_4 : out std_logic;
528  BF_TO_FROM_BSPT_0 : in std_logic;
529  BF_TO_FROM_BSPT_1 : in std_logic;
530  BF_TO_FROM_BSPT_2 : out std_logic;
531  BF_TO_FROM_BSPT_3 : out std_logic;
532  BF_TO_FROM_BSPT_4 : out std_logic;
533  BF_TO_FROM_BSPT_5 : out std_logic;
534  BF_TO_FROM_BSPT_6 : out std_logic;
535  BF_TO_FROM_BSPT_7 : out std_logic;
536 
537 
538  BF_DOUT_CTP_00 : out std_logic;
539  BF_DOUT_CTP_01 : out std_logic;
540  BF_DOUT_CTP_02 : out std_logic;
541  BF_DOUT_CTP_03 : out std_logic;
542  BF_DOUT_CTP_04 : out std_logic;
543  BF_DOUT_CTP_05 : out std_logic;
544  BF_DOUT_CTP_06 : out std_logic;
545  BF_DOUT_CTP_07 : out std_logic;
546  BF_DOUT_CTP_08 : out std_logic;
547  BF_DOUT_CTP_09 : out std_logic;
548  BF_DOUT_CTP_10 : out std_logic;
549  BF_DOUT_CTP_11 : out std_logic;
550  BF_DOUT_CTP_12 : out std_logic;
551  BF_DOUT_CTP_13 : out std_logic;
552  BF_DOUT_CTP_14 : out std_logic;
553  BF_DOUT_CTP_15 : out std_logic;
554  BF_DOUT_CTP_16 : out std_logic;
555  BF_DOUT_CTP_17 : out std_logic;
556  BF_DOUT_CTP_18 : out std_logic;
557  BF_DOUT_CTP_19 : out std_logic;
558  BF_DOUT_CTP_20 : out std_logic;
559  BF_DOUT_CTP_21 : out std_logic;
560  BF_DOUT_CTP_22 : out std_logic;
561  BF_DOUT_CTP_23 : out std_logic;
562  BF_DOUT_CTP_24 : out std_logic;
563  BF_DOUT_CTP_25 : out std_logic;
564  BF_DOUT_CTP_26 : out std_logic;
565  BF_DOUT_CTP_27 : out std_logic;
566  BF_DOUT_CTP_28 : out std_logic;
567  BF_DOUT_CTP_29 : out std_logic;
568  BF_DOUT_CTP_30 : out std_logic;
569  BF_DOUT_CTP_31 : out std_logic;
570  BF_DOUT_CTP_64 : out std_logic;
571 
572  BF_DOUT_CTP_32 : out std_logic;
573  BF_DOUT_CTP_33 : out std_logic;
574  BF_DOUT_CTP_34 : out std_logic;
575  BF_DOUT_CTP_35 : out std_logic;
576  BF_DOUT_CTP_36 : out std_logic;
577  BF_DOUT_CTP_37 : out std_logic;
578  BF_DOUT_CTP_38 : out std_logic;
579  BF_DOUT_CTP_39 : out std_logic;
580  BF_DOUT_CTP_40 : out std_logic;
581  BF_DOUT_CTP_41 : out std_logic;
582  BF_DOUT_CTP_42 : out std_logic;
583  BF_DOUT_CTP_43 : out std_logic;
584  BF_DOUT_CTP_44 : out std_logic;
585  BF_DOUT_CTP_45 : out std_logic;
586  BF_DOUT_CTP_46 : out std_logic;
587  BF_DOUT_CTP_47 : out std_logic;
588  BF_DOUT_CTP_48 : out std_logic;
589  BF_DOUT_CTP_49 : out std_logic;
590  BF_DOUT_CTP_50 : out std_logic;
591  BF_DOUT_CTP_51 : out std_logic;
592  BF_DOUT_CTP_52 : out std_logic;
593  BF_DOUT_CTP_53 : out std_logic;
594  BF_DOUT_CTP_54 : out std_logic;
595  BF_DOUT_CTP_55 : out std_logic;
596  BF_DOUT_CTP_56 : out std_logic;
597  BF_DOUT_CTP_57 : out std_logic;
598  BF_DOUT_CTP_58 : out std_logic;
599  BF_DOUT_CTP_59 : out std_logic;
600  BF_DOUT_CTP_60 : out std_logic;
601  BF_DOUT_CTP_61 : out std_logic;
602  BF_DOUT_CTP_62 : out std_logic;
603  BF_DOUT_CTP_63 : out std_logic;
604  BF_DOUT_CTP_65 : out std_logic;
605 
606  D_CBL_00_B : out std_logic;
607  D_CBL_01_B : out std_logic;
608  D_CBL_02_B : out std_logic;
609  D_CBL_03_B : out std_logic;
610  D_CBL_04_B : out std_logic;
611  D_CBL_05_B : out std_logic;
612  D_CBL_06_B : out std_logic;
613  D_CBL_07_B : out std_logic;
614  D_CBL_08_B : out std_logic;
615  D_CBL_09_B : out std_logic;
616  D_CBL_10_B : out std_logic;
617  D_CBL_11_B : out std_logic;
618  D_CBL_12_B : out std_logic;
619  D_CBL_13_B : out std_logic;
620  D_CBL_14_B : out std_logic;
621  D_CBL_15_B : out std_logic;
622  D_CBL_16_B : out std_logic;
623  D_CBL_17_B : out std_logic;
624  D_CBL_18_B : out std_logic;
625  D_CBL_19_B : out std_logic;
626  D_CBL_20_B : out std_logic;
627  D_CBL_21_B : out std_logic;
628  D_CBL_22_B : out std_logic;
629  D_CBL_23_B : out std_logic;
630  D_CBL_24_B : out std_logic;
631  D_CBL_25_B : out std_logic;
632  D_CBL_26_B : out std_logic;
633  D_CBL_81_B : out std_logic;
634 
635  D_CBL_27_B : out std_logic;
636  D_CBL_28_B : out std_logic;
637  D_CBL_29_B : out std_logic;
638  D_CBL_30_B : out std_logic;
639  D_CBL_31_B : out std_logic;
640  D_CBL_32_B : out std_logic;
641  D_CBL_33_B : out std_logic;
642  D_CBL_34_B : out std_logic;
643  D_CBL_35_B : out std_logic;
644  D_CBL_36_B : out std_logic;
645  D_CBL_37_B : out std_logic;
646  D_CBL_38_B : out std_logic;
647  D_CBL_39_B : out std_logic;
648  D_CBL_40_B : out std_logic;
649  D_CBL_41_B : out std_logic;
650  D_CBL_42_B : out std_logic;
651  D_CBL_43_B : out std_logic;
652  D_CBL_44_B : out std_logic;
653  D_CBL_45_B : out std_logic;
654  D_CBL_46_B : out std_logic;
655  D_CBL_47_B : out std_logic;
656  D_CBL_48_B : out std_logic;
657  D_CBL_49_B : out std_logic;
658  D_CBL_50_B : out std_logic;
659  D_CBL_51_B : out std_logic;
660  D_CBL_52_B : out std_logic;
661  D_CBL_53_B : out std_logic;
662  D_CBL_82_B : out std_logic;
663 
664  D_CBL_54_B : out std_logic;
665  D_CBL_55_B : out std_logic;
666  D_CBL_56_B : out std_logic;
667  D_CBL_57_B : out std_logic;
668  D_CBL_58_B : out std_logic;
669  D_CBL_59_B : out std_logic;
670  D_CBL_60_B : out std_logic;
671  D_CBL_61_B : out std_logic;
672  D_CBL_62_B : out std_logic;
673  D_CBL_63_B : out std_logic;
674  D_CBL_64_B : out std_logic;
675  D_CBL_65_B : out std_logic;
676  D_CBL_66_B : out std_logic;
677  D_CBL_67_B : out std_logic;
678  D_CBL_68_B : out std_logic;
679  D_CBL_69_B : out std_logic;
680  D_CBL_70_B : out std_logic;
681  D_CBL_71_B : out std_logic;
682  D_CBL_72_B : out std_logic;
683  D_CBL_73_B : out std_logic;
684  D_CBL_74_B : out std_logic;
685  D_CBL_75_B : out std_logic;
686  D_CBL_76_B : out std_logic;
687  D_CBL_77_B : out std_logic;
688  D_CBL_78_B : out std_logic;
689  D_CBL_79_B : out std_logic;
690  D_CBL_80_B : out std_logic;
691  D_CBL_83_B : out std_logic;
692 
693  BF_TO_TP_DAQ_SLINK_RETURN_DIR : in std_logic;
694  BF_TO_TP_DAQ_SLINK_RETURN_CMP : in std_logic;
695  BF_TO_TP_ROI_SLINK_RETURN_DIR : in std_logic;
696  BF_TO_TP_ROI_SLINK_RETURN_CMP : in std_logic;
697 
698  BUF_TTC_L1_ACCEPT : in std_logic;
699  BUF_TTC_BNCH_CNT_RES : in std_logic;
700 
701  -- sfp
702  CLK_120MHz000_XTAL_1_BF_TRNCV_DIR: in std_logic;
703  CLK_120MHz000_XTAL_1_BF_TRNCV_CMP: in std_logic;
704  BF_DAQ_DATA_OUT_DIR : out std_logic;
705  BF_DAQ_DATA_OUT_CMP : out std_logic;
706  BF_ROI_DATA_OUT_DIR : out std_logic;
707  BF_ROI_DATA_OUT_CMP : out std_logic;
708 
709  MP1_F01_QUAD_110_TRN_0_DIR : out std_logic;
710  MP1_F01_QUAD_110_TRN_0_CMP : out std_logic;
711  MP1_F03_QUAD_110_TRN_1_DIR : out std_logic;
712  MP1_F03_QUAD_110_TRN_1_CMP : out std_logic;
713  MP1_F07_QUAD_110_TRN_2_DIR : out std_logic;
714  MP1_F07_QUAD_110_TRN_2_CMP : out std_logic;
715  MP1_F05_QUAD_110_TRN_3_DIR : out std_logic;
716  MP1_F05_QUAD_110_TRN_3_CMP : out std_logic;
717  MP1_F09_QUAD_111_TRN_0_DIR : out std_logic;
718  MP1_F09_QUAD_111_TRN_0_CMP : out std_logic;
719  MP1_F11_QUAD_111_TRN_1_DIR : out std_logic;
720  MP1_F11_QUAD_111_TRN_1_CMP : out std_logic;
721  MP1_F10_QUAD_111_TRN_2_DIR : out std_logic;
722  MP1_F10_QUAD_111_TRN_2_CMP : out std_logic;
723  MP1_F08_QUAD_111_TRN_3_DIR : out std_logic;
724  MP1_F08_QUAD_111_TRN_3_CMP : out std_logic;
725  MP1_F04_QUAD_112_TRN_0_DIR : out std_logic;
726  MP1_F04_QUAD_112_TRN_0_CMP : out std_logic;
727  MP1_F06_QUAD_112_TRN_1_DIR : out std_logic;
728  MP1_F06_QUAD_112_TRN_1_CMP : out std_logic;
729  MP1_F02_QUAD_112_TRN_2_DIR : out std_logic;
730  MP1_F02_QUAD_112_TRN_2_CMP : out std_logic;
731  MP1_F00_QUAD_112_TRN_3_DIR : out std_logic;
732  MP1_F00_QUAD_112_TRN_3_CMP : out std_logic;
733  MP2_F01_QUAD_113_TRN_0_DIR : out std_logic;
734  MP2_F01_QUAD_113_TRN_0_CMP : out std_logic;
735  MP2_F03_QUAD_113_TRN_1_DIR : out std_logic;
736  MP2_F03_QUAD_113_TRN_1_CMP : out std_logic;
737  MP2_F07_QUAD_113_TRN_2_DIR : out std_logic;
738  MP2_F07_QUAD_113_TRN_2_CMP : out std_logic;
739  MP2_F05_QUAD_113_TRN_3_DIR : out std_logic;
740  MP2_F05_QUAD_113_TRN_3_CMP : out std_logic;
741  MP2_F09_QUAD_114_TRN_0_DIR : out std_logic;
742  MP2_F09_QUAD_114_TRN_0_CMP : out std_logic;
743  MP2_F11_QUAD_114_TRN_1_DIR : out std_logic;
744  MP2_F11_QUAD_114_TRN_1_CMP : out std_logic;
745  MP2_F10_QUAD_114_TRN_2_DIR : out std_logic;
746  MP2_F10_QUAD_114_TRN_2_CMP : out std_logic;
747  MP2_F08_QUAD_114_TRN_3_DIR : out std_logic;
748  MP2_F08_QUAD_114_TRN_3_CMP : out std_logic;
749  MP2_F04_QUAD_115_TRN_0_DIR : out std_logic;
750  MP2_F04_QUAD_115_TRN_0_CMP : out std_logic;
751  MP2_F06_QUAD_115_TRN_1_DIR : out std_logic;
752  MP2_F06_QUAD_115_TRN_1_CMP : out std_logic;
753  MP2_F02_QUAD_115_TRN_2_DIR : out std_logic;
754  MP2_F02_QUAD_115_TRN_2_CMP : out std_logic;
755  MP2_F00_QUAD_115_TRN_3_DIR : out std_logic;
756  MP2_F00_QUAD_115_TRN_3_CMP : out std_logic;
757  CLK_320MHz64_LHC_BF_QUAD_111_DIR : in std_logic;
758  CLK_320MHz64_LHC_BF_QUAD_111_CMP : in std_logic;
759  CLK_320MHz64_LHC_BF_QUAD_114_DIR : in std_logic;
760  CLK_320MHz64_LHC_BF_QUAD_114_CMP : in std_logic;
761  --clk40 : in std_logic;
762  RXN_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
763  RXP_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0)
764 
765 
766  );
767 
768 
769 end CMX_top_Base;
770 
771 architecture Behavioral of CMX_top_Base is
772 
773  attribute keep : string; -- keep signals in synthesis
774  attribute IOB : string;
775 
776 
777  ------------------------------------------------------------------------------
778  -- VME interface component used in BSPT FPGA (Ian's vme_interface)
779  ------------------------------------------------------------------------------
780  component CMX_BASE_VME_BSPT is
781  port (
782  clk40 : IN std_logic; -- 40MHz Clk
783  geoadd_0 : IN std_logic; -- GeoAddr0
784  n_ds0_int : IN std_logic; -- DS strobe
785  n_write : IN std_logic; -- VME Write
786  vme_address : IN std_logic_vector (23 DOWNTO 1); -- Address bus
787  board_ds : OUT std_logic; -- Board ds
788  brdsel_n : OUT std_logic -- Board select
789  );
790  end component;
791  -- signals for CMX_BASE_VME_INTERFACE component
792  signal ds: std_logic; -- board_ds output from VME (Ian model)
793  signal ncs: std_logic; -- brdsel_n output from VME (Ian model)
794 
795  signal vme_address : std_logic_vector(23 downto 1);
796 
797  component vme_outreg
798  generic (
799  ia_vme : integer;
800  width : integer);
801  port (
802  clk : in std_logic;
803  addr_vme : in std_logic_vector (15 downto 0);
804  ncs : in std_logic;
805  rd_nwr : in std_logic;
806  ds : in std_logic;
807  data_to_vme : in std_logic_vector (width-1 downto 0);
808  read_detect : out std_logic;
809  data_vme : out std_logic_vector (15 downto 0));
810  end component;
811 
812  signal read_detect_outreg_test : std_logic;
813  signal data_to_vme_outreg_test : std_logic_vector (15 downto 0);
814 
815 
816  component vme_inreg
817  generic (
818  ia_vme : integer;
819  width : integer);
820  port (
821  clk : in std_logic;
822  ncs : in std_logic;
823  rd_nwr : in std_logic;
824  ds : in std_logic;
825  data_from_vme : out std_logic_vector (width-1 downto 0);
826  data_to_vme : in std_logic_vector (width-1 downto 0);
827  addr_vme : in std_logic_vector (15 downto 0);
828  read_detect : out std_logic;
829  write_detect : out std_logic;
830  data_vme : inout std_logic_vector (15 downto 0));
831  end component;
832 
833  component vme_inreg_async is
834  generic (
835  ia_vme : integer;
836  width : integer);
837  port (
838  ncs : in std_logic;
839  rd_nwr : in std_logic;
840  ds : in std_logic;
841  addr_vme : in std_logic_vector (15 downto 0);
842  data_vme : inout std_logic_vector (15 downto 0);
843  data_from_vme : out std_logic_vector (width-1 downto 0);
844  data_to_vme : in std_logic_vector (width-1 downto 0));
845  end component vme_inreg_async;
846 
847  component vme_local_switch is
848  port (
849  data_vme_up : out std_logic_vector (15 downto 0);
850  data_vme_from_below : in arr_16;
851  bus_drive_up : out std_logic;
852  bus_drive_from_below : in std_logic_vector);
853  end component vme_local_switch;
854 
855  component vme_main_hub is
856  port (
857  data_vme : inout std_logic_vector(15 downto 0);
858  data_vme_from_below : in std_logic_vector (15 downto 0);
859  bus_drive_from_below : in std_logic;
860  data_vme_going_below : out std_logic_vector(15 downto 0));
861  end component vme_main_hub;
862 
863  signal data_vme_from_below_top : arr_16(1762 downto 0);
864  signal bus_drive_from_below_top : std_logic_vector(1762 downto 0);
865  signal bus_drive_up_top : std_logic;
866  signal data_vme_up_top : std_logic_vector(15 downto 0);
867  signal data_vme_going_below : std_logic_vector(15 downto 0);
868 
869  component vme_inreg_notri_async is
870  generic (
871  ia_vme : integer;
872  width : integer);
873  port (
874  ncs : in std_logic;
875  rd_nwr : in std_logic;
876  ds : in std_logic;
877  addr_vme : in std_logic_vector (15 downto 0);
878  data_vme_in : in std_logic_vector (15 downto 0);
879  data_vme_out : out std_logic_vector (15 downto 0);
880  bus_drive : out std_logic;
881  data_from_vme : out std_logic_vector (width-1 downto 0);
882  data_to_vme : in std_logic_vector (width-1 downto 0));
883  end component vme_inreg_notri_async;
884 
885  component vme_outreg_notri_async is
886  generic (
887  ia_vme : integer;
888  width : integer);
889  port (
890  ncs : in std_logic;
891  rd_nwr : in std_logic;
892  ds : in std_logic;
893  addr_vme : in std_logic_vector (15 downto 0);
894  data_vme : out std_logic_vector (15 downto 0);
895  bus_drive : out std_logic;
896  data_to_vme : in std_logic_vector (width-1 downto 0));
897  end component vme_outreg_notri_async;
898 
899  component vme_inreg_notri is
900  generic (
901  ia_vme : integer;
902  width : integer);
903  port (
904  clk : in std_logic;
905  ncs : in std_logic;
906  rd_nwr : in std_logic;
907  ds : in std_logic;
908  addr_vme : in std_logic_vector (15 downto 0);
909  data_vme_in : in std_logic_vector (15 downto 0);
910  data_vme_out : out std_logic_vector (15 downto 0);
911  bus_drive : out std_logic;
912  data_from_vme : out std_logic_vector (width-1 downto 0);
913  data_to_vme : in std_logic_vector (width-1 downto 0);
914  read_detect : out std_logic;
915  write_detect : out std_logic);
916  end component vme_inreg_notri;
917 
918  component vme_outreg_notri is
919  generic (
920  ia_vme : integer;
921  width : integer);
922  port (
923  clk : in std_logic;
924  ncs : in std_logic;
925  rd_nwr : in std_logic;
926  ds : in std_logic;
927  addr_vme : in std_logic_vector (15 downto 0);
928  data_vme : out std_logic_vector (15 downto 0);
929  bus_drive : out std_logic;
930  data_to_vme : in std_logic_vector (width-1 downto 0);
931  read_detect : out std_logic);
932  end component vme_outreg_notri;
933 
934  signal data_from_vme_test_rw : std_logic_vector (15 downto 0);
935  signal data_to_vme_test_rw : std_logic_vector (15 downto 0);
936  signal read_detect_inreg_test : std_logic;
937  signal write_detect_inreg_test : std_logic;
938  signal test_rw_counter : unsigned(15 downto 0);
939  signal data_to_vme_test_r : std_logic_vector (15 downto 0);
940 
941  signal start_playback, start_playback_r1: std_logic; --r1 is the the
942  --BF_TO_FROM_BSPT_0
943  --registered once
944  -- the first variable is
945  -- yet one more register
946  -- (so synchroniser)
947 
948  component CMX_version is
949  port (
950  clk40 : in std_logic;
951  ncs : in std_logic;
952  rd_nwr : in std_logic;
953  ds : in std_logic;
954  addr_vme : in std_logic_vector (15 downto 0);
955  data_vme_out : out std_logic_vector (15 downto 0);
956  bus_drive : out std_logic);
957  end component CMX_version;
958 
959 
960 
961  component sys_monitor is
962  generic (
963  ADDR_REG_RO_SYSMON_DATA_BLOCK : integer);
964  port (
965  clk : in std_logic;
966  BF_SYSMON_01_P : in STD_LOGIC;
967  BF_SYSMON_01_N : in STD_LOGIC;
968  BF_SYSMON_03_P : in STD_LOGIC;
969  BF_SYSMON_03_N : in STD_LOGIC;
970  BF_SYSMON_04_P : in STD_LOGIC;
971  BF_SYSMON_04_N : in STD_LOGIC;
972  BF_SYSMON_07_P : in STD_LOGIC;
973  BF_SYSMON_07_N : in STD_LOGIC;
974  BF_SYSMON_08_P : in STD_LOGIC;
975  BF_SYSMON_08_N : in STD_LOGIC;
976  BF_SYSMON_09_P : in STD_LOGIC;
977  BF_SYSMON_09_N : in STD_LOGIC;
978  BF_SYSMON_10_P : in STD_LOGIC;
979  BF_SYSMON_10_N : in STD_LOGIC;
980  BF_SYSMON_11_P : in STD_LOGIC;
981  BF_SYSMON_11_N : in STD_LOGIC;
982  BF_SYSMON_12_P : in STD_LOGIC;
983  BF_SYSMON_12_N : in STD_LOGIC;
984  BF_SYSMON_13_P : in STD_LOGIC;
985  BF_SYSMON_13_N : in STD_LOGIC;
986  BF_SYSMON_14_P : in STD_LOGIC;
987  BF_SYSMON_14_N : in STD_LOGIC;
988  BF_SYSMON_15_P : in STD_LOGIC;
989  BF_SYSMON_15_N : in STD_LOGIC;
990  ncs : in std_logic;
991  rd_nwr : in std_logic;
992  ds : in std_logic;
993  addr_vme : in std_logic_vector (15 downto 0);
994  data_vme_in : in std_logic_vector (15 downto 0);
995  data_vme_out : out std_logic_vector (15 downto 0);
996  bus_drive : out std_logic);
997  end component sys_monitor;
998 
999 
1000  component CMX_input_module
1001  port (
1002  P : in mat_var (numactchan-1 downto 0);
1003  buf_clk40 : in std_logic;
1004  buf_clk40_m180o : in std_logic;
1005  buf_clk200 : in std_logic;
1006  pll_locked : in std_logic;
1007  ODATA : out arr_4Xword (numactchan-1 downto 0);
1008  ODATA_first_half : out arr_2Xword(numactchan -1 downto 0);
1009  PAR_ERROR_total : out std_logic;--_vector(numactchan-1 downto 0);
1010  counter_enable_out : out std_logic_vector(numactchan-1 downto 0);
1011  counter_values : out std_logic_vector(numactchan-1 downto 0);
1012  del_register : in del_register_type;
1013  upload_delays : in std_logic;
1014  quiet : in std_logic;
1015  start_playback : in std_logic;
1016  spy_write_inhibit : in std_logic;
1017  ncs : in std_logic;
1018  rd_nwr : in std_logic;
1019  ds : in std_logic;
1020  addr_vme : in std_logic_vector (15 downto 0);
1021  data_vme_in : in std_logic_vector (15 downto 0);
1022  data_vme_out : out std_logic_vector (15 downto 0);
1023  bus_drive : out std_logic
1024  );
1025  end component;
1026 
1027  signal counter_values : std_logic_vector(numactchan-1 downto 0);
1028  signal del_register : del_register_type;
1029  signal upload_delays : std_logic;
1030 
1031  --signal PAR_ERROR: std_logic_vector(numactchan-1 downto 0);
1032 
1033  signal quiet : std_logic;
1034  signal force : std_logic;
1035 
1036  signal data_from_vme_REG_RW_QUIET_FORCE : std_logic_vector(15 downto 0);
1037  signal data_to_vme_REG_RW_QUIET_FORCE : std_logic_vector(15 downto 0);
1038 
1039  signal DATA96 : arr_4Xword (numactchan-1 downto 0); --96 bit data at 40MHz
1040  signal ODATA_first_half : arr_2Xword(numactchan-1 downto 0);
1041 
1042  signal P : mat_var (numactchan-1 downto 0);
1043 
1044  signal BF_DEBUG : std_logic_vector(9 downto 0);
1045 
1046  signal counter_enable_inputmod_sig: std_logic_vector(numactchan-1 downto 0);
1047 
1048 
1049  component CMX_Memory_spy_inhibit is
1050  port (
1051  spy_write_inhibit : out std_logic;
1052  buf_clk40 : in std_logic;
1053  ncs : in std_logic;
1054  rd_nwr : in std_logic;
1055  ds : in std_logic;
1056  addr_vme : in std_logic_vector (15 downto 0);
1057  data_vme_in : in std_logic_vector (15 downto 0);
1058  data_vme_out : out std_logic_vector (15 downto 0);
1059  bus_drive : out std_logic);
1060  end component CMX_Memory_spy_inhibit;
1061 
1062  signal spy_write_inhibit : std_logic;
1063 
1064  component decoder is
1065  generic (
1066  max_tobs_tot : integer;
1067  max_tobs_topo : integer;
1068  max_jems : integer;
1069  max_tobs_pjem : integer;
1070  et2_width : integer;
1071  et1_width : integer;
1072  pos_width : integer;
1073  thresholds_num : integer;
1074  thresholds_width : integer);
1075  port (
1076  clk40MHz : in std_logic;
1077  clk40MHz_m90o : in std_logic;
1078  clk40MHz_90o : in std_logic;
1079  clk40MHz_m180o : in std_logic;
1080  pll_locked : in std_logic;
1081  datai : in arr_4Xword(max_jems-1 downto 0);
1082  datai_first_half : in arr_2Xword(max_jems-1 downto 0);
1083  Tobs_to_TOPO : out copy_arr_TOB; -- TOB arrays to load onto
1084  -- encoder; copied x3
1085  overflow : out std_logic_vector(num_copies-1 downto 0);
1086  BCID_in : in std_logic_vector(11 downto 0);
1087  BCID_delayed : out std_logic_vector(11 downto 0);
1088  --tob rate counter contol
1089  counter_inhibit : in std_logic;
1090  counter_reset : in std_logic;
1091  --VME control:
1092  ncs : in std_logic;
1093  rd_nwr : in std_logic;
1094  ds : in std_logic;
1095  addr_vme : in std_logic_vector (15 downto 0);
1096  data_vme_out : out std_logic_vector (15 downto 0);
1097  bus_drive : out std_logic);
1098  end component decoder;
1099 
1100  signal Tobs_to_TOPO : copy_arr_TOB;
1101  signal overflow : std_logic_vector(num_copies-1 downto 0);
1102 
1103  signal data_from_vme_REG_RW_JET_THRESHOLD_BLOCK : arr_16(1599 downto 0);
1104  signal data_to_vme_REG_RW_JET_THRESHOLD_BLOCK : arr_16(1599 downto 0);
1105 
1106 
1107  component adder_top is
1108  generic (
1109  numactchan : integer;
1110  ADDR_REG_RW_PIPELINE_DELAY_LENGTH : integer;
1111  gen_system : std_logic := '1');
1112  port (
1113  clk : in T_SL; -- clock
1114  thresholds : in arr_16(max_jems*25*4-1 downto 0); -- thresholds
1115  datai : in arr_4Xword(max_jems-1 downto 0); -- input data
1116  din_cbl : in T_SLV65; -- remote input (multiplicty)
1117  din_cbl_ro : in T_SL; -- remote input (overflow)
1118  dout_lcl : out std_logic_vector(59 downto 0); -- local multiplicity
1119  dout_lcl_ro : out T_SL; -- local overflow
1120  dout : out T_SLV62; -- global output data (multiplicity), including parity
1121  dout_ro : out T_SL; -- global overflow
1122  dout_cbla_mux0 : out std_logic_vector(33 downto 0); -- cable output data (multiplicity), including parity
1123  dout_cbla_mux1 : out std_logic_vector(33 downto 0); -- cable output data (multiplicity), including parity
1124  dout_cblb_mux0 : out std_logic_vector(33 downto 0); -- cable output data (multiplicity), including parity
1125  dout_cblb_mux1 : out std_logic_vector(33 downto 0); -- cable output data (multiplicity), including parity
1126 
1127  --VME control:
1128  ncs : in std_logic;
1129  rd_nwr : in std_logic;
1130  ds : in std_logic;
1131  addr_vme : in std_logic_vector (15 downto 0);
1132  data_vme_in : in std_logic_vector (15 downto 0);
1133  data_vme_out : out std_logic_vector (15 downto 0);
1134  bus_drive : out std_logic;
1135  par_err : in T_SLV2; -- parity error (input module - 0, RTM - 1)
1136  force : in T_SL; -- force
1137  -- counter signals
1138  reset : in T_SL;
1139  inhibit : in T_SL
1140  );
1141  end component adder_top;
1142 
1143  signal par_err : T_SLV2;
1144 
1145  signal dout_cbla_mux0 : std_logic_vector(33 downto 0);
1146  signal dout_cbla_mux1 : std_logic_vector(33 downto 0);
1147  signal dout_cblb_mux0 : std_logic_vector(33 downto 0);
1148  signal dout_cblb_mux1 : std_logic_vector(33 downto 0);
1149 
1150  signal data_to_RTM1 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1151  signal data_to_RTM2 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1152 
1153 
1154  signal thresholds : arr_16(max_jems*25*4-1 downto 0); -- thresholds
1155 
1156 -- signal p_d : nx121_array(numactchan-1 downto 0); --120 bits + parity -
1157 -- --will be connected to
1158 -- --the decoder output
1159 -- --threshold mask 25
1160 -- --threshold times 4
1161 -- --TOBs + 5 bits position/TOB
1162 
1163  signal din_cbl : T_SLV65;
1164 
1165  signal dout_lcl : T_SLV60; -- local multiplicity
1166  signal dout_lcl_ro : T_SL;
1167  --signal dout : T_SLV62; --data to CTP from adder
1168 
1169  --component CMX_cable_clocked_80Mbps_output_module
1170  -- generic (
1171  -- numbits_in_cable_connector : integer);
1172  -- port (
1173  -- data : in std_logic_vector((numbits_in_cable_connector*2)-1 downto 0);
1174  -- ddr_data_out : out std_logic_vector(numbits_in_cable_connector downto 0);
1175  -- buf_clk40 : in std_logic;
1176  -- buf_clk40_center : in std_logic;
1177  -- buf_clk200 : in std_logic;
1178  -- pll_locked : in std_logic;
1179  -- del_array : in cable_del_array_type(numbits_in_cable_connector downto 0);
1180  -- upload_delays : in std_logic);
1181  --end component;
1182 
1183 
1184  component daq_collector is
1185  port (
1186  clk : in T_SL;
1187  datai : in arr_4Xword(max_jems-1 downto 0);
1188  din_cbl : in T_SLV65;
1189  din_cbl_ro : in T_SL;
1190  din_lcl : in T_SLV60;
1191  din_lcl_ro : in T_SL;
1192  dout : in T_SLV62;
1193  dout_ro : in T_SL;
1194  data_in_daq : out arr_96(19 downto 0);
1195  BCID_in : in std_logic_vector(11 downto 0);
1196  BCID_delayed : out std_logic_vector(11 downto 0));
1197  end component daq_collector;
1198 
1199 
1200  component CMX_crate_cable_output_module is
1201  port (
1202  data : in std_logic_vector(numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1203  ddr_data_out : out arr_RTM(num_RTM_cables-1 downto 0);
1204  buf_clk40 : in std_logic;
1205  buf_clk40_center : in std_logic;
1206  pll_locked : in std_logic;
1207  start_playback : in std_logic;
1208  spy_write_inhibit : in std_logic;
1209  ncs : in std_logic;
1210  rd_nwr : in std_logic;
1211  ds : in std_logic;
1212  addr_vme : in std_logic_vector (15 downto 0);
1213  data_vme_in : in std_logic_vector (15 downto 0);
1214  data_vme_out : out std_logic_vector (15 downto 0);
1215  bus_drive : out std_logic);
1216  end component CMX_crate_cable_output_module;
1217 
1218  signal data_to_RTM : std_logic_vector( numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1219  signal ddr_data_out_RTM : arr_RTM(num_RTM_cables-1 downto 0);
1220 
1221  signal sdr_data_out_CTP1 : std_logic_vector(31 downto 0);
1222  signal sdr_data_out_CTP2 : std_logic_vector(31 downto 0);
1223  --signal sdr_data_out : std_logic_vector(31 downto 0);
1224 
1225  signal ddr_data_out_RTM1 : std_logic_vector(numbits_in_RTM_connector downto 0);
1226  signal ddr_data_out_RTM2 : std_logic_vector(numbits_in_RTM_connector downto 0);
1227  --signal del_array_RTM : cable_del_array_type(numbits_in_RTM_connector downto 0);
1228 
1229  --signal ddr_data_in_RTM1 : std_logic_vector(numbits_in_RTM_connector downto 0);
1230  --signal ddr_data_in_RTM2 : std_logic_vector(numbits_in_RTM_connector downto 0);
1231  --signal sig_arr_RTM: arr_RTM(num_RTM_cables-1 downto 0);
1232  --signal data_from_RTM : std_logic_vector(numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1233 
1234  component CMX_system_cable_input_module is
1235  port (
1236  data : out std_logic_vector(numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1237  parity_error : out std_logic_vector(num_RTM_cables-1 downto 0);
1238  ddr_data_in : in arr_RTM(num_RTM_cables-1 downto 0);
1239  buf_clk40 : in std_logic;
1240  buf_clk40_ds2 : in std_logic;
1241  pll_locked : in std_logic;
1242  pll_locked_ds2 : in std_logic;
1243  start_playback : in std_logic;
1244  spy_write_inhibit : in std_logic;
1245  ncs : in std_logic;
1246  rd_nwr : in std_logic;
1247  ds : in std_logic;
1248  addr_vme : in std_logic_vector (15 downto 0);
1249  data_vme : inout std_logic_vector (15 downto 0));
1250  end component CMX_system_cable_input_module;
1251 
1252  component CMX_cable_clocked_80Mbps_input_module
1253  generic (
1254  numbits_in_cable_connector : integer);
1255  port (
1256  data : out std_logic_vector((numbits_in_cable_connector*2)-1 downto 0);
1257  parity : out std_logic;
1258  forwarded_clock : out std_logic;
1259  ddr_data_in : in std_logic_vector(numbits_in_cable_connector downto 0);
1260  buf_clk40 : in std_logic;
1261  buf_clk200 : in std_logic;
1262  pll_locked : in std_logic;
1263  del_array : in cable_del_array_type(numbits_in_cable_connector downto 0);
1264  upload_delays : in std_logic);
1265  end component;
1266 
1267 
1268 
1269 
1270  --signal forwarded_clock_CTP2 : std_logic;
1271  --signal data_CTP2 : std_logic_vector((numbits_in_CTP_connector*2)-1 downto 0);
1272  --signal parity_CTP2 : std_logic;
1273  --signal ddr_data_in_CTP2 : std_logic_vector(numbits_in_CTP_connector downto 0);
1274  --
1275  --signal forwarded_clock_RTM3 : std_logic;
1276  --signal data_RTM3 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1277  --signal parity_RTM3 : std_logic;
1278  --signal ddr_data_in_RTM3 : std_logic_vector(numbits_in_RTM_connector downto 0);
1279 
1280  component BCID_counter
1281  port (
1282  reset : in std_logic;
1283  clk_40 : in std_logic;
1284  BCID_out : out std_logic_vector(11 downto 0);
1285  --VME control:
1286  ncs : in std_logic; --ports forwarded to the vme register instances
1287  rd_nwr : in std_logic;
1288  ds : in std_logic;
1289  addr_vme : in std_logic_vector (15 downto 0);
1290  data_vme_in : in std_logic_vector (15 downto 0);
1291  data_vme_out : out std_logic_vector (15 downto 0);
1292  bus_drive : out std_logic);
1293  end component;
1294  signal BCID_counter_sig : std_logic_vector(11 downto 0);
1295  signal BCID_delayed_decoder : std_logic_vector(11 downto 0);
1296  signal BCID_delayed_daq : std_logic_vector(11 downto 0);
1297 
1298 
1299 
1300  component PRNG_LFSR_BIG is
1301  port (
1302  clk : in std_logic;
1303  rst : in std_logic;
1304  DATA_PRN : out std_logic_vector(63 downto 0));
1305  end component PRNG_LFSR_BIG;
1306  signal DATA_PRN: arr_64((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1307 
1308  --component Topo_Data_TX
1309  -- port (
1310  -- MGTREFCLK_PAD_N_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1311  -- MGTREFCLK_PAD_P_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1312  -- GTXTXRESET_IN : in std_logic;
1313  -- GTXRXRESET_IN : in std_logic;
1314  -- GTX_TX_READY_OUT : out std_logic;
1315  -- GTX_RX_READY_OUT : out std_logic;
1316  -- RXN_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1317  -- RXP_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1318  -- TXN_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1319  -- TXP_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1320  -- clk40 : in std_logic;
1321  -- clk320 : in std_logic;
1322  -- pll_locked : in std_logic;
1323  -- send_align : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1324  -- BCID : in std_logic_vector(11 downto 0);
1325  -- indata : in std_logic_vector(TX_indata_length-1 downto 0);
1326  -- ext_trigger :in std_logic;
1327  -- ncs : in std_logic;
1328  -- rd_nwr : in std_logic;
1329  -- ds : in std_logic;
1330  -- addr_vme : in std_logic_vector (15 downto 0);
1331  -- data_vme : inout std_logic_vector (15 downto 0)
1332  -- );
1333  --end component;
1334 
1335  component Topo_Data_TX is
1336  port (
1337  MGTREFCLK_PAD_N_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1338  MGTREFCLK_PAD_P_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1339  GTXTXRESET_IN : in std_logic;
1340  GTXRXRESET_IN : in std_logic;
1341  GTX_TX_READY_OUT : out std_logic;
1342  GTX_RX_READY_OUT : out std_logic;
1343  RXN_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1344  RXP_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1345  TXN_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1346  TXP_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1347  clk40 : in std_logic;
1348  clk320 : in std_logic;
1349  pll_locked : in std_logic;
1350  send_align : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1351  BCID : in std_logic_vector(11 downto 0);
1352  indata : in std_logic_vector(TX_indata_length-1 downto 0);
1353  ext_trigger : in std_logic;
1354  ncs : in std_logic;
1355  rd_nwr : in std_logic;
1356  ds : in std_logic;
1357  addr_vme : in std_logic_vector (15 downto 0);
1358  data_vme_in : in std_logic_vector (15 downto 0);
1359  data_vme_out : out std_logic_vector (15 downto 0);
1360  bus_drive : out std_logic);
1361  end component Topo_Data_TX;
1362 
1363 
1364  component CMX_Jet_Topo_Encoder is
1365  port (
1366  Tobs_to_TOPO : in copy_arr_TOB;
1367  overflow : in std_logic_vector(num_copies-1 downto 0);
1368  send_align_out : out std_logic_vector(num_GTX_groups*num_GTX_per_group - 1 downto 0);
1369  Data_out : out std_logic_vector(TX_indata_length - 1 downto 0));
1370  --clk : in std_logic);
1371  end component CMX_Jet_Topo_Encoder;
1372 
1373  signal TXN_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1374  signal TXP_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1375 
1376  signal MGTREFCLK_PAD_N_IN : std_logic_vector(num_GTX_groups-1 downto 0);
1377  signal MGTREFCLK_PAD_P_IN : std_logic_vector(num_GTX_groups-1 downto 0);
1378 
1379  signal GTX_RX_READY_OUT : std_logic;
1380  signal GTX_TX_READY_OUT : std_logic;
1381 
1382 
1383  signal GTXTXRESET_IN : std_logic;
1384  signal GTXRXRESET_IN : std_logic;
1385 
1386  signal send_align : std_logic_vector(23 downto 0);
1387 
1388  signal indata_Topo_TX : std_logic_vector(TX_indata_length-1 downto 0);
1389 
1390  signal data_to_vme_REG_RW_TOPOTR_GTX_RESET : std_logic_vector(15 downto 0);
1391  signal data_from_vme_REG_RW_TOPOTR_GTX_RESET : std_logic_vector(15 downto 0);
1392 
1393  signal data_to_vme_REG_RO_TOPOTR_GTX_STATUS : std_logic_vector(15 downto 0);
1394 
1395  signal data_from_vme_REG_RW_DAQ_ROI_RESET : std_logic_vector(15 downto 0);
1396  signal data_to_vme_REG_RW_DAQ_ROI_RESET : std_logic_vector(15 downto 0);
1397 
1398  signal data_to_vme_REG_RO_DAQ_ROI_STATUS : std_logic_vector(15 downto 0);
1399 
1400  signal data_from_vme_REG_RW_DAQ_ROI_GTX_RESET: std_logic_vector(15 downto 0);
1401  signal data_to_vme_REG_RW_DAQ_ROI_GTX_RESET: std_logic_vector(15 downto 0);
1402  signal gtx_reset_SFP_DAQ, gtx_reset_SFP_ROI : std_logic;
1403 
1404  signal BUF_TTC_L1_ACCEPT_r: std_logic;
1405  signal l1a_synced: std_logic;
1406 
1407  signal bc_reset_synced : std_logic;
1408  signal BUF_TTC_BNCH_CNT_RES_r : std_logic;
1409 
1410  component CMX_rate_counter_inhibit is
1411  port (
1412  counter_inhibit : out std_logic;
1413  counter_reset : out std_logic;
1414  buf_clk40 : in std_logic;
1415  ncs : in std_logic;
1416  rd_nwr : in std_logic;
1417  ds : in std_logic;
1418  addr_vme : in std_logic_vector (15 downto 0);
1419  data_vme_in : in std_logic_vector (15 downto 0);
1420  data_vme_out : out std_logic_vector (15 downto 0);
1421  bus_drive : out std_logic);
1422  end component CMX_rate_counter_inhibit;
1423 
1424  signal counter_inhibit : std_logic;
1425  signal counter_reset : std_logic;
1426 
1427 
1428 --WTF NO CS 20141128
1429 --WTF NO CS 20141128
1430 --WTF NO CS 20141128 component chipscope_ila_CMX_top_inputmodclk
1431 --WTF NO CS 20141128 port (
1432 --WTF NO CS 20141128 CONTROL : inout std_logic_vector(35 downto 0);
1433 --WTF NO CS 20141128 CLK : in std_logic;
1434 --WTF NO CS 20141128 DATA : in std_logic_vector(2375 downto 0);
1435 --WTF NO CS 20141128 TRIG0 : in std_logic_vector(35 downto 0));
1436 --WTF NO CS 20141128 end component;
1437 --WTF NO CS 20141128
1438 --WTF NO CS 20141128 signal DATA_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(2375 downto 0);
1439 --WTF NO CS 20141128 signal TRIG0_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(35 downto 0);
1440 --WTF NO CS 20141128 --signal TRIG_forward_inputmodclk_outputmodclk : std_logic_vector(0 downto 0);
1441 
1442  --component chipscope_ila_IDELAY
1443  -- port (
1444  -- CONTROL : inout std_logic_vector(35 downto 0);
1445  -- CLK : in std_logic;
1446  -- DATA : in std_logic_vector(2000 downto 0);
1447  -- TRIG0 : in std_logic_vector(0 to 0));
1448  --end component;
1449 
1450  --signal DATA_chipscope_ila_IDELAY : std_logic_vector(2000 downto 0);
1451 
1452 
1453  --component chipscope_ila_CTP2
1454  -- port (
1455  -- CONTROL : inout std_logic_vector(35 downto 0);
1456  -- CLK : in std_logic;
1457  -- DATA : in std_logic_vector(64 downto 0);
1458  -- TRIG0 : in std_logic_vector(0 to 0));
1459  --end component;
1460  --
1461  --component chipscope_ila_RTM
1462  -- port (
1463  -- CONTROL : inout std_logic_vector(35 downto 0);
1464  -- CLK : in std_logic;
1465  -- DATA : in std_logic_vector(52 downto 0);
1466  -- TRIG0 : in std_logic_vector(0 to 0));
1467  --end component;
1468 
1469  --component chipscope_ila_LVDS_TX_CTP_RTM
1470  -- port (
1471  -- CONTROL : inout std_logic_vector(35 downto 0);
1472  -- CLK : in std_logic;
1473  -- DATA : in std_logic_vector(117 downto 0);
1474  -- TRIG0 : in std_logic_vector(1 downto 0));
1475  --end component;
1476 
1477 
1478  component CMX_clock_manager is
1479  port (
1480  I_DS1 : in std_logic;
1481  IB_DS1 : in std_logic;
1482  buf_clk40 : out std_logic;
1483  buf_clk40_90o : out std_logic;
1484  buf_clk40_m180o : out std_logic;
1485  buf_clk40_m90o : out std_logic;
1486  buf_clk320 : out std_logic;
1487  buf_clk160 : out std_logic;
1488  buf_clk200 : out std_logic;
1489  pll_locked : out std_logic;
1490  I_DS2 : in std_logic;
1491  IB_DS2 : in std_logic;
1492  buf_clk40_ds2 : out std_logic;
1493  pll_locked_ds2 : out std_logic;
1494  ncs : in std_logic;
1495  rd_nwr : in std_logic;
1496  ds : in std_logic;
1497  addr_vme : in std_logic_vector (15 downto 0);
1498  data_vme_in : in std_logic_vector (15 downto 0);
1499  data_vme_out : out std_logic_vector (15 downto 0);
1500  bus_drive : out std_logic);
1501  end component CMX_clock_manager;
1502 
1503 
1504  signal buf_clk40 : std_logic;
1505  signal buf_clk40_m180o : std_logic;
1506  signal buf_clk40_90o : std_logic;
1507  signal buf_clk40_m90o : std_logic;
1508 
1509  signal buf_clk320 : std_logic;
1510  signal buf_clk160 : std_logic;
1511  signal buf_clk200 : std_logic;
1512  signal pll_locked : std_logic;
1513 
1514  signal buf_clk40_ds2 : std_logic;
1515  signal pll_locked_ds2 : std_logic;
1516 
1517  component CMX_delay_generator
1518  generic (
1519  start_address : integer);
1520  port (
1521  clk40 : in std_logic;
1522  ncs : in std_logic;
1523  rd_nwr : in std_logic;
1524  ds : in std_logic;
1525  addr_vme : in std_logic_vector (15 downto 0);
1526  data_vme_in : in std_logic_vector (15 downto 0);
1527  data_vme_out : out std_logic_vector (15 downto 0);
1528  bus_drive : out std_logic;
1529  del_register : out del_register_type;
1530  upload_delays : out std_logic);
1531  end component;
1532 
1533  component CMX_CTP_output_module is
1534  port (
1535  data : in std_logic_vector((numbits_in_CTP_connector*2)-1 downto 0);
1536  sdr_data_out : out arr_CTP;
1537  buf_clk40 : in std_logic;
1538  buf_clk40_center : in std_logic;
1539  buf_clk200 : in std_logic;
1540  pll_locked : in std_logic;
1541  start_playback : in std_logic;
1542  spy_write_inhibit : in std_logic;
1543  ncs : in std_logic;
1544  rd_nwr : in std_logic;
1545  ds : in std_logic;
1546  addr_vme : in std_logic_vector (15 downto 0);
1547  data_vme : inout std_logic_vector (15 downto 0));
1548  end component CMX_CTP_output_module;
1549 
1550  --signal sdr_data_CTP: arr_CTP;
1551 
1552  component CMX_CTP_out_tester
1553  port (
1554  sdr_data_out : out std_logic_vector(31 downto 0);
1555  buf_clk40 : in std_logic;
1556  pll_locked : in std_logic;
1557  ncs : in std_logic;
1558  rd_nwr : in std_logic;
1559  ds : in std_logic;
1560  addr_vme : in std_logic_vector (15 downto 0);
1561  data_vme : inout std_logic_vector (15 downto 0));
1562  end component;
1563 
1564 
1565 
1566  component SFP_Data_TXRX
1567  generic (
1568  direction : std_logic;
1569  clock_source : std_logic);
1570  port (
1571  MGTREFCLK : in std_logic;
1572  gtx_reset : in std_logic;
1573  local_pll_lock_out: out std_logic;
1574  GTX_TX_READY_OUT : out std_logic;
1575  GTX_RX_READY_OUT : out std_logic;
1576  PLLLKDET_diag : out std_logic;
1577  local_gtx_reset_diag : out std_logic;
1578  local_mmcm_reset_diag : out std_logic;
1579  GTXTEST_diag : out std_logic;
1580  RXN_IN : in std_logic;
1581  RXP_IN : in std_logic;
1582  TXN_OUT : out std_logic;
1583  TXP_OUT : out std_logic;
1584  clk40_out : out std_logic;
1585  clk120_out : out std_logic;
1586  clk40_in : in std_logic;
1587  clk120_in : in std_logic;
1588  indata : in std_logic_vector(7 downto 0);
1589  odata : out std_logic_vector(7 downto 0);
1590  TXPREEMPHASIS_IN : in std_logic_vector(3 downto 0);
1591  TXPOSTEMPHASIS_IN : in std_logic_vector(4 downto 0);
1592  TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
1593  RXEQMIX_IN : in std_logic_vector(2 downto 0);
1594  DFECLKDLYADJ : in std_logic_vector(5 downto 0);
1595  DFECLKDLYADJMON : out std_logic_vector(5 downto 0);
1596  DFEDLYOVRD : in std_logic;
1597  DFEEYEDACMON : out std_logic_vector(4 downto 0);
1598  DFESENSCAL : out std_logic_vector(2 downto 0);
1599  DFETAP1 : in std_logic_vector(4 downto 0);
1600  DFETAP1MONITOR : out std_logic_vector(4 downto 0);
1601  DFETAP2 : in std_logic_vector(4 downto 0);
1602  DFETAP2MONITOR : out std_logic_vector(4 downto 0);
1603  DFETAP3 : in std_logic_vector(3 downto 0);
1604  DFETAP3MONITOR : out std_logic_vector(3 downto 0);
1605  DFETAP4 : in std_logic_vector(3 downto 0);
1606  DFETAP4MONITOR : out std_logic_vector(3 downto 0);
1607  DFETAPOVRD : in std_logic);
1608  end component;
1609 
1610  signal MGTREFCLK_Q118 : std_logic;
1611 
1612  signal GTXTXRESET_IN_TX_SFP_DAQ : std_logic;
1613  signal GTXRXRESET_IN_TX_SFP_DAQ : std_logic;
1614  signal local_pll_lock_out_SFP_DAQ : std_logic;
1615  signal GTX_TX_READY_OUT_TX_SFP_DAQ : std_logic;
1616  signal GTX_RX_READY_OUT_TX_SFP_DAQ : std_logic;
1617  signal PLLLKDET_diag_TX_SFP_DAQ : std_logic;
1618  signal local_gtx_reset_diag_TX_SFP_DAQ : std_logic;
1619  signal local_mmcm_reset_diag_TX_SFP_DAQ : std_logic;
1620  signal GTXTEST_diag_TX_SFP_DAQ : std_logic;
1621  signal RXN_IN_TX_SFP_DAQ : std_logic;
1622  signal RXP_IN_TX_SFP_DAQ : std_logic;
1623  signal TXN_OUT_TX_SFP_DAQ : std_logic;
1624  signal TXP_OUT_TX_SFP_DAQ : std_logic;
1625  signal clk40_out_TX_SFP_DAQ : std_logic;
1626  signal clk120_out_TX_SFP_DAQ : std_logic;
1627  signal clk40_in_TX_SFP_DAQ : std_logic;
1628  signal clk120_in_TX_SFP_DAQ : std_logic;
1629  signal indata_TX_SFP_DAQ : std_logic_vector(7 downto 0);
1630  signal odata_TX_SFP_DAQ : std_logic_vector(7 downto 0);
1631  signal TXPREEMPHASIS_IN_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1632  signal TXPOSTEMPHASIS_IN_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1633  signal TXDIFFCTRL_IN_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1634  signal RXEQMIX_IN_TX_SFP_DAQ : std_logic_vector(2 downto 0);
1635  signal DFECLKDLYADJ_TX_SFP_DAQ : std_logic_vector(5 downto 0);
1636  signal DFECLKDLYADJMON_TX_SFP_DAQ : std_logic_vector(5 downto 0);
1637  signal DFEDLYOVRD_TX_SFP_DAQ : std_logic;
1638  signal DFEEYEDACMON_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1639  signal DFESENSCAL_TX_SFP_DAQ : std_logic_vector(2 downto 0);
1640  signal DFETAP1_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1641  signal DFETAP1MONITOR_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1642  signal DFETAP2_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1643  signal DFETAP2MONITOR_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1644  signal DFETAP3_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1645  signal DFETAP3MONITOR_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1646  signal DFETAP4_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1647  signal DFETAP4MONITOR_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1648  signal DFETAPOVRD_TX_SFP_DAQ : std_logic;
1649 
1650  signal GTXTXRESET_IN_TX_SFP_ROI : std_logic;
1651  signal GTXRXRESET_IN_TX_SFP_ROI : std_logic;
1652  signal local_pll_lock_out_SFP_ROI : std_logic;
1653  signal GTX_TX_READY_OUT_TX_SFP_ROI : std_logic;
1654  signal GTX_RX_READY_OUT_TX_SFP_ROI : std_logic;
1655  signal PLLLKDET_diag_TX_SFP_ROI : std_logic;
1656  signal local_gtx_reset_diag_TX_SFP_ROI : std_logic;
1657  signal local_mmcm_reset_diag_TX_SFP_ROI : std_logic;
1658  signal GTXTEST_diag_TX_SFP_ROI : std_logic;
1659  signal RXN_IN_TX_SFP_ROI : std_logic;
1660  signal RXP_IN_TX_SFP_ROI : std_logic;
1661  signal TXN_OUT_TX_SFP_ROI : std_logic;
1662  signal TXP_OUT_TX_SFP_ROI : std_logic;
1663  signal clk40_out_TX_SFP_ROI : std_logic;
1664  signal clk120_out_TX_SFP_ROI : std_logic;
1665  signal clk40_in_TX_SFP_ROI : std_logic;
1666  signal clk120_in_TX_SFP_ROI : std_logic;
1667  signal indata_TX_SFP_ROI : std_logic_vector(7 downto 0);
1668  signal odata_TX_SFP_ROI : std_logic_vector(7 downto 0);
1669  signal TXPREEMPHASIS_IN_TX_SFP_ROI : std_logic_vector(3 downto 0);
1670  signal TXPOSTEMPHASIS_IN_TX_SFP_ROI : std_logic_vector(4 downto 0);
1671  signal TXDIFFCTRL_IN_TX_SFP_ROI : std_logic_vector(3 downto 0);
1672  signal RXEQMIX_IN_TX_SFP_ROI : std_logic_vector(2 downto 0);
1673  signal DFECLKDLYADJ_TX_SFP_ROI : std_logic_vector(5 downto 0);
1674  signal DFECLKDLYADJMON_TX_SFP_ROI : std_logic_vector(5 downto 0);
1675  signal DFEDLYOVRD_TX_SFP_ROI : std_logic;
1676  signal DFEEYEDACMON_TX_SFP_ROI : std_logic_vector(4 downto 0);
1677  signal DFESENSCAL_TX_SFP_ROI : std_logic_vector(2 downto 0);
1678  signal DFETAP1_TX_SFP_ROI : std_logic_vector(4 downto 0);
1679  signal DFETAP1MONITOR_TX_SFP_ROI : std_logic_vector(4 downto 0);
1680  signal DFETAP2_TX_SFP_ROI : std_logic_vector(4 downto 0);
1681  signal DFETAP2MONITOR_TX_SFP_ROI : std_logic_vector(4 downto 0);
1682  signal DFETAP3_TX_SFP_ROI : std_logic_vector(3 downto 0);
1683  signal DFETAP3MONITOR_TX_SFP_ROI : std_logic_vector(3 downto 0);
1684  signal DFETAP4_TX_SFP_ROI : std_logic_vector(3 downto 0);
1685  signal DFETAP4MONITOR_TX_SFP_ROI : std_logic_vector(3 downto 0);
1686  signal DFETAPOVRD_TX_SFP_ROI : std_logic;
1687 
1688 
1689 -- glink emulator
1690 
1691  component glink_interface
1692  port (
1693  CLK_40MHz : in std_logic;
1694  CLK_120MHz : in std_logic;
1695  RST : in std_logic;
1696  DAQ_IN : in std_logic_vector (19 DOWNTO 0);
1697  ROI_IN : in std_logic_vector (19 DOWNTO 0);
1698  DAQ_DAV : in std_logic;
1699  ROI_DAV : in std_logic;
1700  DAQ_BYTE : OUT std_logic_vector (7 downto 0);
1701  ROI_BYTE : OUT std_logic_vector (7 downto 0);
1702  DAQ_ENCODED_DIAG : OUT std_logic_vector (23 downto 0);
1703  daq_byte_out : out std_logic_vector (1 downto 0);
1704  byte_pos_out : OUT std_logic_vector (5 downto 0);
1705  word_sel_out : OUT std_logic_vector(1 downto 0);
1706  readout_rst_out : OUT std_logic
1707  );
1708  end component;
1709 
1710  -- Glink emulator signals
1711 
1712  signal daq_in : std_logic_vector (19 DOWNTO 0);
1713  signal roi_in : std_logic_vector (19 DOWNTO 0);
1714  signal daq_dav : std_logic;
1715  signal roi_dav : std_logic;
1716  signal daq_byte : std_logic_vector (7 downto 0);
1717  signal roi_byte : std_logic_vector (7 downto 0);
1718  signal reset_daq : std_logic;
1719  signal daq_encoded_diag : std_logic_vector (23 downto 0);
1720  signal daq_byte_out : std_logic_vector (1 downto 0);
1721 
1722  signal byte_pos_out : std_logic_vector (5 downto 0);
1723  signal word_sel_out : std_logic_vector(1 downto 0);
1724  signal readout_rst_out : std_logic;
1725 
1726  --component chipscope_icon_u2_c3
1727  -- port (
1728  -- CONTROL0 : inout std_logic_vector(35 downto 0);
1729  -- CONTROL1 : inout std_logic_vector(35 downto 0);
1730  -- CONTROL2 : inout std_logic_vector(35 downto 0)
1731  -- );
1732  --end component;
1733  --
1734  --signal CONTROL0 : std_logic_vector(35 downto 0);
1735  --signal CONTROL1 : std_logic_vector(35 downto 0);
1736  --signal CONTROL2 : std_logic_vector(35 downto 0);
1737  --
1738  --signal data_ila_daq : std_logic_vector (53 downto 0);
1739  --signal trig_ila_daq : std_logic_vector (33 downto 0);
1740  --
1741  --signal data_ila_encoder : std_logic_vector (20 downto 0);
1742  --signal trig_ila_encoder : std_logic_vector (11 downto 0);
1743  --
1744  --signal data_ila_gtx_start : std_logic_vector (12 downto 0);
1745  --signal trig_ila_gtx_start : std_logic_vector (2 downto 0);
1746  --
1747  --
1748  ----signal data_ila_1 : std_logic_vector (16 downto 0);
1749  --
1750  --component glink_chipscope_analyzer
1751  -- port (
1752  -- CONTROL: inout std_logic_vector(35 downto 0);
1753  -- CLK: in std_logic;
1754  -- DATA: in std_logic_vector(53 downto 0);
1755  -- TRIG0: in std_logic_vector(33 downto 0));
1756  --end component;
1757  --
1758  --component glink_chipscope_analyzer_encoder
1759  -- port (
1760  -- CONTROL: inout std_logic_vector(35 downto 0);
1761  -- CLK: in std_logic;
1762  -- DATA: in std_logic_vector(20 downto 0);
1763  -- TRIG0: in std_logic_vector(11 downto 0));
1764  --end component;
1765  --
1766  --component glink_chipscope_analyzer_gtx_start is
1767  -- port (
1768  -- CONTROL : inout std_logic_vector(35 downto 0);
1769  -- CLK : in std_logic;
1770  -- DATA : in std_logic_vector(10 downto 0);
1771  -- TRIG0 : in std_logic_vector(0 to 0));
1772  --end component glink_chipscope_analyzer_gtx_start;
1773 
1774 
1775  component daq_glink is
1776  port (
1777  data_in : in arr_96(19 downto 0);
1778  bc_counter : in unsigned(11 downto 0);
1779  l1a : in std_logic;
1780  data_out : out std_logic_vector(19 downto 0);
1781  dav : out std_logic;
1782  clk4000 : in std_logic;
1783  clk4008 : in std_logic;
1784  reset : in std_logic;
1785  RAM_global_offset : in unsigned(7 downto 0);
1786  RAM_rel_offsets : in arr_ctr_8bit(18 downto 0);
1787  nslices : in unsigned(7 downto 0));
1788  end component daq_glink;
1789 
1790  signal RAM_global_offset : unsigned(7 downto 0);
1791  signal RAM_rel_offsets : arr_ctr_8bit(18 downto 0);
1792  signal nslices : unsigned(7 downto 0);
1793 
1794  signal data_in_daq: arr_96(19 downto 0);
1795 
1796  --control of daq delays
1797  signal data_from_vme_REG_RW_DAQ_SLICE: std_logic_vector(15 downto 0);
1798  signal data_to_vme_REG_RW_DAQ_SLICE: std_logic_vector(15 downto 0);
1799  signal data_from_vme_REG_RW_DAQ_RAM_OFFSET: std_logic_vector(15 downto 0);
1800  signal data_to_vme_REG_RW_DAQ_RAM_OFFSET: std_logic_vector(15 downto 0);
1801 
1802  signal data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1803  signal data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1804 
1805 
1806  attribute keep of start_playback_r1, BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r, send_align, ODATA_first_half : signal is "TRUE";
1807  attribute IOB of BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r : signal is "FORCE";
1808 
1809  --attribute IOB of BF_DOUT_CTP_00 : signal is "TRUE";
1810  --attribute IOB of BF_DOUT_CTP_01 : signal is "TRUE";
1811  --attribute IOB of BF_DOUT_CTP_02 : signal is "TRUE";
1812  --attribute IOB of BF_DOUT_CTP_03 : signal is "TRUE";
1813  --attribute IOB of BF_DOUT_CTP_04 : signal is "TRUE";
1814  --attribute IOB of BF_DOUT_CTP_05 : signal is "TRUE";
1815  --attribute IOB of BF_DOUT_CTP_06 : signal is "TRUE";
1816  --attribute IOB of BF_DOUT_CTP_07 : signal is "TRUE";
1817  --attribute IOB of BF_DOUT_CTP_08 : signal is "TRUE";
1818  --attribute IOB of BF_DOUT_CTP_09 : signal is "TRUE";
1819  --attribute IOB of BF_DOUT_CTP_10 : signal is "TRUE";
1820  --attribute IOB of BF_DOUT_CTP_11 : signal is "TRUE";
1821  --attribute IOB of BF_DOUT_CTP_12 : signal is "TRUE";
1822  --attribute IOB of BF_DOUT_CTP_13 : signal is "TRUE";
1823  --attribute IOB of BF_DOUT_CTP_14 : signal is "TRUE";
1824  --attribute IOB of BF_DOUT_CTP_15 : signal is "TRUE";
1825  --attribute IOB of BF_DOUT_CTP_16 : signal is "TRUE";
1826  --attribute IOB of BF_DOUT_CTP_17 : signal is "TRUE";
1827  --attribute IOB of BF_DOUT_CTP_18 : signal is "TRUE";
1828  --attribute IOB of BF_DOUT_CTP_19 : signal is "TRUE";
1829  --attribute IOB of BF_DOUT_CTP_20 : signal is "TRUE";
1830  --attribute IOB of BF_DOUT_CTP_21 : signal is "TRUE";
1831  --attribute IOB of BF_DOUT_CTP_22 : signal is "TRUE";
1832  --attribute IOB of BF_DOUT_CTP_23 : signal is "TRUE";
1833  --attribute IOB of BF_DOUT_CTP_24 : signal is "TRUE";
1834  --attribute IOB of BF_DOUT_CTP_25 : signal is "TRUE";
1835  --attribute IOB of BF_DOUT_CTP_26 : signal is "TRUE";
1836  --attribute IOB of BF_DOUT_CTP_27 : signal is "TRUE";
1837  --attribute IOB of BF_DOUT_CTP_28 : signal is "TRUE";
1838  --attribute IOB of BF_DOUT_CTP_29 : signal is "TRUE";
1839  --attribute IOB of BF_DOUT_CTP_64 : signal is "TRUE";
1840  --
1841  --attribute IOB of BF_DOUT_CTP_32 : signal is "TRUE";
1842  --attribute IOB of BF_DOUT_CTP_33 : signal is "TRUE";
1843  --attribute IOB of BF_DOUT_CTP_34 : signal is "TRUE";
1844  --attribute IOB of BF_DOUT_CTP_35 : signal is "TRUE";
1845  --attribute IOB of BF_DOUT_CTP_36 : signal is "TRUE";
1846  --attribute IOB of BF_DOUT_CTP_37 : signal is "TRUE";
1847  --attribute IOB of BF_DOUT_CTP_38 : signal is "TRUE";
1848  --attribute IOB of BF_DOUT_CTP_39 : signal is "TRUE";
1849  --attribute IOB of BF_DOUT_CTP_40 : signal is "TRUE";
1850  --attribute IOB of BF_DOUT_CTP_41 : signal is "TRUE";
1851  --attribute IOB of BF_DOUT_CTP_42 : signal is "TRUE";
1852  --attribute IOB of BF_DOUT_CTP_43 : signal is "TRUE";
1853  --attribute IOB of BF_DOUT_CTP_44 : signal is "TRUE";
1854  --attribute IOB of BF_DOUT_CTP_45 : signal is "TRUE";
1855  --attribute IOB of BF_DOUT_CTP_46 : signal is "TRUE";
1856  --attribute IOB of BF_DOUT_CTP_47 : signal is "TRUE";
1857  --attribute IOB of BF_DOUT_CTP_48 : signal is "TRUE";
1858  --attribute IOB of BF_DOUT_CTP_49 : signal is "TRUE";
1859  --attribute IOB of BF_DOUT_CTP_50 : signal is "TRUE";
1860  --attribute IOB of BF_DOUT_CTP_51 : signal is "TRUE";
1861  --attribute IOB of BF_DOUT_CTP_52 : signal is "TRUE";
1862  --attribute IOB of BF_DOUT_CTP_53 : signal is "TRUE";
1863  --attribute IOB of BF_DOUT_CTP_54 : signal is "TRUE";
1864  --attribute IOB of BF_DOUT_CTP_55 : signal is "TRUE";
1865  --attribute IOB of BF_DOUT_CTP_56 : signal is "TRUE";
1866  --attribute IOB of BF_DOUT_CTP_57 : signal is "TRUE";
1867  --attribute IOB of BF_DOUT_CTP_58 : signal is "TRUE";
1868  --attribute IOB of BF_DOUT_CTP_59 : signal is "TRUE";
1869  --attribute IOB of BF_DOUT_CTP_60 : signal is "TRUE";
1870  --attribute IOB of BF_DOUT_CTP_61 : signal is "TRUE";
1871 
1872 
1873 
1874 
1875 
1876 
1877 
1878 
1879 
1880 Begin
1881 
1882  --safety setup
1883  BF_REQ_CTP_1_INPUT <= '0';
1884  BF_REQ_CTP_2_INPUT <= '0';
1885  BF_REQ_CABLE_1_INPUT<= '0';
1886  BF_REQ_CABLE_2_INPUT<= '0';
1887  BF_REQ_CABLE_3_INPUT<= '0';
1888  BF_LED_REQ_0 <= '0';
1889  BF_LED_REQ_1 <= '0';
1890  BF_LED_REQ_2 <= '0';
1891  BF_LED_REQ_3 <= '0';
1892  BF_LED_REQ_4 <= '0';
1893  --BF_TO_FROM_BSPT_0 <= '0';
1894  --BF_TO_FROM_BSPT_1 <= '0';
1895  BF_TO_FROM_BSPT_2 <= '0';
1896  BF_TO_FROM_BSPT_3 <= '0';
1897  BF_TO_FROM_BSPT_4 <= '0';
1898  BF_TO_FROM_BSPT_5 <= '0';
1899  BF_TO_FROM_BSPT_6 <= '0';
1900  BF_TO_FROM_BSPT_7 <= '0';
1901 
1902  --sdr_data_out_CTP1
1903  BF_DOUT_CTP_00 <= '0';--sdr_data_CTP(0)(0);
1904  BF_DOUT_CTP_01 <= '0';--sdr_data_CTP(0)(1);
1905  BF_DOUT_CTP_02 <= '0';--sdr_data_CTP(0)(2);
1906  BF_DOUT_CTP_03 <= '0';--sdr_data_CTP(0)(3);
1907  BF_DOUT_CTP_04 <= '0';--sdr_data_CTP(0)(4);
1908  BF_DOUT_CTP_05 <= '0';--sdr_data_CTP(0)(5);
1909  BF_DOUT_CTP_06 <= '0';--sdr_data_CTP(0)(6);
1910  BF_DOUT_CTP_07 <= '0';--sdr_data_CTP(0)(7);
1911  BF_DOUT_CTP_08 <= '0';--sdr_data_CTP(0)(8);
1912  BF_DOUT_CTP_09 <= '0';--sdr_data_CTP(0)(9);
1913  BF_DOUT_CTP_10 <= '0';--sdr_data_CTP(0)(10);
1914  BF_DOUT_CTP_11 <= '0';--sdr_data_CTP(0)(11);
1915  BF_DOUT_CTP_12 <= '0';--sdr_data_CTP(0)(12);
1916  BF_DOUT_CTP_13 <= '0';--sdr_data_CTP(0)(13);
1917  BF_DOUT_CTP_14 <= '0';--sdr_data_CTP(0)(14);
1918  BF_DOUT_CTP_15 <= '0';--sdr_data_CTP(0)(15);
1919  BF_DOUT_CTP_16 <= '0';--sdr_data_CTP(0)(16);
1920  BF_DOUT_CTP_17 <= '0';--sdr_data_CTP(0)(17);
1921  BF_DOUT_CTP_18 <= '0';--sdr_data_CTP(0)(18);
1922  BF_DOUT_CTP_19 <= '0';--sdr_data_CTP(0)(19);
1923  BF_DOUT_CTP_20 <= '0';--sdr_data_CTP(0)(20);
1924  BF_DOUT_CTP_21 <= '0';--sdr_data_CTP(0)(21);
1925  BF_DOUT_CTP_22 <= '0';--sdr_data_CTP(0)(22);
1926  BF_DOUT_CTP_23 <= '0';--sdr_data_CTP(0)(23);
1927  BF_DOUT_CTP_24 <= '0';--sdr_data_CTP(0)(24);
1928  BF_DOUT_CTP_25 <= '0';--sdr_data_CTP(0)(25);
1929  BF_DOUT_CTP_26 <= '0';--sdr_data_CTP(0)(26);
1930  BF_DOUT_CTP_27 <= '0';--sdr_data_CTP(0)(27);
1931  BF_DOUT_CTP_28 <= '0';--sdr_data_CTP(0)(28);
1932  BF_DOUT_CTP_29 <= '0';--sdr_data_CTP(0)(29);
1933  BF_DOUT_CTP_30 <= '0';--'0';
1934  BF_DOUT_CTP_64 <= '0';--sdr_data_CTP(0)(30);
1935  BF_DOUT_CTP_31 <= '0';--sdr_data_CTP(0)(31);
1936 
1937 
1938  BF_DOUT_CTP_32 <= '0';--sdr_data_CTP(1)(0);
1939  BF_DOUT_CTP_33 <= '0';--sdr_data_CTP(1)(1);
1940  BF_DOUT_CTP_34 <= '0';--sdr_data_CTP(1)(2);
1941  BF_DOUT_CTP_35 <= '0';--sdr_data_CTP(1)(3);
1942  BF_DOUT_CTP_36 <= '0';--sdr_data_CTP(1)(4);
1943  BF_DOUT_CTP_37 <= '0';--sdr_data_CTP(1)(5);
1944  BF_DOUT_CTP_38 <= '0';--sdr_data_CTP(1)(6);
1945  BF_DOUT_CTP_39 <= '0';--sdr_data_CTP(1)(7);
1946  BF_DOUT_CTP_40 <= '0';--sdr_data_CTP(1)(8);
1947  BF_DOUT_CTP_41 <= '0';--sdr_data_CTP(1)(9);
1948  BF_DOUT_CTP_42 <= '0';--sdr_data_CTP(1)(10);
1949  BF_DOUT_CTP_43 <= '0';--sdr_data_CTP(1)(11);
1950  BF_DOUT_CTP_44 <= '0';--sdr_data_CTP(1)(12);
1951  BF_DOUT_CTP_45 <= '0';--sdr_data_CTP(1)(13);
1952  BF_DOUT_CTP_46 <= '0';--sdr_data_CTP(1)(14);
1953  BF_DOUT_CTP_47 <= '0';--sdr_data_CTP(1)(15);
1954  BF_DOUT_CTP_48 <= '0';--sdr_data_CTP(1)(16);
1955  BF_DOUT_CTP_49 <= '0';--sdr_data_CTP(1)(17);
1956  BF_DOUT_CTP_50 <= '0';--sdr_data_CTP(1)(18);
1957  BF_DOUT_CTP_51 <= '0';--sdr_data_CTP(1)(19);
1958  BF_DOUT_CTP_52 <= '0';--sdr_data_CTP(1)(20);
1959  BF_DOUT_CTP_53 <= '0';--sdr_data_CTP(1)(21);
1960  BF_DOUT_CTP_54 <= '0';--sdr_data_CTP(1)(22);
1961  BF_DOUT_CTP_55 <= '0';--sdr_data_CTP(1)(23);
1962  BF_DOUT_CTP_56 <= '0';--sdr_data_CTP(1)(24);
1963  BF_DOUT_CTP_57 <= '0';--sdr_data_CTP(1)(25);
1964  BF_DOUT_CTP_58 <= '0';--sdr_data_CTP(1)(26);
1965  BF_DOUT_CTP_59 <= '0';--sdr_data_CTP(1)(27);
1966  BF_DOUT_CTP_60 <= '0';--sdr_data_CTP(1)(28);
1967  BF_DOUT_CTP_61 <= '0';--sdr_data_CTP(1)(29);
1968  BF_DOUT_CTP_62 <= '0';--'0';
1969  BF_DOUT_CTP_65 <= '0';--sdr_data_CTP(1)(30);
1970  BF_DOUT_CTP_63 <= '0';--sdr_data_CTP(1)(31);
1971 
1972 
1973 
1974 
1975 
1976 
1977 
1978 
1979  --ddr_data_in_CTP2(0) <=BF_DOUT_CTP_32;
1980  --ddr_data_in_CTP2(1) <=BF_DOUT_CTP_33;
1981  --ddr_data_in_CTP2(2) <=BF_DOUT_CTP_34;
1982  --ddr_data_in_CTP2(3) <=BF_DOUT_CTP_35;
1983  --ddr_data_in_CTP2(4) <=BF_DOUT_CTP_36;
1984  --ddr_data_in_CTP2(5) <=BF_DOUT_CTP_37;
1985  --ddr_data_in_CTP2(6) <=BF_DOUT_CTP_38;
1986  --ddr_data_in_CTP2(7) <=BF_DOUT_CTP_39;
1987  --ddr_data_in_CTP2(8) <=BF_DOUT_CTP_40;
1988  --ddr_data_in_CTP2(9) <=BF_DOUT_CTP_41;
1989  --ddr_data_in_CTP2(10) <=BF_DOUT_CTP_42;
1990  --ddr_data_in_CTP2(11) <=BF_DOUT_CTP_43;
1991  --ddr_data_in_CTP2(12) <=BF_DOUT_CTP_44;
1992  --ddr_data_in_CTP2(13) <=BF_DOUT_CTP_45;
1993  --ddr_data_in_CTP2(14) <=BF_DOUT_CTP_46;
1994  --ddr_data_in_CTP2(15) <=BF_DOUT_CTP_47;
1995  --ddr_data_in_CTP2(16) <=BF_DOUT_CTP_48;
1996  --ddr_data_in_CTP2(17) <=BF_DOUT_CTP_49;
1997  --ddr_data_in_CTP2(18) <=BF_DOUT_CTP_50;
1998  --ddr_data_in_CTP2(19) <=BF_DOUT_CTP_51;
1999  --ddr_data_in_CTP2(20) <=BF_DOUT_CTP_52;
2000  --ddr_data_in_CTP2(21) <=BF_DOUT_CTP_53;
2001  --ddr_data_in_CTP2(22) <=BF_DOUT_CTP_54;
2002  --ddr_data_in_CTP2(23) <=BF_DOUT_CTP_55;
2003  --ddr_data_in_CTP2(24) <=BF_DOUT_CTP_56;
2004  --ddr_data_in_CTP2(25) <=BF_DOUT_CTP_57;
2005  --ddr_data_in_CTP2(26) <=BF_DOUT_CTP_58;
2006  --ddr_data_in_CTP2(27) <=BF_DOUT_CTP_59;
2007  --ddr_data_in_CTP2(28) <=BF_DOUT_CTP_60;
2008  --ddr_data_in_CTP2(29) <=BF_DOUT_CTP_61;
2009  --ddr_data_in_CTP2(30) <=BF_DOUT_CTP_62;
2010  --ddr_data_in_CTP2(31) <=BF_DOUT_CTP_65;
2011  --ddr_data_in_CTP2(32) <=BF_DOUT_CTP_63;
2012 
2013 
2014  D_CBL_00_B <= ddr_data_out_RTM1(0);
2015  D_CBL_01_B <= ddr_data_out_RTM1(1);
2016  D_CBL_02_B <= ddr_data_out_RTM1(2);
2017  D_CBL_03_B <= ddr_data_out_RTM1(3);
2018  D_CBL_04_B <= ddr_data_out_RTM1(4);
2019  D_CBL_05_B <= ddr_data_out_RTM1(5);
2020  D_CBL_06_B <= ddr_data_out_RTM1(6);
2021  D_CBL_07_B <= ddr_data_out_RTM1(7);
2022  D_CBL_08_B <= ddr_data_out_RTM1(8);
2023  D_CBL_09_B <= ddr_data_out_RTM1(9);
2024  D_CBL_10_B <= ddr_data_out_RTM1(10);
2025  D_CBL_11_B <= ddr_data_out_RTM1(11);
2026  D_CBL_12_B <= ddr_data_out_RTM1(12);
2027  D_CBL_13_B <= ddr_data_out_RTM1(13);
2028  D_CBL_14_B <= ddr_data_out_RTM1(14);
2029  D_CBL_15_B <= ddr_data_out_RTM1(15);
2030  D_CBL_16_B <= ddr_data_out_RTM1(16);
2031  D_CBL_17_B <= ddr_data_out_RTM1(17);
2032  D_CBL_18_B <= ddr_data_out_RTM1(18);
2033  D_CBL_19_B <= ddr_data_out_RTM1(19);
2034  D_CBL_20_B <= ddr_data_out_RTM1(20);
2035  D_CBL_21_B <= ddr_data_out_RTM1(21);
2036  D_CBL_22_B <= ddr_data_out_RTM1(22);
2037  D_CBL_23_B <= ddr_data_out_RTM1(23);
2038  D_CBL_24_B <= ddr_data_out_RTM1(24);
2039  D_CBL_25_B <= ddr_data_out_RTM1(26);
2040  D_CBL_26_B <= ddr_data_out_RTM1(25);
2041  D_CBL_81_B <= '0';
2042 
2043  D_CBL_27_B <= ddr_data_out_RTM2(0);
2044  D_CBL_28_B <= ddr_data_out_RTM2(1);
2045  D_CBL_29_B <= ddr_data_out_RTM2(2);
2046  D_CBL_30_B <= ddr_data_out_RTM2(3);
2047  D_CBL_31_B <= ddr_data_out_RTM2(4);
2048  D_CBL_32_B <= ddr_data_out_RTM2(5);
2049  D_CBL_33_B <= ddr_data_out_RTM2(6);
2050  D_CBL_34_B <= ddr_data_out_RTM2(7);
2051  D_CBL_35_B <= ddr_data_out_RTM2(8);
2052  D_CBL_36_B <= ddr_data_out_RTM2(9);
2053  D_CBL_37_B <= ddr_data_out_RTM2(10);
2054  D_CBL_38_B <= ddr_data_out_RTM2(11);
2055  D_CBL_39_B <= ddr_data_out_RTM2(12);
2056  D_CBL_40_B <= ddr_data_out_RTM2(13);
2057  D_CBL_41_B <= ddr_data_out_RTM2(14);
2058  D_CBL_42_B <= ddr_data_out_RTM2(15);
2059  D_CBL_43_B <= ddr_data_out_RTM2(16);
2060  D_CBL_44_B <= ddr_data_out_RTM2(17);
2061  D_CBL_45_B <= ddr_data_out_RTM2(18);
2062  D_CBL_46_B <= ddr_data_out_RTM2(19);
2063  D_CBL_47_B <= ddr_data_out_RTM2(20);
2064  D_CBL_50_B <= ddr_data_out_RTM2(21);
2065  D_CBL_51_B <= ddr_data_out_RTM2(22);
2066  D_CBL_52_B <= ddr_data_out_RTM2(23);
2067  D_CBL_53_B <= ddr_data_out_RTM2(24);
2068  D_CBL_48_B <= ddr_data_out_RTM2(26);
2069  D_CBL_49_B <= ddr_data_out_RTM2(25);
2070  D_CBL_82_B <= '0';
2071 
2072  D_CBL_54_B <= '0';
2073  D_CBL_55_B <= '0';
2074  D_CBL_56_B <= '0';
2075  D_CBL_57_B <= '0';
2076  D_CBL_58_B <= '0';
2077  D_CBL_59_B <= '0';
2078  D_CBL_60_B <= '0';
2079  D_CBL_61_B <= '0';
2080  D_CBL_62_B <= '0';
2081  D_CBL_63_B <= '0';
2082  D_CBL_64_B <= '0';
2083  D_CBL_65_B <= '0';
2084  D_CBL_66_B <= '0';
2085  D_CBL_67_B <= '0';
2086  D_CBL_68_B <= '0';
2087  D_CBL_69_B <= '0';
2088  D_CBL_70_B <= '0';
2089  D_CBL_71_B <= '0';
2090  D_CBL_72_B <= '0';
2091  D_CBL_73_B <= '0';
2092  D_CBL_74_B <= '0';
2093  D_CBL_75_B <= '0';
2094  D_CBL_76_B <= '0';
2095  D_CBL_77_B <= '0';
2096  D_CBL_80_B <= '0';
2097  D_CBL_79_B <= '0';
2098  D_CBL_78_B <= '0';
2099  D_CBL_83_B <= '0';
2100 
2101 
2102  --backplane bus assignment
2103  P(0)(0) <= P0_0;
2104  P(0)(1) <= P0_1;
2105  P(0)(2) <= P0_2;
2106  P(0)(3) <= P0_3;
2107  P(0)(4) <= P0_4;
2108  P(0)(5) <= P0_5;
2109  P(0)(6) <= P0_6;
2110  P(0)(7) <= P0_7;
2111  P(0)(8) <= P0_8;
2112  P(0)(9) <= P0_9;
2113  P(0)(10) <= P0_10;
2114  P(0)(11) <= P0_11;
2115  P(0)(12) <= P0_12;
2116  P(0)(13) <= P0_13;
2117  P(0)(14) <= P0_14;
2118  P(0)(15) <= P0_15;
2119  P(0)(16) <= P0_16;
2120  P(0)(17) <= P0_17;
2121  P(0)(18) <= P0_18;
2122  P(0)(19) <= P0_19;
2123  P(0)(20) <= P0_20;
2124  P(0)(21) <= P0_21;
2125  P(0)(22) <= P0_22;
2126  P(0)(23) <= P0_23;
2127  P(0)(24) <= P0_24;
2128  P(1)(0) <= P1_0;
2129  P(1)(1) <= P1_1;
2130  P(1)(2) <= P1_2;
2131  P(1)(3) <= P1_3;
2132  P(1)(4) <= P1_4;
2133  P(1)(5) <= P1_5;
2134  P(1)(6) <= P1_6;
2135  P(1)(7) <= P1_7;
2136  P(1)(8) <= P1_8;
2137  P(1)(9) <= P1_9;
2138  P(1)(10) <= P1_10;
2139  P(1)(11) <= P1_11;
2140  P(1)(12) <= P1_12;
2141  P(1)(13) <= P1_13;
2142  P(1)(14) <= P1_14;
2143  P(1)(15) <= P1_15;
2144  P(1)(16) <= P1_16;
2145  P(1)(17) <= P1_17;
2146  P(1)(18) <= P1_18;
2147  P(1)(19) <= P1_19;
2148  P(1)(20) <= P1_20;
2149  P(1)(21) <= P1_21;
2150  P(1)(22) <= P1_22;
2151  P(1)(23) <= P1_23;
2152  P(1)(24) <= P1_24;
2153  P(2)(0) <= P2_0;
2154  P(2)(1) <= P2_1;
2155  P(2)(2) <= P2_2;
2156  P(2)(3) <= P2_3;
2157  P(2)(4) <= P2_4;
2158  P(2)(5) <= P2_5;
2159  P(2)(6) <= P2_6;
2160  P(2)(7) <= P2_7;
2161  P(2)(8) <= P2_8;
2162  P(2)(9) <= P2_9;
2163  P(2)(10) <= P2_10;
2164  P(2)(11) <= P2_11;
2165  P(2)(12) <= P2_12;
2166  P(2)(13) <= P2_13;
2167  P(2)(14) <= P2_14;
2168  P(2)(15) <= P2_15;
2169  P(2)(16) <= P2_16;
2170  P(2)(17) <= P2_17;
2171  P(2)(18) <= P2_18;
2172  P(2)(19) <= P2_19;
2173  P(2)(20) <= P2_20;
2174  P(2)(21) <= P2_21;
2175  P(2)(22) <= P2_22;
2176  P(2)(23) <= P2_23;
2177  P(2)(24) <= P2_24;
2178  P(3)(0) <= P3_0;
2179  P(3)(1) <= P3_1;
2180  P(3)(2) <= P3_2;
2181  P(3)(3) <= P3_3;
2182  P(3)(4) <= P3_4;
2183  P(3)(5) <= P3_5;
2184  P(3)(6) <= P3_6;
2185  P(3)(7) <= P3_7;
2186  P(3)(8) <= P3_8;
2187  P(3)(9) <= P3_9;
2188  P(3)(10) <= P3_10;
2189  P(3)(11) <= P3_11;
2190  P(3)(12) <= P3_12;
2191  P(3)(13) <= P3_13;
2192  P(3)(14) <= P3_14;
2193  P(3)(15) <= P3_15;
2194  P(3)(16) <= P3_16;
2195  P(3)(17) <= P3_17;
2196  P(3)(18) <= P3_18;
2197  P(3)(19) <= P3_19;
2198  P(3)(20) <= P3_20;
2199  P(3)(21) <= P3_21;
2200  P(3)(22) <= P3_22;
2201  P(3)(23) <= P3_23;
2202  P(3)(24) <= P3_24;
2203  P(4)(0) <= P4_0;
2204  P(4)(1) <= P4_1;
2205  P(4)(2) <= P4_2;
2206  P(4)(3) <= P4_3;
2207  P(4)(4) <= P4_4;
2208  P(4)(5) <= P4_5;
2209  P(4)(6) <= P4_6;
2210  P(4)(7) <= P4_7;
2211  P(4)(8) <= P4_8;
2212  P(4)(9) <= P4_9;
2213  P(4)(10) <= P4_10;
2214  P(4)(11) <= P4_11;
2215  P(4)(12) <= P4_12;
2216  P(4)(13) <= P4_13;
2217  P(4)(14) <= P4_14;
2218  P(4)(15) <= P4_15;
2219  P(4)(16) <= P4_16;
2220  P(4)(17) <= P4_17;
2221  P(4)(18) <= P4_18;
2222  P(4)(19) <= P4_19;
2223  P(4)(20) <= P4_20;
2224  P(4)(21) <= P4_21;
2225  P(4)(22) <= P4_22;
2226  P(4)(23) <= P4_23;
2227  P(4)(24) <= P4_24;
2228  P(5)(0) <= P5_0;
2229  P(5)(1) <= P5_1;
2230  P(5)(2) <= P5_2;
2231  P(5)(3) <= P5_3;
2232  P(5)(4) <= P5_4;
2233  P(5)(5) <= P5_5;
2234  P(5)(6) <= P5_6;
2235  P(5)(7) <= P5_7;
2236  P(5)(8) <= P5_8;
2237  P(5)(9) <= P5_9;
2238  P(5)(10) <= P5_10;
2239  P(5)(11) <= P5_11;
2240  P(5)(12) <= P5_12;
2241  P(5)(13) <= P5_13;
2242  P(5)(14) <= P5_14;
2243  P(5)(15) <= P5_15;
2244  P(5)(16) <= P5_16;
2245  P(5)(17) <= P5_17;
2246  P(5)(18) <= P5_18;
2247  P(5)(19) <= P5_19;
2248  P(5)(20) <= P5_20;
2249  P(5)(21) <= P5_21;
2250  P(5)(22) <= P5_22;
2251  P(5)(23) <= P5_23;
2252  P(5)(24) <= P5_24;
2253  P(6)(0) <= P6_0;
2254  P(6)(1) <= P6_1;
2255  P(6)(2) <= P6_2;
2256  P(6)(3) <= P6_3;
2257  P(6)(4) <= P6_4;
2258  P(6)(5) <= P6_5;
2259  P(6)(6) <= P6_6;
2260  P(6)(7) <= P6_7;
2261  P(6)(8) <= P6_8;
2262  P(6)(9) <= P6_9;
2263  P(6)(10) <= P6_10;
2264  P(6)(11) <= P6_11;
2265  P(6)(12) <= P6_12;
2266  P(6)(13) <= P6_13;
2267  P(6)(14) <= P6_14;
2268  P(6)(15) <= P6_15;
2269  P(6)(16) <= P6_16;
2270  P(6)(17) <= P6_17;
2271  P(6)(18) <= P6_18;
2272  P(6)(19) <= P6_19;
2273  P(6)(20) <= P6_20;
2274  P(6)(21) <= P6_21;
2275  P(6)(22) <= P6_22;
2276  P(6)(23) <= P6_23;
2277  P(6)(24) <= P6_24;
2278  P(7)(0) <= P7_0;
2279  P(7)(1) <= P7_1;
2280  P(7)(2) <= P7_2;
2281  P(7)(3) <= P7_3;
2282  P(7)(4) <= P7_4;
2283  P(7)(5) <= P7_5;
2284  P(7)(6) <= P7_6;
2285  P(7)(7) <= P7_7;
2286  P(7)(8) <= P7_8;
2287  P(7)(9) <= P7_9;
2288  P(7)(10) <= P7_10;
2289  P(7)(11) <= P7_11;
2290  P(7)(12) <= P7_12;
2291  P(7)(13) <= P7_13;
2292  P(7)(14) <= P7_14;
2293  P(7)(15) <= P7_15;
2294  P(7)(16) <= P7_16;
2295  P(7)(17) <= P7_17;
2296  P(7)(18) <= P7_18;
2297  P(7)(19) <= P7_19;
2298  P(7)(20) <= P7_20;
2299  P(7)(21) <= P7_21;
2300  P(7)(22) <= P7_22;
2301  P(7)(23) <= P7_23;
2302  P(7)(24) <= P7_24;
2303  P(8)(0) <= P8_0;
2304  P(8)(1) <= P8_1;
2305  P(8)(2) <= P8_2;
2306  P(8)(3) <= P8_3;
2307  P(8)(4) <= P8_4;
2308  P(8)(5) <= P8_5;
2309  P(8)(6) <= P8_6;
2310  P(8)(7) <= P8_7;
2311  P(8)(8) <= P8_8;
2312  P(8)(9) <= P8_9;
2313  P(8)(10) <= P8_10;
2314  P(8)(11) <= P8_11;
2315  P(8)(12) <= P8_12;
2316  P(8)(13) <= P8_13;
2317  P(8)(14) <= P8_14;
2318  P(8)(15) <= P8_15;
2319  P(8)(16) <= P8_16;
2320  P(8)(17) <= P8_17;
2321  P(8)(18) <= P8_18;
2322  P(8)(19) <= P8_19;
2323  P(8)(20) <= P8_20;
2324  P(8)(21) <= P8_21;
2325  P(8)(22) <= P8_22;
2326  P(8)(23) <= P8_23;
2327  P(8)(24) <= P8_24;
2328  P(9)(0) <= P9_0;
2329  P(9)(1) <= P9_1;
2330  P(9)(2) <= P9_2;
2331  P(9)(3) <= P9_3;
2332  P(9)(4) <= P9_4;
2333  P(9)(5) <= P9_5;
2334  P(9)(6) <= P9_6;
2335  P(9)(7) <= P9_7;
2336  P(9)(8) <= P9_8;
2337  P(9)(9) <= P9_9;
2338  P(9)(10) <= P9_10;
2339  P(9)(11) <= P9_11;
2340  P(9)(12) <= P9_12;
2341  P(9)(13) <= P9_13;
2342  P(9)(14) <= P9_14;
2343  P(9)(15) <= P9_15;
2344  P(9)(16) <= P9_16;
2345  P(9)(17) <= P9_17;
2346  P(9)(18) <= P9_18;
2347  P(9)(19) <= P9_19;
2348  P(9)(20) <= P9_20;
2349  P(9)(21) <= P9_21;
2350  P(9)(22) <= P9_22;
2351  P(9)(23) <= P9_23;
2352  P(9)(24) <= P9_24;
2353  P(10)(0) <= P10_0;
2354  P(10)(1) <= P10_1;
2355  P(10)(2) <= P10_2;
2356  P(10)(3) <= P10_3;
2357  P(10)(4) <= P10_4;
2358  P(10)(5) <= P10_5;
2359  P(10)(6) <= P10_6;
2360  P(10)(7) <= P10_7;
2361  P(10)(8) <= P10_8;
2362  P(10)(9) <= P10_9;
2363  P(10)(10) <= P10_10;
2364  P(10)(11) <= P10_11;
2365  P(10)(12) <= P10_12;
2366  P(10)(13) <= P10_13;
2367  P(10)(14) <= P10_14;
2368  P(10)(15) <= P10_15;
2369  P(10)(16) <= P10_16;
2370  P(10)(17) <= P10_17;
2371  P(10)(18) <= P10_18;
2372  P(10)(19) <= P10_19;
2373  P(10)(20) <= P10_20;
2374  P(10)(21) <= P10_21;
2375  P(10)(22) <= P10_22;
2376  P(10)(23) <= P10_23;
2377  P(10)(24) <= P10_24;
2378  P(11)(0) <= P11_0;
2379  P(11)(1) <= P11_1;
2380  P(11)(2) <= P11_2;
2381  P(11)(3) <= P11_3;
2382  P(11)(4) <= P11_4;
2383  P(11)(5) <= P11_5;
2384  P(11)(6) <= P11_6;
2385  P(11)(7) <= P11_7;
2386  P(11)(8) <= P11_8;
2387  P(11)(9) <= P11_9;
2388  P(11)(10) <= P11_10;
2389  P(11)(11) <= P11_11;
2390  P(11)(12) <= P11_12;
2391  P(11)(13) <= P11_13;
2392  P(11)(14) <= P11_14;
2393  P(11)(15) <= P11_15;
2394  P(11)(16) <= P11_16;
2395  P(11)(17) <= P11_17;
2396  P(11)(18) <= P11_18;
2397  P(11)(19) <= P11_19;
2398  P(11)(20) <= P11_20;
2399  P(11)(21) <= P11_21;
2400  P(11)(22) <= P11_22;
2401  P(11)(23) <= P11_23;
2402  P(11)(24) <= P11_24;
2403  P(12)(0) <= P12_0;
2404  P(12)(1) <= P12_1;
2405  P(12)(2) <= P12_2;
2406  P(12)(3) <= P12_3;
2407  P(12)(4) <= P12_4;
2408  P(12)(5) <= P12_5;
2409  P(12)(6) <= P12_6;
2410  P(12)(7) <= P12_7;
2411  P(12)(8) <= P12_8;
2412  P(12)(9) <= P12_9;
2413  P(12)(10) <= P12_10;
2414  P(12)(11) <= P12_11;
2415  P(12)(12) <= P12_12;
2416  P(12)(13) <= P12_13;
2417  P(12)(14) <= P12_14;
2418  P(12)(15) <= P12_15;
2419  P(12)(16) <= P12_16;
2420  P(12)(17) <= P12_17;
2421  P(12)(18) <= P12_18;
2422  P(12)(19) <= P12_19;
2423  P(12)(20) <= P12_20;
2424  P(12)(21) <= P12_21;
2425  P(12)(22) <= P12_22;
2426  P(12)(23) <= P12_23;
2427  P(12)(24) <= P12_24;
2428  P(13)(0) <= P13_0;
2429  P(13)(1) <= P13_1;
2430  P(13)(2) <= P13_2;
2431  P(13)(3) <= P13_3;
2432  P(13)(4) <= P13_4;
2433  P(13)(5) <= P13_5;
2434  P(13)(6) <= P13_6;
2435  P(13)(7) <= P13_7;
2436  P(13)(8) <= P13_8;
2437  P(13)(9) <= P13_9;
2438  P(13)(10) <= P13_10;
2439  P(13)(11) <= P13_11;
2440  P(13)(12) <= P13_12;
2441  P(13)(13) <= P13_13;
2442  P(13)(14) <= P13_14;
2443  P(13)(15) <= P13_15;
2444  P(13)(16) <= P13_16;
2445  P(13)(17) <= P13_17;
2446  P(13)(18) <= P13_18;
2447  P(13)(19) <= P13_19;
2448  P(13)(20) <= P13_20;
2449  P(13)(21) <= P13_21;
2450  P(13)(22) <= P13_22;
2451  P(13)(23) <= P13_23;
2452  P(13)(24) <= P13_24;
2453  P(14)(0) <= P14_0;
2454  P(14)(1) <= P14_1;
2455  P(14)(2) <= P14_2;
2456  P(14)(3) <= P14_3;
2457  P(14)(4) <= P14_4;
2458  P(14)(5) <= P14_5;
2459  P(14)(6) <= P14_6;
2460  P(14)(7) <= P14_7;
2461  P(14)(8) <= P14_8;
2462  P(14)(9) <= P14_9;
2463  P(14)(10) <= P14_10;
2464  P(14)(11) <= P14_11;
2465  P(14)(12) <= P14_12;
2466  P(14)(13) <= P14_13;
2467  P(14)(14) <= P14_14;
2468  P(14)(15) <= P14_15;
2469  P(14)(16) <= P14_16;
2470  P(14)(17) <= P14_17;
2471  P(14)(18) <= P14_18;
2472  P(14)(19) <= P14_19;
2473  P(14)(20) <= P14_20;
2474  P(14)(21) <= P14_21;
2475  P(14)(22) <= P14_22;
2476  P(14)(23) <= P14_23;
2477  P(14)(24) <= P14_24;
2478  P(15)(0) <= P15_0;
2479  P(15)(1) <= P15_1;
2480  P(15)(2) <= P15_2;
2481  P(15)(3) <= P15_3;
2482  P(15)(4) <= P15_4;
2483  P(15)(5) <= P15_5;
2484  P(15)(6) <= P15_6;
2485  P(15)(7) <= P15_7;
2486  P(15)(8) <= P15_8;
2487  P(15)(9) <= P15_9;
2488  P(15)(10) <= P15_10;
2489  P(15)(11) <= P15_11;
2490  P(15)(12) <= P15_12;
2491  P(15)(13) <= P15_13;
2492  P(15)(14) <= P15_14;
2493  P(15)(15) <= P15_15;
2494  P(15)(16) <= P15_16;
2495  P(15)(17) <= P15_17;
2496  P(15)(18) <= P15_18;
2497  P(15)(19) <= P15_19;
2498  P(15)(20) <= P15_20;
2499  P(15)(21) <= P15_21;
2500  P(15)(22) <= P15_22;
2501  P(15)(23) <= P15_23;
2502  P(15)(24) <= P15_24;
2503 
2504 
2505 
2506  MP1_F01_QUAD_110_TRN_0_DIR <= TXP_OUT(0) ;
2507  MP1_F01_QUAD_110_TRN_0_CMP <= TXN_OUT(0) ;
2508  MP1_F03_QUAD_110_TRN_1_DIR <= TXP_OUT(1) ;
2509  MP1_F03_QUAD_110_TRN_1_CMP <= TXN_OUT(1) ;
2510  MP1_F07_QUAD_110_TRN_2_DIR <= TXP_OUT(2) ;
2511  MP1_F07_QUAD_110_TRN_2_CMP <= TXN_OUT(2) ;
2512  MP1_F05_QUAD_110_TRN_3_DIR <= TXP_OUT(3) ;
2513  MP1_F05_QUAD_110_TRN_3_CMP <= TXN_OUT(3) ;
2514  MP1_F09_QUAD_111_TRN_0_DIR <= TXP_OUT(4) ;
2515  MP1_F09_QUAD_111_TRN_0_CMP <= TXN_OUT(4) ;
2516  MP1_F11_QUAD_111_TRN_1_DIR <= TXP_OUT(5) ;
2517  MP1_F11_QUAD_111_TRN_1_CMP <= TXN_OUT(5) ;
2518  MP1_F10_QUAD_111_TRN_2_DIR <= TXP_OUT(6) ;
2519  MP1_F10_QUAD_111_TRN_2_CMP <= TXN_OUT(6) ;
2520  MP1_F08_QUAD_111_TRN_3_DIR <= TXP_OUT(7) ;
2521  MP1_F08_QUAD_111_TRN_3_CMP <= TXN_OUT(7) ;
2522  MP1_F04_QUAD_112_TRN_0_DIR <= TXP_OUT(8) ;
2523  MP1_F04_QUAD_112_TRN_0_CMP <= TXN_OUT(8) ;
2524  MP1_F06_QUAD_112_TRN_1_DIR <= TXP_OUT(9) ;
2525  MP1_F06_QUAD_112_TRN_1_CMP <= TXN_OUT(9) ;
2526  MP1_F02_QUAD_112_TRN_2_DIR <= TXP_OUT(10) ;
2527  MP1_F02_QUAD_112_TRN_2_CMP <= TXN_OUT(10) ;
2528  MP1_F00_QUAD_112_TRN_3_DIR <= TXP_OUT(11) ;
2529  MP1_F00_QUAD_112_TRN_3_CMP <= TXN_OUT(11) ;
2530  MP2_F01_QUAD_113_TRN_0_DIR <= TXP_OUT(12) ;
2531  MP2_F01_QUAD_113_TRN_0_CMP <= TXN_OUT(12) ;
2532  MP2_F03_QUAD_113_TRN_1_DIR <= TXP_OUT(13) ;
2533  MP2_F03_QUAD_113_TRN_1_CMP <= TXN_OUT(13) ;
2534  MP2_F07_QUAD_113_TRN_2_DIR <= TXP_OUT(14) ;
2535  MP2_F07_QUAD_113_TRN_2_CMP <= TXN_OUT(14) ;
2536  MP2_F05_QUAD_113_TRN_3_DIR <= TXP_OUT(15) ;
2537  MP2_F05_QUAD_113_TRN_3_CMP <= TXN_OUT(15) ;
2538  MP2_F09_QUAD_114_TRN_0_DIR <= TXP_OUT(16) ;
2539  MP2_F09_QUAD_114_TRN_0_CMP <= TXN_OUT(16) ;
2540  MP2_F11_QUAD_114_TRN_1_DIR <= TXP_OUT(17) ;
2541  MP2_F11_QUAD_114_TRN_1_CMP <= TXN_OUT(17) ;
2542  MP2_F10_QUAD_114_TRN_2_DIR <= TXP_OUT(18) ;
2543  MP2_F10_QUAD_114_TRN_2_CMP <= TXN_OUT(18) ;
2544  MP2_F08_QUAD_114_TRN_3_DIR <= TXP_OUT(19) ;
2545  MP2_F08_QUAD_114_TRN_3_CMP <= TXN_OUT(19) ;
2546  MP2_F04_QUAD_115_TRN_0_DIR <= TXP_OUT(20) ;
2547  MP2_F04_QUAD_115_TRN_0_CMP <= TXN_OUT(20) ;
2548  MP2_F06_QUAD_115_TRN_1_DIR <= TXP_OUT(21) ;
2549  MP2_F06_QUAD_115_TRN_1_CMP <= TXN_OUT(21) ;
2550  MP2_F02_QUAD_115_TRN_2_DIR <= TXP_OUT(22) ;
2551  MP2_F02_QUAD_115_TRN_2_CMP <= TXN_OUT(22) ;
2552  MP2_F00_QUAD_115_TRN_3_DIR <= TXP_OUT(23) ;
2553  MP2_F00_QUAD_115_TRN_3_CMP <= TXN_OUT(23) ;
2554 
2555  MGTREFCLK_PAD_P_IN(0) <= CLK_320MHz64_LHC_BF_QUAD_111_DIR;
2556  MGTREFCLK_PAD_N_IN(0) <= CLK_320MHz64_LHC_BF_QUAD_111_CMP;
2557  MGTREFCLK_PAD_P_IN(1) <= CLK_320MHz64_LHC_BF_QUAD_114_DIR;
2558  MGTREFCLK_PAD_N_IN(1) <= CLK_320MHz64_LHC_BF_QUAD_114_CMP;
2559 
2560 
2561 
2562  --debug pins bus assignment
2563  BF_DEBUG_0 <= BF_DEBUG(0);
2564  BF_DEBUG_1 <= BF_DEBUG(1);
2565  BF_DEBUG_2 <= BF_DEBUG(2);
2566  BF_DEBUG_3 <= BF_DEBUG(3);
2567  BF_DEBUG_4 <= BF_DEBUG(4);
2568  BF_DEBUG_5 <= BF_DEBUG(5);
2569  BF_DEBUG_6 <= BF_DEBUG(6);
2570  BF_DEBUG_7 <= BF_DEBUG(7);
2571  BF_DEBUG_8 <= BF_DEBUG(8);
2572  BF_DEBUG_9 <= BF_DEBUG(9);
2573 
2574  --BF_DEBUG(8) <= buf_clk40;
2575 
2576  ODDR_inst_buf_clk_40 : ODDR
2577  generic map(
2578  DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
2579  INIT => '0', -- Initial value for Q port ('1' or '0')
2580  SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
2581  port map (
2582  Q => BF_DEBUG(8), -- 1-bit DDR output
2583  C => buf_clk40, -- 1-bit clock input
2584  CE => '1', -- 1-bit clock enable input
2585  D1 => '1', -- 1-bit data input (positive edge)
2586  D2 => '0', -- 1-bit data input (negative edge)
2587  R => (not pll_locked), -- 1-bit reset input
2588  S => '0' -- 1-bit set input
2589  );
2590 
2591  BF_DEBUG(9) <= DATA96(5)(0);--start_playback;--BF_TO_TP_DAQ_SLINK_RETURN_DIR;--send_align(0);-- BUF_TTC_BNCH_CNT_RES; --bunch counter reset
2592 
2593  BF_DEBUG(7 downto 0)<=(others=>'0');
2594 
2595  vme_address(1) <= OCB_A01;
2596  vme_address(2) <= OCB_A02;
2597  vme_address(3) <= OCB_A03;
2598  vme_address(4) <= OCB_A04;
2599  vme_address(5) <= OCB_A05;
2600  vme_address(6) <= OCB_A06;
2601  vme_address(7) <= OCB_A07;
2602  vme_address(8) <= OCB_A08;
2603  vme_address(9) <= OCB_A09;
2604  vme_address(10) <= OCB_A10;
2605  vme_address(11) <= OCB_A11;
2606  vme_address(12) <= OCB_A12;
2607  vme_address(13) <= OCB_A13;
2608  vme_address(14) <= OCB_A14;
2609  vme_address(15) <= OCB_A15;
2610  vme_address(16) <= OCB_A16;
2611  vme_address(17) <= OCB_A17;
2612  vme_address(18) <= OCB_A18;
2613  vme_address(19) <= OCB_A19;
2614  vme_address(20) <= OCB_A20;
2615  vme_address(21) <= OCB_A21;
2616  vme_address(22) <= OCB_A22;
2617  vme_address(23) <= OCB_A23;
2618 
2619  ------------------------------------------------------------------------------
2620  -- VME interface component used in BSPT FPGA (Ian's vme_interface)
2621  ------------------------------------------------------------------------------
2622  CMX_BASE_VMEIF_BSPT : CMX_BASE_VME_BSPT
2623  port map (
2624  ----------------------------------------------------------------------------
2625  -- inputs
2626  ----------------------------------------------------------------------------
2627  clk40 => buf_clk40 ,
2628  geoadd_0 => OCB_GEO_ADRS_0 ,
2629  n_ds0_int => OCB_DS_B,
2630  n_write => OCB_WRITE_B ,
2631  -- vme_address
2632  vme_address => vme_address,
2633  ----------------------------------------------------------------------------
2634  -- outputs
2635  ----------------------------------------------------------------------------
2636  board_ds => ds, -- board_ds output from VME (Ian model)
2637  brdsel_n => ncs -- brdsel_n output from VME (Ian model)
2638  );
2639 
2640 
2641  vme_main_hub_inst: entity work.vme_main_hub
2642  port map (
2643  data_vme => OCB_D,
2644  data_vme_from_below => data_vme_up_top,
2645  bus_drive_from_below => bus_drive_up_top ,
2646  data_vme_going_below => data_vme_going_below);
2647 
2648 
2649  vme_local_switch_inst: entity work.vme_local_switch
2650  port map (
2651  data_vme_up => data_vme_up_top,
2652  data_vme_from_below => data_vme_from_below_top ,
2653  bus_drive_up => bus_drive_up_top ,
2654  bus_drive_from_below => bus_drive_from_below_top );
2655 
2656  CMX_version_inst: entity work.CMX_version
2657  port map (
2658  clk40 => buf_clk40 ,
2659  ncs => ncs,
2660  rd_nwr => OCB_WRITE_B ,
2661  ds => ds,
2662  addr_vme => vme_address(16 downto 1),
2663  data_vme_out => data_vme_from_below_top(1605),
2664  bus_drive => bus_drive_from_below_top (1605));
2665 
2666 
2667 
2668  sys_monitor_inst: entity work.sys_monitor
2669  generic map (
2670  ADDR_REG_RO_SYSMON_DATA_BLOCK => ADDR_REG_RO_SYSMON_DATA_BLOCK)
2671  port map (
2672  clk => buf_clk40 ,
2673  BF_SYSMON_01_P => BF_SYSMON_01_P,
2674  BF_SYSMON_01_N => BF_SYSMON_01_N,
2675  BF_SYSMON_03_P => BF_SYSMON_03_P,
2676  BF_SYSMON_03_N => BF_SYSMON_03_N,
2677  BF_SYSMON_04_P => BF_SYSMON_04_P,
2678  BF_SYSMON_04_N => BF_SYSMON_04_N,
2679  BF_SYSMON_07_P => BF_SYSMON_07_P,
2680  BF_SYSMON_07_N => BF_SYSMON_07_N,
2681  BF_SYSMON_08_P => BF_SYSMON_08_P,
2682  BF_SYSMON_08_N => BF_SYSMON_08_N,
2683  BF_SYSMON_09_P => BF_SYSMON_09_P,
2684  BF_SYSMON_09_N => BF_SYSMON_09_N,
2685  BF_SYSMON_10_P => BF_SYSMON_10_P,
2686  BF_SYSMON_10_N => BF_SYSMON_10_N,
2687  BF_SYSMON_11_P => BF_SYSMON_11_P,
2688  BF_SYSMON_11_N => BF_SYSMON_11_N,
2689  BF_SYSMON_12_P => BF_SYSMON_12_P,
2690  BF_SYSMON_12_N => BF_SYSMON_12_N,
2691  BF_SYSMON_13_P => BF_SYSMON_13_P,
2692  BF_SYSMON_13_N => BF_SYSMON_13_N,
2693  BF_SYSMON_14_P => BF_SYSMON_14_P,
2694  BF_SYSMON_14_N => BF_SYSMON_14_N,
2695  BF_SYSMON_15_P => BF_SYSMON_15_P,
2696  BF_SYSMON_15_N => BF_SYSMON_15_N,
2697  ncs => ncs,
2698  rd_nwr => OCB_WRITE_B ,
2699  ds => ds,
2700  addr_vme => vme_address(16 downto 1),
2701  data_vme_in => data_vme_going_below ,
2702  data_vme_out => data_vme_from_below_top (1760),
2703  bus_drive => bus_drive_from_below_top (1760));
2704 
2705 
2706  process(buf_clk40)
2707  begin
2708  if rising_edge(buf_clk40) then
2709  if (read_detect_inreg_test='1' or write_detect_inreg_test='1') and read_detect_outreg_test='0' then
2710  test_rw_counter<=test_rw_counter+1;
2711  elsif read_detect_outreg_test='1' then
2712  test_rw_counter<=test_rw_counter-1;
2713  end if;
2714  end if;
2715  end process;
2716 
2717  data_to_vme_test_r<=std_logic_vector(test_rw_counter);
2718 
2719 
2720  vme_outreg_notri_test: entity work.vme_outreg_notri
2721  generic map (
2722  ia_vme => ADDR_REG_RO_test ,
2723  width => 16)
2724  port map (
2725  clk => buf_clk40 ,
2726  ncs => ncs,
2727  rd_nwr => OCB_WRITE_B ,
2728  ds => ds,
2729  addr_vme => vme_address(16 downto 1),
2730  data_vme => data_vme_from_below_top (1600),
2731  bus_drive => bus_drive_from_below_top (1600),
2732  data_to_vme => data_to_vme_test_r ,
2733  read_detect => read_detect_outreg_test);
2734 
2735  --vme_outreg_test: vme_outreg
2736  -- generic map (
2737  -- ia_vme => ADDR_REG_RO_test,
2738  -- width => 16)
2739  -- port map (
2740  -- clk => buf_clk40,
2741  -- addr_vme => vme_address(16 downto 1),
2742  -- ncs => ncs,
2743  -- rd_nwr => OCB_WRITE_B,
2744  -- ds => ds,
2745  -- data_to_vme => data_to_vme_test_r,
2746  -- read_detect => read_detect_outreg_test,
2747  -- data_vme => OCB_D);
2748 
2749 
2750  vme_inreg_notri_test: entity work.vme_inreg_notri
2751  generic map (
2752  ia_vme => ADDR_REG_RW_test ,
2753  width => 16)
2754  port map (
2755  clk => buf_clk40 ,
2756  ncs => ncs,
2757  rd_nwr => OCB_WRITE_B ,
2758  ds => ds,
2759  addr_vme => vme_address(16 downto 1),
2760  data_vme_in => data_vme_going_below ,
2761  data_vme_out => data_vme_from_below_top (1601),
2762  bus_drive => bus_drive_from_below_top (1601),
2763  data_from_vme => data_from_vme_test_rw ,
2764  data_to_vme => data_to_vme_test_rw ,
2765  read_detect => read_detect_inreg_test,
2766  write_detect => write_detect_inreg_test );
2767 
2768  --vme_inreg_test: vme_inreg
2769  -- generic map (
2770  -- ia_vme => ADDR_REG_RW_test,
2771  -- width => 16)
2772  -- port map (
2773  -- clk => buf_clk40,
2774  -- ncs => ncs,
2775  -- rd_nwr => OCB_WRITE_B,
2776  -- ds => ds,
2777  -- data_from_vme => data_from_vme_test_rw,
2778  -- data_to_vme => data_to_vme_test_rw,
2779  -- addr_vme => vme_address(16 downto 1),
2780  -- read_detect => read_detect_inreg_test,
2781  -- write_detect => write_detect_inreg_test,
2782  -- data_vme => OCB_D);
2783  --
2784  data_to_vme_test_rw<=(data_from_vme_test_rw or data_to_vme_test_r);
2785 
2786 
2787 
2788  --chipscope_icon_u2_c3_inst: chipscope_icon_u2_c3
2789  -- port map (
2790  -- CONTROL0 => CONTROL0,
2791  -- CONTROL1 => CONTROL1,
2792  -- CONTROL2 => CONTROL2
2793  -- );
2794 
2795  --WTF NO CS 20141128
2796  --WTF NO CS 20141128 chipscope_ila_CMX_top_inputmodclk_inst: chipscope_ila_CMX_top_inputmodclk
2797  --WTF NO CS 20141128 port map (
2798  --WTF NO CS 20141128 CONTROL => CONTROL0,
2799  --WTF NO CS 20141128 CLK => buf_clk40,
2800  --WTF NO CS 20141128 DATA => DATA_chipscope_ila_CMX_top_inputmodclk,
2801  --WTF NO CS 20141128 TRIG0 => TRIG0_chipscope_ila_CMX_top_inputmodclk);
2802  --WTF NO CS 20141128
2803  --WTF NO CS 20141128
2804  --WTF NO CS 20141128 TRIG0_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2805  --WTF NO CS 20141128 TRIG0_chipscope_ila_CMX_top_inputmodclk(33)<=start_playback;
2806  --WTF NO CS 20141128 TRIG0_chipscope_ila_CMX_top_inputmodclk(34)<='0';
2807  --WTF NO CS 20141128 TRIG0_chipscope_ila_CMX_top_inputmodclk(35)<=data_to_RTM(0);
2808  --WTF NO CS 20141128
2809  --WTF NO CS 20141128
2810  --WTF NO CS 20141128 DATA_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2811  --WTF NO CS 20141128
2812  --WTF NO CS 20141128 gen_data_chipscope_ila: for ichannel in numactchan-1 downto 0 generate
2813  --WTF NO CS 20141128
2814  --WTF NO CS 20141128 TRIG0_chipscope_ila_CMX_top_inputmodclk(1+ichannel*2)<=PAR_ERROR(ichannel);
2815  --WTF NO CS 20141128 TRIG0_chipscope_ila_CMX_top_inputmodclk(2+ichannel*2)<=counter_enable_inputmod_sig(ichannel);
2816  --WTF NO CS 20141128
2817  --WTF NO CS 20141128 DATA_chipscope_ila_CMX_top_inputmodclk(1+ichannel*98)<=PAR_ERROR(ichannel);
2818  --WTF NO CS 20141128 DATA_chipscope_ila_CMX_top_inputmodclk(2+ichannel*98)<=counter_enable_inputmod_sig(ichannel);
2819  --WTF NO CS 20141128 DATA_chipscope_ila_CMX_top_inputmodclk(95+3+ichannel*98 downto 3+ichannel*98)<=DATA96(ichannel);
2820  --WTF NO CS 20141128
2821  --WTF NO CS 20141128 end generate gen_data_chipscope_ila;
2822  --WTF NO CS 20141128
2823  --WTF NO CS 20141128 DATA_chipscope_ila_CMX_top_inputmodclk(1630 downto 1569)<=(others=>'0');
2824  --WTF NO CS 20141128 DATA_chipscope_ila_CMX_top_inputmodclk(1734 downto 1631)<=data_to_RTM;
2825  --WTF NO CS 20141128 DATA_chipscope_ila_CMX_top_inputmodclk(1735)<=start_playback;
2826  --WTF NO CS 20141128 DATA_chipscope_ila_CMX_top_inputmodclk(2375 downto 1736)<=tot_Et2;
2827 
2828 
2829  CMX_delay_generator_inst: CMX_delay_generator
2830  generic map (
2831  start_address => ADDR_REG_RW_IDELAY_BACKPLANE )
2832  port map (
2833  clk40 => buf_clk40 ,
2834  ncs => ncs,
2835  rd_nwr => OCB_WRITE_B ,
2836  ds => ds,
2837  addr_vme => vme_address(16 downto 1),
2838  data_vme_in => data_vme_going_below ,
2839  data_vme_out => data_vme_from_below_top (1602),
2840  bus_drive => bus_drive_from_below_top (1602),
2841  del_register => del_register,
2842  upload_delays => upload_delays);
2843 
2844  --upload_delays<='0';
2845  --del_register<=(others=>(others=>(others=>'0')));
2846 
2847  BCID_counter_inst: BCID_counter
2848  port map (
2849  reset => bc_reset_synced ,
2850  clk_40 => buf_clk40,
2851  BCID_out => BCID_counter_sig ,
2852  ncs => ncs,
2853  rd_nwr => OCB_WRITE_B ,
2854  ds => ds,
2855  addr_vme => vme_address(16 downto 1),
2856  data_vme_in => data_vme_going_below ,
2857  data_vme_out => data_vme_from_below_top (1639),
2858  bus_drive => bus_drive_from_below_top (1639));
2859 
2860 
2861 
2862  process(buf_clk40)
2863  begin
2864  if rising_edge(buf_clk40) then
2865  start_playback<=start_playback_r1;
2866  start_playback_r1<=BF_TO_FROM_BSPT_0;
2867  end if;
2868  end process;
2869 
2870  CMX_input_inst: CMX_input_module
2871  port map (
2872  P => P,
2873  buf_clk40 => buf_clk40,
2874  buf_clk40_m180o => buf_clk40_m180o,
2875  buf_clk200 => buf_clk200,
2876  pll_locked => pll_locked,
2877  ODATA => DATA96,
2878  ODATA_first_half => ODATA_first_half ,
2879  --ODATA_WORD0 => open,
2880  PAR_ERROR_total => par_err(0),
2881  counter_enable_out => counter_enable_inputmod_sig ,
2882  counter_values => counter_values,
2883  del_register => del_register,
2884  upload_delays => upload_delays,
2885  quiet => quiet,
2886  start_playback => start_playback,
2887  spy_write_inhibit => spy_write_inhibit ,
2888  ncs => ncs,
2889  rd_nwr => OCB_WRITE_B,
2890  ds => ds,
2891  addr_vme => vme_address(16 downto 1),
2892  data_vme_in => data_vme_going_below ,
2893  data_vme_out => data_vme_from_below_top (1603),
2894  bus_drive => bus_drive_from_below_top (1603));
2895 
2896  par_err(1)<='0';
2897 
2898  vme_inreg_async_REG_RW_QUIET_FORCE : vme_inreg_notri_async
2899  generic map (
2900  ia_vme => ADDR_REG_RW_QUIET_FORCE ,
2901  width => 16)
2902  port map (
2903  ncs => ncs,
2904  rd_nwr => OCB_WRITE_B,
2905  ds => ds,
2906  addr_vme => vme_address(16 downto 1),
2907  data_vme_in => data_vme_going_below,
2908  data_vme_out => data_vme_from_below_top(1630),
2909  bus_drive => bus_drive_from_below_top (1630),
2910  data_from_vme => data_from_vme_REG_RW_QUIET_FORCE,
2911  data_to_vme => data_to_vme_REG_RW_QUIET_FORCE);
2912 
2913  data_to_vme_REG_RW_QUIET_FORCE<=data_from_vme_REG_RW_QUIET_FORCE;
2914  quiet<=data_from_vme_REG_RW_QUIET_FORCE(1);
2915  force<=data_from_vme_REG_RW_QUIET_FORCE(0);
2916 
2917 
2918  CMX_Memory_spy_inhibit_inst: entity work.CMX_Memory_spy_inhibit
2919  port map (
2920  spy_write_inhibit => spy_write_inhibit ,
2921  buf_clk40 => buf_clk40,
2922  ncs => ncs,
2923  rd_nwr => OCB_WRITE_B,
2924  ds => ds,
2925  addr_vme => vme_address(16 downto 1),
2926  data_vme_in => data_vme_going_below,
2927  data_vme_out => data_vme_from_below_top(1761),
2928  bus_drive => bus_drive_from_below_top (1761));
2929 
2930 
2931  gen_REG_RW_JET_THRESHOLD_BLOCK: for i_thr in 1599 downto 0 generate
2932 
2933  vme_inreg_notri_async_REG_RW_JET_THRESHOLD_BLOCK: entity work.vme_inreg_notri_async
2934  generic map (
2935  ia_vme => ADDR_REG_RW_JET_THRESHOLD_BLOCK+2*i_thr,
2936  width => 16)
2937  port map (
2938  ncs => ncs,
2939  rd_nwr => OCB_WRITE_B,
2940  ds => ds,
2941  addr_vme => vme_address(16 downto 1),
2942  data_vme_in => data_vme_going_below,
2943  data_vme_out => data_vme_from_below_top (i_thr),
2944  bus_drive => bus_drive_from_below_top (i_thr),
2945  data_from_vme => data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr),
2946  data_to_vme => data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr));
2947 
2948 
2949  --vme_inreg_async_REG_RW_JET_THRESHOLD_BLOCK: vme_inreg_async
2950  -- generic map (
2951  -- ia_vme => ADDR_REG_RW_JET_THRESHOLD_BLOCK+2*i_thr,
2952  -- width => 16)
2953  -- port map (
2954  -- ncs => ncs,
2955  -- rd_nwr => OCB_WRITE_B,
2956  -- ds => ds,
2957  -- addr_vme => vme_address(16 downto 1),
2958  -- data_vme => OCB_D,
2959  -- data_from_vme => data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr),
2960  -- data_to_vme => data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr));
2961  --
2962  data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr)<=data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr);
2963  end generate gen_REG_RW_JET_THRESHOLD_BLOCK;
2964 
2965  thresholds<=data_from_vme_REG_RW_JET_THRESHOLD_BLOCK;
2966 
2967  decoder_inst: decoder
2968  generic map (
2969  max_tobs_tot => max_tobs_tot,
2970  max_tobs_topo => max_tobs_topo,
2971  max_jems => max_jems,
2972  max_tobs_pjem => max_tobs_pjem,
2973  et2_width => et2_width,
2974  et1_width => et1_width,
2975  pos_width => pos_width,
2976  thresholds_num => thresholds_num,
2977  thresholds_width => thresholds_width)
2978  port map (
2979  clk40MHz => buf_clk40,
2980  clk40MHz_m90o => buf_clk40_m90o,
2981  clk40MHz_90o => buf_clk40_90o,
2982  clk40MHz_m180o => buf_clk40_m180o,
2983  pll_locked => pll_locked,
2984  datai => DATA96,
2985  datai_first_half =>ODATA_first_half,
2986  Tobs_to_TOPO => Tobs_to_TOPO,
2987  overflow => overflow,
2988  BCID_in => BCID_counter_sig ,
2989  BCID_delayed => BCID_delayed_decoder ,
2990  counter_inhibit => counter_inhibit,
2991  counter_reset => counter_reset,
2992  ncs => ncs,
2993  rd_nwr => OCB_WRITE_B ,
2994  ds => ds,
2995  addr_vme => vme_address(16 downto 1),
2996  data_vme_out => data_vme_from_below_top (1638),
2997  bus_drive => bus_drive_from_below_top (1638));
2998 
2999 
3000 
3001  adder_top_inst: entity work.adder_top
3002  generic map (
3003  numactchan => numactchan,
3004  ADDR_REG_RW_PIPELINE_DELAY_LENGTH => ADDR_REG_RW_DELAY_INPUT_DATA_ADDER,
3005  gen_system => '0'
3006  )
3007  port map (
3008  clk => buf_clk40 ,
3009  thresholds => thresholds,
3010  datai => DATA96,
3011  din_cbl => din_cbl,
3012  din_cbl_ro => '0',
3013  dout_lcl => dout_lcl,
3014  dout_lcl_ro => dout_lcl_ro,
3015  dout => open,--dout,
3016  dout_cbla_mux0 => dout_cbla_mux0,
3017  dout_cbla_mux1 => dout_cbla_mux1,
3018  dout_cblb_mux0 => dout_cblb_mux0,
3019  dout_cblb_mux1 => dout_cblb_mux1,
3020  --VME control:
3021  ncs => ncs,
3022  rd_nwr => OCB_WRITE_B ,
3023  ds => ds,
3024  addr_vme => vme_address(16 downto 1),
3025  data_vme_in => data_vme_going_below ,
3026  data_vme_out => data_vme_from_below_top (1606),
3027  bus_drive => bus_drive_from_below_top (1606),
3028  par_err => par_err,
3029  force => force,
3030  reset => counter_reset ,
3031  inhibit => counter_inhibit
3032  );
3033 
3034  din_cbl<="01111" & x"000000000000000"; --nothing coming 'remote', add dummy odd parity bits
3035 
3036  data_to_RTM1(14 downto 0) <= dout_cbla_mux0(14 downto 0);
3037  data_to_RTM1(40 downto 26) <= dout_cbla_mux1(14 downto 0);
3038  data_to_RTM1(25)<=dout_cbla_mux0(32);
3039  data_to_RTM1(51)<=dout_cbla_mux1(32);
3040  data_to_RTM1(24 downto 15)<=(others=>'0');
3041  data_to_RTM1(41) <= dout_lcl_ro;
3042  data_to_RTM1(50 downto 42)<=(others=>'0');
3043 
3044  data_to_RTM2(15 downto 0) <= dout_cblb_mux0(15 downto 0);
3045  data_to_RTM2(39 downto 26) <= dout_cblb_mux1(13 downto 0);
3046  data_to_RTM2(25)<=dout_cblb_mux0(32);
3047  data_to_RTM2(51)<=dout_cblb_mux1(32);
3048  data_to_RTM2(24 downto 16)<=(others=>'0');
3049  data_to_RTM2(50 downto 40)<=(others=>'0');
3050 
3051 
3052  data_to_RTM(numbits_in_RTM_connector*2 -1 downto 0)<=data_to_RTM1;
3053  data_to_RTM((numbits_in_RTM_connector*2)*2 -1 downto (numbits_in_RTM_connector*2) )<=data_to_RTM2;
3054 
3055  ddr_data_out_RTM1<=ddr_data_out_RTM(0);
3056  ddr_data_out_RTM2<=ddr_data_out_RTM(1);
3057 
3058 
3059  gen_dummy_loc_vme_bus: for i_dummy in 1640 to 1759 generate
3060  data_vme_from_below_top(i_dummy)<=(others=>'0');
3061  bus_drive_from_below_top(i_dummy)<='0';
3062  end generate gen_dummy_loc_vme_bus;
3063 
3064 
3065  CMX_crate_cable_output_module_inst: entity work.CMX_crate_cable_output_module
3066  port map (
3067  data => data_to_RTM,
3068  ddr_data_out => ddr_data_out_RTM ,
3069  buf_clk40 => buf_clk40,
3070  buf_clk40_center => buf_clk40_90o,
3071  pll_locked => pll_locked,
3072  start_playback => start_playback,
3073  spy_write_inhibit => spy_write_inhibit ,
3074  ncs => ncs,
3075  rd_nwr => OCB_WRITE_B,
3076  ds => ds,
3077  addr_vme => vme_address(16 downto 1),
3078  data_vme_in => data_vme_going_below,
3079  data_vme_out => data_vme_from_below_top (1631),
3080  bus_drive => bus_drive_from_below_top(1631));
3081 
3082 
3083  --this address normally assigned to the rtm system cable input module
3084  data_vme_from_below_top(1636)<=(others=>'0');
3085  bus_drive_from_below_top(1636)<='0';
3086 
3087 
3088  --CMX_cable_clocked_80Mbps_output_module_RTM1: CMX_cable_clocked_80Mbps_output_module
3089  -- generic map (
3090  -- numbits_in_cable_connector => numbits_in_RTM_connector)
3091  -- port map (
3092  -- data => data_to_RTM1,
3093  -- ddr_data_out => ddr_data_out_RTM1,
3094  -- buf_clk40 => buf_clk40,
3095  -- buf_clk40_center => buf_clk40_center,
3096  -- buf_clk200 => buf_clk200,
3097  -- pll_locked => pll_locked,
3098  -- del_array => del_array_RTM,
3099  -- upload_delays => '0');
3100  --
3101  --CMX_cable_clocked_80Mbps_output_module_RTM2: CMX_cable_clocked_80Mbps_output_module
3102  -- generic map (
3103  -- numbits_in_cable_connector => numbits_in_RTM_connector)
3104  -- port map (
3105  -- data => data_to_RTM2,
3106  -- ddr_data_out => ddr_data_out_RTM2,
3107  -- buf_clk40 => buf_clk40,
3108  -- buf_clk40_center => buf_clk40_center,
3109  -- buf_clk200 => buf_clk200,
3110  -- pll_locked => pll_locked,
3111  -- del_array => del_array_RTM,
3112  -- upload_delays => '0');
3113 
3114  --del_array_RTM<=(others=>(others=>'0'));
3115 
3116 -- no output to CTP -- CMX_CTP_output_module_inst: entity work.CMX_CTP_output_module
3117 -- no output to CTP -- port map (
3118 -- no output to CTP -- data => dout,
3119 -- no output to CTP -- sdr_data_out => sdr_data_CTP,
3120 -- no output to CTP -- buf_clk40 => buf_clk40,
3121 -- no output to CTP -- buf_clk40_center => buf_clk40_m180o,
3122 -- no output to CTP -- buf_clk200 => buf_clk200,
3123 -- no output to CTP -- pll_locked => pll_locked,
3124 -- no output to CTP -- start_playback => start_playback,
3125 -- no output to CTP -- spy_write_inhibit => spy_write_inhibit,
3126 -- no output to CTP -- ncs => ncs,
3127 -- no output to CTP -- rd_nwr => OCB_WRITE_B,
3128 -- no output to CTP -- ds => ds,
3129 -- no output to CTP -- addr_vme => vme_address(16 downto 1),
3130 -- no output to CTP -- data_vme => OCB_D);
3131 
3132 
3133  --CMX_system_cable_input_module_inst: entity work.CMX_system_cable_input_module
3134  -- port map (
3135  -- data => data_from_RTM,
3136  -- parity_error => open,
3137  -- ddr_data_in => sig_arr_RTM,
3138  -- buf_clk40 => buf_clk40,
3139  -- buf_clk40_ds2 => buf_clk40_ds2,
3140  -- pll_locked => pll_locked,
3141  -- pll_locked_ds2 => pll_locked_ds2,
3142  -- start_playback => start_playback,
3143  -- spy_write_inhibit => spy_write_inhibit,
3144  -- ncs => ncs,
3145  -- rd_nwr => OCB_WRITE_B,
3146  -- ds => ds,
3147  -- addr_vme => vme_address(16 downto 1),
3148  -- data_vme => OCB_D);
3149 
3150  --chipscope_ila_LVDS_TX_CTP_RTM_inst: chipscope_ila_LVDS_TX_CTP_RTM
3151  -- port map (
3152  -- CONTROL => CONTROL1,
3153  -- CLK => buf_clk40,
3154  -- DATA(31 downto 0) => sdr_data_out,
3155  -- DATA(63 downto 32) => (others=>'0'),
3156  -- DATA(115 downto 64) => data_RTM,
3157  -- DATA(116) => '0',
3158  -- DATA(117) => '0',
3159  -- TRIG0(0) => '0',
3160  -- TRIG0(1) => '0'
3161  -- );
3162 
3163 
3164 
3165 
3166  CMX_clock_manager_inst: CMX_clock_manager
3167  port map (
3168  I_DS1 => CLK_40MHz08_DSKW_1_BF_LOGIC_DIR,
3169  IB_DS1 => CLK_40MHz08_DSKW_1_BF_LOGIC_CMP,
3170  buf_clk40 => buf_clk40,
3171  buf_clk40_90o => buf_clk40_90o,
3172  buf_clk40_m180o => buf_clk40_m180o,
3173  buf_clk40_m90o => buf_clk40_m90o,
3174  buf_clk320 => buf_clk320,
3175  buf_clk160 => buf_clk160,
3176  buf_clk200 => buf_clk200,
3177  pll_locked => pll_locked,
3178  I_DS2 => CLK_40MHz08_DSKW_2_BF_LOGIC_DIR,
3179  IB_DS2 => CLK_40MHz08_DSKW_2_BF_LOGIC_CMP,
3180  buf_clk40_ds2 => buf_clk40_ds2,
3181  pll_locked_ds2 => pll_locked_ds2,
3182  ncs => ncs,
3183  rd_nwr => OCB_WRITE_B ,
3184  ds => ds,
3185  addr_vme => vme_address(16 downto 1),
3186  data_vme_in => data_vme_going_below ,
3187  data_vme_out => data_vme_from_below_top(1762),
3188  bus_drive => bus_drive_from_below_top (1762));
3189 
3190 
3191  CMX_Jet_Topo_Encoder_inst: CMX_Jet_Topo_Encoder
3192  port map (
3193  Tobs_to_TOPO => Tobs_to_TOPO,
3194  overflow => overflow,
3195  send_align_out => send_align,
3196  Data_out => indata_Topo_TX );--,
3197  --clk => buf_clk40);
3198 
3199 
3200 
3201  Topo_Data_TX_inst: Topo_Data_TX
3202  port map (
3203  MGTREFCLK_PAD_N_IN => MGTREFCLK_PAD_N_IN,
3204  MGTREFCLK_PAD_P_IN => MGTREFCLK_PAD_P_IN,
3205  GTXTXRESET_IN => GTXTXRESET_IN,
3206  GTXRXRESET_IN => GTXRXRESET_IN,
3207  GTX_TX_READY_OUT => GTX_TX_READY_OUT ,
3208  GTX_RX_READY_OUT => GTX_RX_READY_OUT ,
3209  RXN_IN => RXN_IN,
3210  RXP_IN => RXP_IN,
3211  TXN_OUT => TXN_OUT,
3212  TXP_OUT => TXP_OUT,
3213  clk40 => buf_clk40,
3214  clk320 => buf_clk320,
3215  pll_locked => pll_locked,
3216  send_align => send_align,
3217  BCID => BCID_delayed_decoder,
3218  indata => indata_Topo_TX,
3219  ext_trigger => '0',
3220  ncs => ncs,
3221  rd_nwr => OCB_WRITE_B,
3222  ds => ds,
3223  addr_vme => vme_address(16 downto 1),
3224  data_vme_in => data_vme_going_below,
3225  data_vme_out => data_vme_from_below_top(1604),
3226  bus_drive => bus_drive_from_below_top (1604)
3227  );
3228 
3229 
3230 -- --for the test make a fake data to send topo
3231 -- gen_indata_counter_fiber: for i_fiber in 0 to 23 generate
3232 -- process(buf_clk40)
3233 -- begin
3234 -- if rising_edge(buf_clk40) then
3235 -- if counter_fake_data_Topo_TX(i_fiber)(11 downto 0)=to_unsigned(0,12) then
3236 -- send_align(i_fiber)<='1';
3237 -- else
3238 -- send_align(i_fiber)<='0';
3239 -- end if;
3240 -- counter_fake_data_Topo_TX(i_fiber)<=counter_fake_data_Topo_TX(i_fiber)+1;
3241 -- end if;
3242 -- end process;
3243 --
3244 --
3245 -- PRNG_LFSR_BIG_inst: PRNG_LFSR_BIG
3246 -- port map (
3247 -- clk => buf_clk40,
3248 -- rst => (not pll_locked),
3249 -- DATA_PRN => DATA_PRN(i_fiber) );
3250 --
3251 -- --counter repeated twice for the msb words
3252 -- gen_data_counter_word: for i_word in 6 to 7 generate
3253 -- indata_Topo_TX(128*(i_fiber)+16*(i_word)+15 downto 128*(i_fiber)+16*(i_word))<=std_logic_vector(counter_fake_data_Topo_TX(i_fiber));
3254 -- end generate gen_data_counter_word;
3255 --
3256 -- --then the 8 msb of the counter
3257 -- indata_Topo_TX(128*(i_fiber)+95 downto 128*(i_fiber)+88) <= std_logic_vector(counter_fake_data_Topo_TX(i_fiber)(15 downto 8));
3258 --
3259 -- --then the mgt number
3260 -- indata_Topo_TX(128*(i_fiber)+87 downto 128*(i_fiber)+80) <= std_logic_vector(to_unsigned(i_fiber,8));
3261 --
3262 -- --then the pseudo random number
3263 -- indata_Topo_TX(128*(i_fiber)+79 downto 128*(i_fiber)+16) <= DATA_PRN(i_fiber);
3264 --
3265 --
3266 -- --last 12 bits must be 0, four msb bits of the last word have the counter again
3267 -- indata_Topo_TX(128*(i_fiber)+15 downto 128*(i_fiber)+12) <= std_logic_vector(counter_fake_data_Topo_TX(i_fiber)(15 downto 12));
3268 -- indata_Topo_TX(128*(i_fiber)+11 downto 128*(i_fiber))<=(others=>'0');
3269 --
3270 -- end generate gen_indata_counter_fiber;
3271 
3272 
3273  vme_inreg_REG_RW_TOPOTR_GTX_RESET: vme_inreg_notri_async
3274  generic map (
3275  ia_vme => ADDR_REG_RW_TOPOTR_GTX_RESET ,
3276  width => 16)
3277  port map (
3278  ncs => ncs,
3279  rd_nwr => OCB_WRITE_B,
3280  ds => ds,
3281  addr_vme => vme_address(16 downto 1),
3282  data_vme_in => data_vme_going_below,
3283  data_vme_out => data_vme_from_below_top(1634),
3284  bus_drive => bus_drive_from_below_top (1634),
3285  data_from_vme => data_from_vme_REG_RW_TOPOTR_GTX_RESET,
3286  data_to_vme => data_to_vme_REG_RW_TOPOTR_GTX_RESET
3287  );
3288 
3289  GTXTXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(1);
3290  GTXRXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(0);
3291 
3292  data_to_vme_REG_RW_TOPOTR_GTX_RESET<=data_from_vme_REG_RW_TOPOTR_GTX_RESET;
3293 
3294 
3295  vme_outreg_async_REG_RO_TOPOTR_GTX_STATUS : vme_outreg_notri_async
3296  generic map (
3297  ia_vme => ADDR_REG_RO_TOPOTR_GTX_STATUS ,
3298  width => 16)
3299  port map (
3300  ncs => ncs,
3301  rd_nwr => OCB_WRITE_B,
3302  ds => ds,
3303  addr_vme => vme_address(16 downto 1),
3304  data_vme => data_vme_from_below_top(1635),
3305  bus_drive => bus_drive_from_below_top (1635),
3306  data_to_vme => data_to_vme_REG_RO_TOPOTR_GTX_STATUS );
3307 
3308  data_to_vme_REG_RO_TOPOTR_GTX_STATUS(1)<=GTX_TX_READY_OUT;
3309  data_to_vme_REG_RO_TOPOTR_GTX_STATUS(0)<=GTX_RX_READY_OUT;
3310 
3311  data_to_vme_REG_RO_TOPOTR_GTX_STATUS(15 downto 2)<=(others=>'0');
3312 
3313  -- sfp
3314 
3315 
3316  SFP_Data_TXRX_TX_SFP_DAQ: SFP_Data_TXRX
3317  generic map(
3318  direction => '1',
3319  clock_source => '1')
3320  port map (
3321  MGTREFCLK => MGTREFCLK_Q118,
3322  gtx_reset => gtx_reset_SFP_DAQ ,
3323  local_pll_lock_out => local_pll_lock_out_SFP_DAQ ,
3324  GTX_TX_READY_OUT => GTX_TX_READY_OUT_TX_SFP_DAQ ,
3325  GTX_RX_READY_OUT => GTX_RX_READY_OUT_TX_SFP_DAQ ,
3326  PLLLKDET_diag => PLLLKDET_diag_TX_SFP_DAQ ,
3327  local_gtx_reset_diag => local_gtx_reset_diag_TX_SFP_DAQ ,
3328  local_mmcm_reset_diag => local_mmcm_reset_diag_TX_SFP_DAQ ,
3329  GTXTEST_diag => GTXTEST_diag_TX_SFP_DAQ ,
3330  RXN_IN => RXN_IN_TX_SFP_DAQ ,
3331  RXP_IN => RXP_IN_TX_SFP_DAQ ,
3332  TXN_OUT => TXN_OUT_TX_SFP_DAQ,
3333  TXP_OUT => TXP_OUT_TX_SFP_DAQ,
3334  clk40_out => clk40_out_TX_SFP_DAQ,
3335  clk120_out => clk120_out_TX_SFP_DAQ,
3336  clk40_in => clk40_in_TX_SFP_DAQ,
3337  clk120_in => clk120_in_TX_SFP_DAQ,
3338  indata => indata_TX_SFP_DAQ ,
3339  odata => odata_TX_SFP_DAQ ,
3340  TXPREEMPHASIS_IN => TXPREEMPHASIS_IN_TX_SFP_DAQ ,
3341  TXPOSTEMPHASIS_IN => TXPOSTEMPHASIS_IN_TX_SFP_DAQ ,
3342  TXDIFFCTRL_IN => TXDIFFCTRL_IN_TX_SFP_DAQ ,
3343  RXEQMIX_IN => RXEQMIX_IN_TX_SFP_DAQ,
3344  DFECLKDLYADJ => DFECLKDLYADJ_TX_SFP_DAQ ,
3345  DFECLKDLYADJMON => DFECLKDLYADJMON_TX_SFP_DAQ ,
3346  DFEDLYOVRD => DFEDLYOVRD_TX_SFP_DAQ ,
3347  DFEEYEDACMON => DFEEYEDACMON_TX_SFP_DAQ ,
3348  DFESENSCAL => DFESENSCAL_TX_SFP_DAQ,
3349  DFETAP1 => DFETAP1_TX_SFP_DAQ,
3350  DFETAP1MONITOR => DFETAP1MONITOR_TX_SFP_DAQ ,
3351  DFETAP2 => DFETAP2_TX_SFP_DAQ,
3352  DFETAP2MONITOR => DFETAP2MONITOR_TX_SFP_DAQ ,
3353  DFETAP3 => DFETAP3_TX_SFP_DAQ,
3354  DFETAP3MONITOR => DFETAP3MONITOR_TX_SFP_DAQ ,
3355  DFETAP4 => DFETAP4_TX_SFP_DAQ,
3356  DFETAP4MONITOR => DFETAP4MONITOR_TX_SFP_DAQ ,
3357  DFETAPOVRD => DFETAPOVRD_TX_SFP_DAQ);
3358 
3359 
3360  SFP_Data_TXRX_TX_SFP_ROI: SFP_Data_TXRX
3361  generic map(
3362  direction => '1',
3363  clock_source => '0')
3364  port map (
3365  MGTREFCLK => MGTREFCLK_Q118,
3366  gtx_reset => gtx_reset_SFP_ROI ,
3367  local_pll_lock_out => local_pll_lock_out_SFP_ROI ,
3368  GTX_TX_READY_OUT => GTX_TX_READY_OUT_TX_SFP_ROI ,
3369  GTX_RX_READY_OUT => GTX_RX_READY_OUT_TX_SFP_ROI ,
3370  PLLLKDET_diag => PLLLKDET_diag_TX_SFP_ROI ,
3371  local_gtx_reset_diag => local_gtx_reset_diag_TX_SFP_ROI ,
3372  local_mmcm_reset_diag => local_mmcm_reset_diag_TX_SFP_ROI ,
3373  GTXTEST_diag => GTXTEST_diag_TX_SFP_ROI ,
3374  RXN_IN => RXN_IN_TX_SFP_ROI ,
3375  RXP_IN => RXP_IN_TX_SFP_ROI ,
3376  TXN_OUT => TXN_OUT_TX_SFP_ROI,
3377  TXP_OUT => TXP_OUT_TX_SFP_ROI,
3378  clk40_out => clk40_out_TX_SFP_ROI,
3379  clk120_out => clk120_out_TX_SFP_ROI,
3380  clk40_in => clk40_in_TX_SFP_ROI,
3381  clk120_in => clk120_in_TX_SFP_ROI,
3382  indata => indata_TX_SFP_ROI ,
3383  odata => odata_TX_SFP_ROI ,
3384  TXPREEMPHASIS_IN => TXPREEMPHASIS_IN_TX_SFP_ROI ,
3385  TXPOSTEMPHASIS_IN => TXPOSTEMPHASIS_IN_TX_SFP_ROI ,
3386  TXDIFFCTRL_IN => TXDIFFCTRL_IN_TX_SFP_ROI ,
3387  RXEQMIX_IN => RXEQMIX_IN_TX_SFP_ROI,
3388  DFECLKDLYADJ => DFECLKDLYADJ_TX_SFP_ROI ,
3389  DFECLKDLYADJMON => DFECLKDLYADJMON_TX_SFP_ROI ,
3390  DFEDLYOVRD => DFEDLYOVRD_TX_SFP_ROI ,
3391  DFEEYEDACMON => DFEEYEDACMON_TX_SFP_ROI ,
3392  DFESENSCAL => DFESENSCAL_TX_SFP_ROI,
3393  DFETAP1 => DFETAP1_TX_SFP_ROI,
3394  DFETAP1MONITOR => DFETAP1MONITOR_TX_SFP_ROI ,
3395  DFETAP2 => DFETAP2_TX_SFP_ROI,
3396  DFETAP2MONITOR => DFETAP2MONITOR_TX_SFP_ROI ,
3397  DFETAP3 => DFETAP3_TX_SFP_ROI,
3398  DFETAP3MONITOR => DFETAP3MONITOR_TX_SFP_ROI ,
3399  DFETAP4 => DFETAP4_TX_SFP_ROI,
3400  DFETAP4MONITOR => DFETAP4MONITOR_TX_SFP_ROI ,
3401  DFETAPOVRD => DFETAPOVRD_TX_SFP_ROI);
3402 
3403 -- glink interface
3404 
3405 
3406  glink: glink_interface
3407  port map (
3408  CLK_40MHz => clk40_in_TX_SFP_ROI, -- clk40MHz
3409  CLK_120MHz => clk120_in_TX_SFP_ROI , -- clk120MHz
3410  RST => reset_daq , --not pll_locked, --reset(0), -- reset
3411  DAQ_IN => daq_in, -- Input data (DAQ)
3412  ROI_IN => roi_in, -- Input data (ROI)
3413  DAQ_DAV => daq_dav, -- Control (DAQ)
3414  ROI_DAV => roi_dav, -- Control (ROI)
3415  DAQ_BYTE => roi_byte, -- Output Byte (DAQ)
3416  ROI_BYTE => daq_byte, -- Output Byte (ROI)
3417  DAQ_ENCODED_DIAG => daq_encoded_diag,
3418  daq_byte_out => daq_byte_out,
3419  byte_pos_out => byte_pos_out,
3420  word_sel_out => word_sel_out,
3421  readout_rst_out => readout_rst_out
3422 
3423 
3424 
3425  ); -- daq_encoded_DIAG
3426 
3427  MGT_118_clk0_ibufds_i : IBUFDS_GTXE1
3428  port map
3429  (
3430  O => MGTREFCLK_Q118,
3431  ODIV2 => open,
3432  CEB => '0',
3433  I => CLK_120MHz000_XTAL_1_BF_TRNCV_DIR,
3434  IB => CLK_120MHz000_XTAL_1_BF_TRNCV_CMP
3435  );
3436 
3437  BF_DAQ_DATA_OUT_DIR<=TXP_OUT_TX_SFP_DAQ;
3438  BF_DAQ_DATA_OUT_CMP<=TXN_OUT_TX_SFP_DAQ;
3439 
3440  BF_ROI_DATA_OUT_DIR<=TXP_OUT_TX_SFP_ROI;
3441  BF_ROI_DATA_OUT_CMP<=TXN_OUT_TX_SFP_ROI;
3442 
3443  clk40_in_TX_SFP_ROI<=clk40_out_TX_SFP_DAQ;
3444  clk120_in_TX_SFP_ROI<=clk120_out_TX_SFP_DAQ;
3445 
3446  indata_TX_SFP_DAQ<=daq_byte; -- from GLINK emulator
3447  indata_TX_SFP_ROI<=roi_byte; -- from GLINK emulator;
3448 
3449 -- Reset control
3450 
3451  --vio_data_i : diagn_module_vio
3452  -- port map(
3453  -- CONTROL => control1,
3454  -- ASYNC_OUT => reset);
3455 
3456  vme_inreg_async_REG_RW_DAQ_ROI_RESET : vme_inreg_notri_async
3457  generic map (
3458  ia_vme => ADDR_REG_RW_DAQ_ROI_RESET ,
3459  width => 16)
3460  port map (
3461  ncs => ncs,
3462  rd_nwr => OCB_WRITE_B,
3463  ds => ds,
3464  addr_vme => vme_address(16 downto 1),
3465  data_vme_in => data_vme_going_below,
3466  data_vme_out => data_vme_from_below_top(1629),
3467  bus_drive => bus_drive_from_below_top (1629),
3468  data_from_vme => data_from_vme_REG_RW_DAQ_ROI_RESET,
3469  data_to_vme => data_to_vme_REG_RW_DAQ_ROI_RESET);
3470 
3471  reset_daq<=data_from_vme_REG_RW_DAQ_ROI_RESET(0);
3472  data_to_vme_REG_RW_DAQ_ROI_RESET<=data_from_vme_REG_RW_DAQ_ROI_RESET;
3473 
3474  vme_inreg_async_REG_RW_DAQ_ROI_GTX_RESET : vme_inreg_notri_async
3475  generic map (
3476  ia_vme => ADDR_REG_RW_DAQ_ROI_GTX_RESET ,
3477  width => 16)
3478  port map (
3479  ncs => ncs,
3480  rd_nwr => OCB_WRITE_B,
3481  ds => ds,
3482  addr_vme => vme_address(16 downto 1),
3483  data_vme_in => data_vme_going_below,
3484  data_vme_out => data_vme_from_below_top(1633),
3485  bus_drive => bus_drive_from_below_top (1633),
3486  data_from_vme => data_from_vme_REG_RW_DAQ_ROI_GTX_RESET,
3487  data_to_vme => data_to_vme_REG_RW_DAQ_ROI_GTX_RESET);
3488 
3489  gtx_reset_SFP_DAQ<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(0);
3490  gtx_reset_SFP_ROI<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(1);
3491  data_to_vme_REG_RW_DAQ_ROI_GTX_RESET<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET;
3492 
3493 
3494  vme_outreg_async_REG_RO_DAQ_ROI_STATUS : vme_outreg_notri_async
3495  generic map (
3496  ia_vme => ADDR_REG_RO_DAQ_ROI_STATUS ,
3497  width => 16)
3498  port map (
3499  ncs => ncs,
3500  rd_nwr => OCB_WRITE_B,
3501  ds => ds,
3502  addr_vme => vme_address(16 downto 1),
3503  data_vme => data_vme_from_below_top(1632),
3504  bus_drive => bus_drive_from_below_top (1632),
3505  data_to_vme => data_to_vme_REG_RO_DAQ_ROI_STATUS );
3506 
3507  data_to_vme_REG_RO_DAQ_ROI_STATUS(0)<=local_pll_lock_out_SFP_DAQ;
3508  data_to_vme_REG_RO_DAQ_ROI_STATUS(1)<=GTX_TX_READY_OUT_TX_SFP_DAQ;
3509  data_to_vme_REG_RO_DAQ_ROI_STATUS(2)<=GTX_RX_READY_OUT_TX_SFP_DAQ;
3510  data_to_vme_REG_RO_DAQ_ROI_STATUS(3)<=PLLLKDET_diag_TX_SFP_DAQ;
3511  data_to_vme_REG_RO_DAQ_ROI_STATUS(4)<=local_pll_lock_out_SFP_ROI;
3512  data_to_vme_REG_RO_DAQ_ROI_STATUS(5)<=GTX_TX_READY_OUT_TX_SFP_ROI;
3513  data_to_vme_REG_RO_DAQ_ROI_STATUS(6)<=GTX_RX_READY_OUT_TX_SFP_ROI;
3514  data_to_vme_REG_RO_DAQ_ROI_STATUS(7)<=PLLLKDET_diag_TX_SFP_ROI;
3515  data_to_vme_REG_RO_DAQ_ROI_STATUS(8)<=readout_rst_out;
3516 
3517  data_to_vme_REG_RO_DAQ_ROI_STATUS(15 downto 9) <= (others=>'0');
3518 
3519 
3520 -- Chipscope analyzer
3521 
3522  --ila_daq_glink : glink_chipscope_analyzer
3523  -- port map (
3524  -- CONTROL => control0,
3525  -- CLK => clk40_in_TX_SFP_ROI,
3526  -- DATA => data_ila_daq,
3527  -- TRIG0 => trig_ila_daq);
3528  --
3529  --ila_glink_encoder : glink_chipscope_analyzer_encoder
3530  -- port map (
3531  -- CONTROL => control1,
3532  -- CLK => clk120_in_TX_SFP_ROI,
3533  -- DATA => data_ila_encoder,
3534  -- TRIG0 => trig_ila_encoder);
3535  --
3536  --ila_gtx_start: entity work.glink_chipscope_analyzer_gtx_start
3537  -- port map (
3538  -- CONTROL => CONTROL2,
3539  -- CLK => MGTREFCLK_Q118,
3540  -- DATA => data_ila_gtx_start,
3541  -- TRIG0 => trig_ila_gtx_start);
3542  --
3543  --data_ila_daq <= daq_in &
3544  -- daq_encoded_diag &
3545  -- pll_locked &
3546  -- local_pll_lock_out_SFP_DAQ &
3547  -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3548  -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3549  -- local_pll_lock_out_SFP_ROI &
3550  -- GTX_TX_READY_OUT_TX_SFP_ROI &
3551  -- GTX_RX_READY_OUT_TX_SFP_ROI &
3552  -- reset_daq &
3553  -- l1a_synced &
3554  -- daq_dav ;
3555  --
3556  --
3557  --trig_ila_daq <= daq_encoded_diag &
3558  -- pll_locked &
3559  -- local_pll_lock_out_SFP_DAQ &
3560  -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3561  -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3562  -- local_pll_lock_out_SFP_ROI &
3563  -- GTX_TX_READY_OUT_TX_SFP_ROI &
3564  -- GTX_RX_READY_OUT_TX_SFP_ROI &
3565  -- reset_daq &
3566  -- l1a_synced &
3567  -- daq_dav ;
3568  --
3569  --
3570  --
3571  --trig_ila_encoder <= GTX_TX_READY_OUT_TX_SFP_DAQ &
3572  -- reset_daq &
3573  -- l1a_synced &
3574  -- daq_byte &
3575  -- pll_locked;
3576  --
3577  --data_ila_encoder <= byte_pos_out &
3578  -- word_sel_out &
3579  -- readout_rst_out &
3580  -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3581  -- reset_daq &
3582  -- l1a_synced &
3583  -- daq_byte&
3584  -- pll_locked;
3585  --
3586  --trig_ila_gtx_start(0)<=pll_locked;
3587  --trig_ila_gtx_start(1)<=gtx_reset_SFP_DAQ;
3588  --trig_ila_gtx_start(2)<=gtx_reset_SFP_ROI;
3589  --
3590  --
3591  --
3592  --data_ila_gtx_start(0)<= pll_locked;
3593  --data_ila_gtx_start(1)<= gtx_reset_SFP_DAQ;
3594  --data_ila_gtx_start(2)<= gtx_reset_SFP_ROI;
3595  --data_ila_gtx_start(3)<= GTX_TX_READY_OUT_TX_SFP_DAQ;
3596  --data_ila_gtx_start(4)<= PLLLKDET_diag_TX_SFP_DAQ;
3597  --data_ila_gtx_start(5)<= local_gtx_reset_diag_TX_SFP_DAQ;
3598  --data_ila_gtx_start(6)<= local_mmcm_reset_diag_TX_SFP_DAQ;
3599  --data_ila_gtx_start(7)<= GTXTEST_diag_TX_SFP_DAQ;
3600  --data_ila_gtx_start(8)<= GTX_TX_READY_OUT_TX_SFP_ROI;
3601  --data_ila_gtx_start(9)<= PLLLKDET_diag_TX_SFP_ROI;
3602  --data_ila_gtx_start(10)<= local_gtx_reset_diag_TX_SFP_ROI;
3603  --data_ila_gtx_start(11)<= local_mmcm_reset_diag_TX_SFP_ROI;
3604  --data_ila_gtx_start(12)<= GTXTEST_diag_TX_SFP_ROI;
3605 
3606 
3607 
3608  process(buf_clk40)
3609  begin
3610  if rising_edge(buf_clk40) then
3611  l1a_synced<=BUF_TTC_L1_ACCEPT_r;
3612  BUF_TTC_L1_ACCEPT_r<=BUF_TTC_L1_ACCEPT;
3613 
3614  bc_reset_synced<=BUF_TTC_BNCH_CNT_RES_r;
3615  BUF_TTC_BNCH_CNT_RES_r<=BUF_TTC_BNCH_CNT_RES;
3616  end if;
3617  end process;
3618 
3619 
3620  daq_i: entity work.daq_glink
3621  port map (
3622  data_in => data_in_daq ,
3623  bc_counter => unsigned(BCID_delayed_daq),
3624  l1a => l1a_synced ,
3625  data_out => daq_in,
3626  dav => daq_dav ,
3627  clk4000 => clk40_out_TX_SFP_DAQ ,
3628  clk4008 => buf_clk40,
3629  reset => reset_daq ,--not pll_locked,
3630  RAM_global_offset => RAM_global_offset ,
3631  RAM_rel_offsets => RAM_rel_offsets,
3632  nslices => nslices
3633  );
3634 
3635  --in this flavor roi and daq have the same behavior
3636  roi_dav<=daq_dav;
3637  roi_in<=daq_in;
3638 
3639  --readout control registers
3640  vme_inreg_async_REG_RW_DAQ_SLICE: entity work.vme_inreg_notri_async
3641  generic map (
3642  ia_vme => ADDR_REG_RW_DAQ_SLICE,
3643  width => 16)
3644  port map (
3645  ncs => ncs,
3646  rd_nwr => OCB_WRITE_B ,
3647  ds => ds,
3648  addr_vme => vme_address(16 downto 1),
3649  data_vme_in => data_vme_going_below ,
3650  data_vme_out => data_vme_from_below_top(1607),
3651  bus_drive => bus_drive_from_below_top (1607),
3652  data_from_vme => data_from_vme_REG_RW_DAQ_SLICE,
3653  data_to_vme => data_to_vme_REG_RW_DAQ_SLICE );
3654 
3655  nslices(1 downto 0) <= unsigned(data_to_vme_REG_RW_DAQ_SLICE(1 downto 0));
3656  nslices(7 downto 2) <= (others=>'0');
3657 
3658  data_to_vme_REG_RW_DAQ_SLICE<=data_from_vme_REG_RW_DAQ_SLICE;
3659 
3660 
3661  vme_inreg_async_REG_DAQ_RAM_OFFSET: entity work.vme_inreg_notri_async
3662  generic map (
3663  ia_vme => ADDR_REG_RW_DAQ_RAM_OFFSET ,
3664  width => 16)
3665  port map (
3666  ncs => ncs,
3667  rd_nwr => OCB_WRITE_B ,
3668  ds => ds,
3669  addr_vme => vme_address(16 downto 1),
3670  data_vme_in => data_vme_going_below ,
3671  data_vme_out => data_vme_from_below_top(1608),
3672  bus_drive => bus_drive_from_below_top (1608),
3673  data_from_vme => data_from_vme_REG_RW_DAQ_RAM_OFFSET,
3674  data_to_vme => data_to_vme_REG_RW_DAQ_RAM_OFFSET);
3675 
3676  data_to_vme_REG_RW_DAQ_RAM_OFFSET<=data_from_vme_REG_RW_DAQ_RAM_OFFSET;
3677  RAM_global_offset <= unsigned(data_from_vme_REG_RW_DAQ_RAM_OFFSET(7 downto 0));
3678 
3679 
3680  rel_offset_gen: for i_row in 1 to 19 generate
3681  vme_inreg_async_REG_DAQ_RAM_OFFSET: entity work.vme_inreg_notri_async
3682  generic map (
3683  ia_vme => (ADDR_REG_RW_DAQ_RAM_RELATIVE_OFFSET+2*(i_row-1)),
3684  width => 16)
3685  port map (
3686  ncs => ncs,
3687  rd_nwr => OCB_WRITE_B,
3688  ds => ds,
3689  data_vme_in => data_vme_going_below,
3690  addr_vme => vme_address(16 downto 1),
3691  data_vme_out => data_vme_from_below_top (1609+i_row),
3692  bus_drive => bus_drive_from_below_top (1609+i_row),
3693  data_from_vme => data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1),
3694  data_to_vme => data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1));
3695 
3696  data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)<=data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1);
3697  RAM_rel_offsets(i_row-1)<=unsigned(data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)(7 downto 0));
3698  end generate rel_offset_gen;
3699 
3700 
3701  daq_collector_i :entity work.daq_collector
3702  port map (
3703  clk => buf_clk40 ,
3704  datai => DATA96,
3705  din_cbl => din_cbl,
3706  din_cbl_ro => '0',
3707  din_lcl => dout_lcl,
3708  din_lcl_ro => dout_lcl_ro,
3709  dout => (others =>'0'),
3710  dout_ro => '0',
3711  data_in_daq => data_in_daq,
3712  BCID_in => BCID_counter_sig ,
3713  BCID_delayed => BCID_delayed_daq );
3714 
3715  CMX_rate_counter_inhibit_inst: entity work.CMX_rate_counter_inhibit
3716  port map (
3717  counter_inhibit => counter_inhibit,
3718  counter_reset => counter_reset,
3719  buf_clk40 => buf_clk40,
3720  ncs => ncs,
3721  rd_nwr => OCB_WRITE_B ,
3722  ds => ds,
3723  addr_vme => vme_address(16 downto 1),
3724  data_vme_in => data_vme_going_below,
3725  data_vme_out => data_vme_from_below_top(1637),
3726  bus_drive => bus_drive_from_below_top (1637));
3727 
3728 end Behavioral;
3729 
CMX_top_Base.P6_5
in P6_5std_logic
Definition: CMX_top_Base.vhd:246
CMX_top_Base.BF_DOUT_CTP_41
out BF_DOUT_CTP_41std_logic
Definition: CMX_top_Base.vhd:581
CMX_top_Base.P3_21
in P3_21std_logic
Definition: CMX_top_Base.vhd:187
CMX_top_Base.P9_17
in P9_17std_logic
Definition: CMX_top_Base.vhd:333
CMX_top_Base.BF_SYSMON_13_N
in BF_SYSMON_13_NSTD_LOGIC
Definition: CMX_top_Base.vhd:84
CMX_top_Base.P1_7
in P1_7std_logic
Definition: CMX_top_Base.vhd:123
Topo_Data_TX.TXN_OUT
out TXN_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:36
CMX_top_Base.BF_SYSMON_14_P
in BF_SYSMON_14_PSTD_LOGIC
Definition: CMX_top_Base.vhd:85
CMX_top_Base.P12_4
in P12_4std_logic
Definition: CMX_top_Base.vhd:395
CMX_top_Base.P3_6
in P3_6std_logic
Definition: CMX_top_Base.vhd:172
CMX_top_Base.Behavioral.ncs
std_logic ncs
Definition: CMX_top_Base.vhd:793
CMX_top_Base.P11_20
in P11_20std_logic
Definition: CMX_top_Base.vhd:386
CMX_top_Base.D_CBL_48_B
out D_CBL_48_Bstd_logic
Definition: CMX_top_Base.vhd:656
CMX_top_Base.P6_24
in P6_24std_logic
Definition: CMX_top_Base.vhd:265
CMX_top_Base.BF_DOUT_CTP_01
out BF_DOUT_CTP_01std_logic
Definition: CMX_top_Base.vhd:539
CMX_top_Base.P13_17
in P13_17std_logic
Definition: CMX_top_Base.vhd:433
CMX_top_Base.P10_16
in P10_16std_logic
Definition: CMX_top_Base.vhd:357
CMX_top_Base.P14_21
in P14_21std_logic
Definition: CMX_top_Base.vhd:462
CMX_top_Base.P11_18
in P11_18std_logic
Definition: CMX_top_Base.vhd:384
CMX_top_Base.BF_TO_FROM_BSPT_2
out BF_TO_FROM_BSPT_2std_logic
Definition: CMX_top_Base.vhd:530
vme_inreg.read_detect
out read_detectstd_logic
Definition: vme_inreg_rtl.vhd:38
CMX_top_Base.BF_DAQ_DATA_OUT_CMP
out BF_DAQ_DATA_OUT_CMPstd_logic
Definition: CMX_top_Base.vhd:705
CMX_top_Base.OCB_A10
in OCB_A10std_logic
Definition: CMX_top_Base.vhd:41
CMX_top_Base.CLK_120MHz000_XTAL_1_BF_TRNCV_DIR
in CLK_120MHz000_XTAL_1_BF_TRNCV_DIRstd_logic
Definition: CMX_top_Base.vhd:702
CMX_top_Base.P11_7
in P11_7std_logic
Definition: CMX_top_Base.vhd:373
CMX_top_Base.P14_13
in P14_13std_logic
Definition: CMX_top_Base.vhd:454
CMX_top_Base.D_CBL_74_B
out D_CBL_74_Bstd_logic
Definition: CMX_top_Base.vhd:684
CMX_top_Base.P1_21
in P1_21std_logic
Definition: CMX_top_Base.vhd:137
sys_monitor.BF_SYSMON_09_P
in BF_SYSMON_09_PSTD_LOGIC
Definition: sys_monitor.vhd:38
CMX_top_Base.P7_20
in P7_20std_logic
Definition: CMX_top_Base.vhd:286
CMX_top_Base.D_CBL_32_B
out D_CBL_32_Bstd_logic
Definition: CMX_top_Base.vhd:640
CMX_delay_generator.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_delay_generator.vhd:39
CMX_top_Base.BF_TO_TP_ROI_SLINK_RETURN_CMP
in BF_TO_TP_ROI_SLINK_RETURN_CMPstd_logic
Definition: CMX_top_Base.vhd:696
vme_outreg_notri.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl_notri.vhd:16
CMX_top_Base.BF_TO_FROM_BSPT_3
out BF_TO_FROM_BSPT_3std_logic
Definition: CMX_top_Base.vhd:531
CMX_top_Base.MP1_F11_QUAD_111_TRN_1_CMP
out MP1_F11_QUAD_111_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:720
CMX_top_Base.P5_10
in P5_10std_logic
Definition: CMX_top_Base.vhd:226
CMX_crate_cable_output_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_crate_cable_output_module.vhd:39
CMX_top_Base.P7_10
in P7_10std_logic
Definition: CMX_top_Base.vhd:276
CMX_top_Base.P2_14
in P2_14std_logic
Definition: CMX_top_Base.vhd:155
CMX_top_Base.P1_2
in P1_2std_logic
Definition: CMX_top_Base.vhd:118
CMX_top_Base.P9_3
in P9_3std_logic
Definition: CMX_top_Base.vhd:319
daq_collector.dout
in doutT_SLV62
Definition: daq_collector.vhd:30
CMX_input_module.ODATA
out ODATAarr_4Xword (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:33
CMX_top_Base.P1_10
in P1_10std_logic
Definition: CMX_top_Base.vhd:126
CMX_top_Base.D_CBL_42_B
out D_CBL_42_Bstd_logic
Definition: CMX_top_Base.vhd:650
CMX_top_Base.P1_19
in P1_19std_logic
Definition: CMX_top_Base.vhd:135
CMX_top_Base.P4_12
in P4_12std_logic
Definition: CMX_top_Base.vhd:203
CMX_top_Base.P7_5
in P7_5std_logic
Definition: CMX_top_Base.vhd:271
vme_inreg.write_detect
out write_detectstd_logic
Definition: vme_inreg_rtl.vhd:39
CMX_top_Base.P12_6
in P12_6std_logic
Definition: CMX_top_Base.vhd:397
CMX_input_module.ds
in dsstd_logic
Definition: CMX_input_module.vhd:59
CMX_top_Base.Behavioral.read_detect_inreg_test
std_logic read_detect_inreg_test
Definition: CMX_top_Base.vhd:936
vme_outreg.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl.vhd:24
CMX_top_Base.BF_LED_REQ_4
out BF_LED_REQ_4std_logic
Definition: CMX_top_Base.vhd:527
CMX_top_Base.P8_24
in P8_24std_logic
Definition: CMX_top_Base.vhd:315
CMX_top_Base.OCB_A19
in OCB_A19std_logic
Definition: CMX_top_Base.vhd:50
CMX_crate_cable_output_module.start_playback
in start_playbackstd_logic
Definition: CMX_crate_cable_output_module.vhd:34
vme_outreg.clk
in clkstd_logic
Definition: vme_outreg_rtl.vhd:21
CMX_BASE_VME_BSPT.n_write
in n_writestd_logic
Definition: cmx_base_vme_bspt.vhd:29
CMX_top_Base.BF_TO_FROM_BSPT_0
in BF_TO_FROM_BSPT_0std_logic
Definition: CMX_top_Base.vhd:528
CMX_clock_manager
Definition: CMX_clock_manager.vhd:27
CMX_top_Base.D_CBL_17_B
out D_CBL_17_Bstd_logic
Definition: CMX_top_Base.vhd:623
CMX_top_Base.P7_18
in P7_18std_logic
Definition: CMX_top_Base.vhd:284
vme_inreg_notri.read_detect
out read_detectstd_logic
Definition: vme_inreg_rtl_notri.vhd:39
CMX_top_Base.P6_15
in P6_15std_logic
Definition: CMX_top_Base.vhd:256
decoder.thresholds_width
thresholds_widthinteger :=10
Definition: jet_decoder.vhd:39
CMX_top_Base.BF_DOUT_CTP_61
out BF_DOUT_CTP_61std_logic
Definition: CMX_top_Base.vhd:601
vme_outreg_notri_async.ncs
in ncsstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:22
CMX_top_Base.P3_14
in P3_14std_logic
Definition: CMX_top_Base.vhd:180
CMX_input_module.PAR_ERROR_total
out PAR_ERROR_totalstd_logic
Definition: CMX_input_module.vhd:39
CMX_Memory_spy_inhibit
Definition: CMX_Memory_spy_inhibit.vhd:37
CMX_top_Base.P4_21
in P4_21std_logic
Definition: CMX_top_Base.vhd:212
daq_collector.data_in_daq
out data_in_daqarr_96 (19 downto 0)
Definition: daq_collector.vhd:32
CMX_top_Base.OCB_A21
in OCB_A21std_logic
Definition: CMX_top_Base.vhd:52
adder_top
Definition: adder_top_vs.vhd:28
CMX_top_Base.P1_11
in P1_11std_logic
Definition: CMX_top_Base.vhd:127
CMX_top_Base.D_CBL_64_B
out D_CBL_64_Bstd_logic
Definition: CMX_top_Base.vhd:674
CMX_top_Base.P5_13
in P5_13std_logic
Definition: CMX_top_Base.vhd:229
CMX_top_Base.P6_19
in P6_19std_logic
Definition: CMX_top_Base.vhd:260
vme_inreg_notri_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:29
sys_monitor.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: sys_monitor.vhd:58
CMX_top_Base.BF_DOUT_CTP_34
out BF_DOUT_CTP_34std_logic
Definition: CMX_top_Base.vhd:574
Topo_Data_TX.MGTREFCLK_PAD_N_IN
in MGTREFCLK_PAD_N_INstd_logic_vector (num_GTX_groups - 1 downto 0)
Definition: Topo_Data_TX.vhd:27
CMX_top_Base.P15_5
in P15_5std_logic
Definition: CMX_top_Base.vhd:471
CMX_top_Base.P5_6
in P5_6std_logic
Definition: CMX_top_Base.vhd:222
CMX_top_Base.P9_10
in P9_10std_logic
Definition: CMX_top_Base.vhd:326
CMX_top_Base.MP1_F04_QUAD_112_TRN_0_DIR
out MP1_F04_QUAD_112_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:725
vme_inreg.data_vme
inout data_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl.vhd:32
CMX_system_cable_input_module.start_playback
in start_playbackstd_logic
Definition: CMX_system_cable_input_module.vhd:40
CMX_top_Base.BF_DOUT_CTP_32
out BF_DOUT_CTP_32std_logic
Definition: CMX_top_Base.vhd:572
CMX_CTP_output_module.buf_clk200
in buf_clk200std_logic
Definition: CMX_CTP_output_module.vhd:38
daq_glink.data_in
in data_inarr_96 (19 downto 0)
Definition: daq_glink.vhd:24
adder_top.din_cbl
in din_cblT_SLV65
Definition: adder_top_vs.vhd:38
CMX_crate_cable_output_module.ncs
in ncsstd_logic
Definition: CMX_crate_cable_output_module.vhd:38
CMX_top_Base.D_CBL_81_B
out D_CBL_81_Bstd_logic
Definition: CMX_top_Base.vhd:633
CMX_crate_cable_output_module.buf_clk40_center
in buf_clk40_centerstd_logic
Definition: CMX_crate_cable_output_module.vhd:32
CMX_top_Base.P11_3
in P11_3std_logic
Definition: CMX_top_Base.vhd:369
CMX_version.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_version.vhd:26
CMX_top_Base.P6_4
in P6_4std_logic
Definition: CMX_top_Base.vhd:245
decoder.Tobs_to_TOPO
out Tobs_to_TOPOcopy_arr_TOB
Definition: jet_decoder.vhd:49
CMX_top_Base.P9_7
in P9_7std_logic
Definition: CMX_top_Base.vhd:323
adder_top.ds
in dsstd_logic
Definition: adder_top_vs.vhd:51
CMX_top_Base.P9_12
in P9_12std_logic
Definition: CMX_top_Base.vhd:328
CMX_top_Base.P13_18
in P13_18std_logic
Definition: CMX_top_Base.vhd:434
decoder.datai_first_half
in datai_first_halfarr_2Xword (max_jems - 1 downto 0)
Definition: jet_decoder.vhd:48
CMX_top_Base.D_CBL_67_B
out D_CBL_67_Bstd_logic
Definition: CMX_top_Base.vhd:677
CMX_top_Base.P7_9
in P7_9std_logic
Definition: CMX_top_Base.vhd:275
CMX_top_Base.MP1_F07_QUAD_110_TRN_2_DIR
out MP1_F07_QUAD_110_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:713
CMX_top_Base.P0_6
in P0_6std_logic
Definition: CMX_top_Base.vhd:97
CMX_top_Base.P6_1
in P6_1std_logic
Definition: CMX_top_Base.vhd:242
CMX_top_Base.P10_5
in P10_5std_logic
Definition: CMX_top_Base.vhd:346
CMX_top_Base.P1_4
in P1_4std_logic
Definition: CMX_top_Base.vhd:120
sys_monitor.rd_nwr
in rd_nwrstd_logic
Definition: sys_monitor.vhd:54
vme_outreg_notri_async.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:27
CMX_top_Base.P13_20
in P13_20std_logic
Definition: CMX_top_Base.vhd:436
CMX_top_Base.D_CBL_24_B
in D_CBL_24_Bstd_logic
Definition: CMX_top_Base.vhd:630
CMX_top_Base.D_CBL_28_B
out D_CBL_28_Bstd_logic
Definition: CMX_top_Base.vhd:636
decoder.clk40MHz_90o
in clk40MHz_90ostd_logic
Definition: jet_decoder.vhd:44
CMX_top_Base.BF_TO_FROM_BSPT_6
out BF_TO_FROM_BSPT_6std_logic
Definition: CMX_top_Base.vhd:534
vme_inreg_notri.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:33
SFP_Data_TXRX.local_gtx_reset_diag
out local_gtx_reset_diagstd_logic
Definition: SFP_TXRX.vhd:39
CMX_top_Base.P8_19
in P8_19std_logic
Definition: CMX_top_Base.vhd:310
SFP_Data_TXRX.DFETAP2MONITOR
out DFETAP2MONITORstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:64
CMX_top_Base.P6_16
in P6_16std_logic
Definition: CMX_top_Base.vhd:257
decoder.counter_inhibit
in counter_inhibitstd_logic
Definition: jet_decoder.vhd:61
CMX_top_Base.BF_LED_REQ_1
out BF_LED_REQ_1std_logic
Definition: CMX_top_Base.vhd:524
CMX_top_Base.MP2_F01_QUAD_113_TRN_0_CMP
out MP2_F01_QUAD_113_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:734
vme_outreg.ds
in dsstd_logic
Definition: vme_outreg_rtl.vhd:25
CMX_top_Base.P11_0
in P11_0std_logic
Definition: CMX_top_Base.vhd:366
CMX_top_Base.P5_21
in P5_21std_logic
Definition: CMX_top_Base.vhd:237
CMX_Memory_spy_inhibit.bus_drive
out bus_drivestd_logic
Definition: CMX_Memory_spy_inhibit.vhd:48
Topo_Data_TX.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:56
CMX_top_Base.BF_DEBUG_2
out BF_DEBUG_2std_logic
Definition: CMX_top_Base.vhd:508
CMX_top_Base.P5_8
in P5_8std_logic
Definition: CMX_top_Base.vhd:224
CMX_cable_clocked_80Mbps_input_module.data
out datastd_logic_vector ((numbits_in_cable_connector * 2) - 1 downto 0)
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:26
CMX_top_Base.BF_DOUT_CTP_21
out BF_DOUT_CTP_21std_logic
Definition: CMX_top_Base.vhd:559
CMX_top_Base.P7_21
in P7_21std_logic
Definition: CMX_top_Base.vhd:287
CMX_clock_manager.buf_clk160
out buf_clk160std_logic
Definition: CMX_clock_manager.vhd:37
SFP_Data_TXRX
Definition: SFP_TXRX.vhd:21
CMX_system_cable_input_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_system_cable_input_module.vhd:47
CMX_top_Base.MP1_F10_QUAD_111_TRN_2_DIR
out MP1_F10_QUAD_111_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:721
CMX_top_Base.D_CBL_79_B
out D_CBL_79_Bstd_logic
Definition: CMX_top_Base.vhd:689
CMX_top_Base.P1_8
in P1_8std_logic
Definition: CMX_top_Base.vhd:124
vme_outreg.read_detect
out read_detectstd_logic
Definition: vme_outreg_rtl.vhd:31
CMX_top_Base.D_CBL_59_B
out D_CBL_59_Bstd_logic
Definition: CMX_top_Base.vhd:669
CMX_top_Base.P6_0
in P6_0std_logic
Definition: CMX_top_Base.vhd:241
CMX_top_Base.Behavioral.data_to_vme_test_rw
std_logic_vector (15 downto 0) data_to_vme_test_rw
Definition: CMX_top_Base.vhd:935
CMX_top_Base.BF_DOUT_CTP_46
out BF_DOUT_CTP_46std_logic
Definition: CMX_top_Base.vhd:586
daq_collector.clk
in clkT_SL
Definition: daq_collector.vhd:24
CMX_Memory_spy_inhibit.rd_nwr
in rd_nwrstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:43
CMX_top_Base.P2_18
in P2_18std_logic
Definition: CMX_top_Base.vhd:159
CMX_top_Base.P10_23
in P10_23std_logic
Definition: CMX_top_Base.vhd:364
CMX_top_Base.D_CBL_38_B
out D_CBL_38_Bstd_logic
Definition: CMX_top_Base.vhd:646
CMX_CTP_output_module.start_playback
in start_playbackstd_logic
Definition: CMX_CTP_output_module.vhd:40
CMX_delay_generator.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_delay_generator.vhd:37
SFP_Data_TXRX.DFETAP4
in DFETAP4std_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:67
CMX_CTP_output_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_CTP_output_module.vhd:44
CMX_CTP_output_module
Definition: CMX_CTP_output_module.vhd:27
sys_monitor.BF_SYSMON_03_N
in BF_SYSMON_03_NSTD_LOGIC
Definition: sys_monitor.vhd:31
CMX_top_Base.P11_8
in P11_8std_logic
Definition: CMX_top_Base.vhd:374
CMX_top_Base.BF_DOUT_CTP_04
out BF_DOUT_CTP_04std_logic
Definition: CMX_top_Base.vhd:542
adder_top.numactchan
numactchaninteger :=16
Definition: adder_top_vs.vhd:30
CMX_top_Base.P2_15
in P2_15std_logic
Definition: CMX_top_Base.vhd:156
CMX_top_Base.OCB_A09
in OCB_A09std_logic
Definition: CMX_top_Base.vhd:40
SFP_Data_TXRX.TXN_OUT
out TXN_OUTstd_logic
Definition: SFP_TXRX.vhd:44
CMX_input_module.counter_enable_out
out counter_enable_outstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:41
CMX_top_Base.P8_9
in P8_9std_logic
Definition: CMX_top_Base.vhd:300
sys_monitor.BF_SYSMON_10_P
in BF_SYSMON_10_PSTD_LOGIC
Definition: sys_monitor.vhd:40
CMX_top_Base.BF_DOUT_CTP_65
out BF_DOUT_CTP_65std_logic
Definition: CMX_top_Base.vhd:604
CMX_top_Base.P3_11
in P3_11std_logic
Definition: CMX_top_Base.vhd:177
CMX_top_Base.P11_1
in P11_1std_logic
Definition: CMX_top_Base.vhd:367
CMX_top_Base.BF_DOUT_CTP_55
out BF_DOUT_CTP_55std_logic
Definition: CMX_top_Base.vhd:595
sys_monitor.BF_SYSMON_13_N
in BF_SYSMON_13_NSTD_LOGIC
Definition: sys_monitor.vhd:47
CMX_top_Base.P11_23
in P11_23std_logic
Definition: CMX_top_Base.vhd:389
CMX_input_module.upload_delays
in upload_delaysstd_logic
Definition: CMX_input_module.vhd:45
CMX_top_Base.Behavioral.data_vme_up_top
std_logic_vector (15 downto 0) data_vme_up_top
Definition: CMX_top_Base.vhd:866
CMX_top_Base.P0_8
in P0_8std_logic
Definition: CMX_top_Base.vhd:99
CMX_top_Base.P9_6
in P9_6std_logic
Definition: CMX_top_Base.vhd:322
CMX_top_Base.P4_20
in P4_20std_logic
Definition: CMX_top_Base.vhd:211
vme_inreg_notri.ncs
in ncsstd_logic
Definition: vme_inreg_rtl_notri.vhd:27
CMX_cable_clocked_80Mbps_input_module
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:22
CMX_top_Base.P12_12
in P12_12std_logic
Definition: CMX_top_Base.vhd:403
CMX_top_Base.BF_SYSMON_13_P
in BF_SYSMON_13_PSTD_LOGIC
Definition: CMX_top_Base.vhd:83
CMX_top_Base.BF_DOUT_CTP_19
out BF_DOUT_CTP_19std_logic
Definition: CMX_top_Base.vhd:557
sys_monitor.BF_SYSMON_12_P
in BF_SYSMON_12_PSTD_LOGIC
Definition: sys_monitor.vhd:44
CMX_top_Base.P1_16
in P1_16std_logic
Definition: CMX_top_Base.vhd:132
SFP_Data_TXRX.TXDIFFCTRL_IN
in TXDIFFCTRL_INstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:54
CMX_top_Base.OCB_A14
in OCB_A14std_logic
Definition: CMX_top_Base.vhd:45
CMX_top_Base.P3_23
in P3_23std_logic
Definition: CMX_top_Base.vhd:189
CMX_top_Base.OCB_DS_B
in OCB_DS_Bstd_logic
Definition: CMX_top_Base.vhd:56
CMX_top_Base.OCB_A11
in OCB_A11std_logic
Definition: CMX_top_Base.vhd:42
CMX_top_Base.P6_21
in P6_21std_logic
Definition: CMX_top_Base.vhd:262
adder_top.dout_cbla_mux0
out dout_cbla_mux0std_logic_vector (33 downto 0)
Definition: adder_top_vs.vhd:44
CMX_input_module.buf_clk40_m180o
in buf_clk40_m180ostd_logic
Definition: CMX_input_module.vhd:29
CMX_top_Base.BF_DOUT_CTP_14
out BF_DOUT_CTP_14std_logic
Definition: CMX_top_Base.vhd:552
CMX_crate_cable_output_module.ds
in dsstd_logic
Definition: CMX_crate_cable_output_module.vhd:40
CMX_top_Base.BF_DOUT_CTP_47
out BF_DOUT_CTP_47std_logic
Definition: CMX_top_Base.vhd:587
CMX_top_Base.D_CBL_39_B
in D_CBL_39_Bstd_logic
Definition: CMX_top_Base.vhd:647
CMX_rate_counter_inhibit.buf_clk40
in buf_clk40std_logic
Definition: CMX_rate_counter_inhibit.vhd:33
CMX_input_module
Definition: CMX_input_module.vhd:25
CMX_top_Base.P4_18
in P4_18std_logic
Definition: CMX_top_Base.vhd:209
adder_top.dout_lcl
out dout_lclstd_logic_vector (59 downto 0)
Definition: adder_top_vs.vhd:40
CMX_top_Base.P9_2
in P9_2std_logic
Definition: CMX_top_Base.vhd:318
CMX_top_Base.BF_SYSMON_01_N
in BF_SYSMON_01_NSTD_LOGIC
Definition: CMX_top_Base.vhd:66
vme_outreg_notri_async.width
widthinteger :=16
Definition: vme_outreg_rtl_notri_async.vhd:19
vme_main_hub.data_vme
inout data_vmestd_logic_vector (15 downto 0)
the tri-stated port
Definition: vme_main_hub.vhd:23
CMX_top_Base.P4_14
in P4_14std_logic
Definition: CMX_top_Base.vhd:205
CMX_top_Base.D_CBL_27_B
out D_CBL_27_Bstd_logic
Definition: CMX_top_Base.vhd:635
CMX_top_Base.P10_18
in P10_18std_logic
Definition: CMX_top_Base.vhd:359
CMX_input_module.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:61
CMX_top_Base.P9_21
in P9_21std_logic
Definition: CMX_top_Base.vhd:337
CMX_top_Base.BF_SYSMON_10_N
in BF_SYSMON_10_NSTD_LOGIC
Definition: CMX_top_Base.vhd:78
CMX_top_Base.P15_18
in P15_18std_logic
Definition: CMX_top_Base.vhd:484
CMX_top_Base.OCB_A15
in OCB_A15std_logic
Definition: CMX_top_Base.vhd:46
vme_inreg_async.ds
in dsstd_logic
Definition: vme_inreg_async_rtl.vhd:27
CMX_top_Base.P8_21
in P8_21std_logic
Definition: CMX_top_Base.vhd:312
CMX_CTP_output_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_CTP_output_module.vhd:46
CMX_top_Base.P2_1
in P2_1std_logic
Definition: CMX_top_Base.vhd:142
CMX_top_Base.D_CBL_06_B
out D_CBL_06_Bstd_logic
Definition: CMX_top_Base.vhd:612
CMX_top_Base.P14_17
in P14_17std_logic
Definition: CMX_top_Base.vhd:458
decoder.pos_width
pos_widthinteger :=9
Definition: jet_decoder.vhd:37
CMX_top_Base.BF_LED_REQ_2
out BF_LED_REQ_2std_logic
Definition: CMX_top_Base.vhd:525
glink_interface.RST
in RSTstd_logic
Definition: glink_interface.vhd:21
CMX_top_Base.P7_6
in P7_6std_logic
Definition: CMX_top_Base.vhd:272
adder_top.dout_cblb_mux0
out dout_cblb_mux0std_logic_vector (33 downto 0)
Definition: adder_top_vs.vhd:46
CMX_top_Base.P9_13
in P9_13std_logic
Definition: CMX_top_Base.vhd:329
CMX_top_Base.BF_TO_TP_DAQ_SLINK_RETURN_DIR
in BF_TO_TP_DAQ_SLINK_RETURN_DIRstd_logic
Definition: CMX_top_Base.vhd:693
CMX_top_Base.P9_18
in P9_18std_logic
Definition: CMX_top_Base.vhd:334
vme_inreg_notri.width
widthinteger :=16
Definition: vme_inreg_rtl_notri.vhd:22
CMX_top_Base.D_CBL_76_B
out D_CBL_76_Bstd_logic
Definition: CMX_top_Base.vhd:686
CMX_top_Base.P10_11
in P10_11std_logic
Definition: CMX_top_Base.vhd:352
CMX_CTP_output_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_CTP_output_module.vhd:41
vme_outreg.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl.vhd:17
CMX_top_Base.MP2_F11_QUAD_114_TRN_1_DIR
out MP2_F11_QUAD_114_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:743
CMX_top_Base.D_CBL_01_B
out D_CBL_01_Bstd_logic
Definition: CMX_top_Base.vhd:607
Topo_Data_TX.rd_nwr
in rd_nwrstd_logic
Definition: Topo_Data_TX.vhd:53
vme_inreg_notri_async.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:34
CMX_top_Base.P14_9
in P14_9std_logic
Definition: CMX_top_Base.vhd:450
vme_inreg.width
widthinteger :=16
Definition: vme_inreg_rtl.vhd:22
daq_glink.RAM_rel_offsets
in RAM_rel_offsetsarr_ctr_8bit (18 downto 0)
Definition: daq_glink.vhd:35
CMX_top_Base.P3_16
in P3_16std_logic
Definition: CMX_top_Base.vhd:182
CMX_top_Base.P4_13
in P4_13std_logic
Definition: CMX_top_Base.vhd:204
CMX_top_Base.BF_LED_REQ_0
out BF_LED_REQ_0std_logic
Definition: CMX_top_Base.vhd:523
CMX_top_Base.P2_6
in P2_6std_logic
Definition: CMX_top_Base.vhd:147
CMX_input_module.P
in Pmat_var (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:27
CMX_top_Base.P13_6
in P13_6std_logic
Definition: CMX_top_Base.vhd:422
CMX_system_cable_input_module.buf_clk40_ds2
in buf_clk40_ds2std_logic
Definition: CMX_system_cable_input_module.vhd:36
CMX_top_Base.BF_DOUT_CTP_00
out BF_DOUT_CTP_00std_logic
Definition: CMX_top_Base.vhd:538
CMX_top_Base.P15_19
in P15_19std_logic
Definition: CMX_top_Base.vhd:485
CMX_version
Definition: CMX_version.vhd:19
BCID_counter.BCID_out
out BCID_outstd_logic_vector (11 downto 0)
Definition: BCID_counter.vhd:32
SFP_Data_TXRX.TXPREEMPHASIS_IN
in TXPREEMPHASIS_INstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:52
vme_inreg_notri_async.width
widthinteger :=16
Definition: vme_inreg_rtl_notri_async.vhd:21
vme_inreg.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl.vhd:35
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_114_DIR
in CLK_320MHz64_LHC_BF_QUAD_114_DIRstd_logic
Definition: CMX_top_Base.vhd:759
CMX_top_Base.Behavioral.vme_local_switch
vme_local_switch
Definition: CMX_top_Base.vhd:847
sys_monitor.BF_SYSMON_03_P
in BF_SYSMON_03_PSTD_LOGIC
Definition: sys_monitor.vhd:30
CMX_top_Base.P6_11
in P6_11std_logic
Definition: CMX_top_Base.vhd:252
CMX_top_Base.P1_20
in P1_20std_logic
Definition: CMX_top_Base.vhd:136
CMX_top_Base.P15_15
in P15_15std_logic
Definition: CMX_top_Base.vhd:481
CMX_top_Base.D_CBL_20_B
in D_CBL_20_Bstd_logic
Definition: CMX_top_Base.vhd:626
CMX_top_Base.P14_6
in P14_6std_logic
Definition: CMX_top_Base.vhd:447
CMX_top_Base.P3_15
in P3_15std_logic
Definition: CMX_top_Base.vhd:181
CMX_top_Base.P5_4
in P5_4std_logic
Definition: CMX_top_Base.vhd:220
CMX_top_Base.P4_17
in P4_17std_logic
Definition: CMX_top_Base.vhd:208
CMX_top_Base.P1_18
in P1_18std_logic
Definition: CMX_top_Base.vhd:134
CMX_top_Base.Behavioral.data_to_vme_outreg_test
std_logic_vector (15 downto 0) data_to_vme_outreg_test
Definition: CMX_top_Base.vhd:813
CMX_top_Base.MP2_F07_QUAD_113_TRN_2_DIR
out MP2_F07_QUAD_113_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:737
CMX_top_Base.RXP_IN
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: CMX_top_Base.vhd:763
CMX_clock_manager.I_DS1
in I_DS1std_logic
Definition: CMX_clock_manager.vhd:30
CMX_delay_generator.del_register
out del_registerdel_register_type
Definition: CMX_delay_generator.vhd:41
CMX_top_Base.P5_2
in P5_2std_logic
Definition: CMX_top_Base.vhd:218
CMX_top_Base.D_CBL_58_B
out D_CBL_58_Bstd_logic
Definition: CMX_top_Base.vhd:668
Topo_Data_TX
Definition: Topo_Data_TX.vhd:23
CMX_top_Base.BF_DOUT_CTP_49
out BF_DOUT_CTP_49std_logic
Definition: CMX_top_Base.vhd:589
CMX_top_Base.P14_10
in P14_10std_logic
Definition: CMX_top_Base.vhd:451
sys_monitor.BF_SYSMON_09_N
in BF_SYSMON_09_NSTD_LOGIC
Definition: sys_monitor.vhd:39
CMX_top_Base.P7_7
in P7_7std_logic
Definition: CMX_top_Base.vhd:273
CMX_top_Base.P12_23
in P12_23std_logic
Definition: CMX_top_Base.vhd:414
CMX_top_Base.P10_15
in P10_15std_logic
Definition: CMX_top_Base.vhd:356
sys_monitor.BF_SYSMON_13_P
in BF_SYSMON_13_PSTD_LOGIC
Definition: sys_monitor.vhd:46
CMX_clock_manager.pll_locked
out pll_lockedstd_logic
Definition: CMX_clock_manager.vhd:39
CMX_top_Base.BF_DEBUG_7
out BF_DEBUG_7std_logic
Definition: CMX_top_Base.vhd:513
CMX_cable_clocked_80Mbps_input_module.numbits_in_cable_connector
numbits_in_cable_connectorinteger
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:24
CMX_crate_cable_output_module.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_crate_cable_output_module.vhd:42
SFP_Data_TXRX.TXP_OUT
out TXP_OUTstd_logic
Definition: SFP_TXRX.vhd:45
CMX_top_Base.P9_11
in P9_11std_logic
Definition: CMX_top_Base.vhd:327
CMX_top_Base.P0_11
in P0_11std_logic
Definition: CMX_top_Base.vhd:102
CMX_clock_manager.buf_clk320
out buf_clk320std_logic
Definition: CMX_clock_manager.vhd:36
CMX_delay_generator
Definition: CMX_delay_generator.vhd:28
CMX_top_Base.BF_DOUT_CTP_64
out BF_DOUT_CTP_64std_logic
Definition: CMX_top_Base.vhd:570
BCID_counter.ds
in dsstd_logic
Definition: BCID_counter.vhd:36
CMX_top_Base.P7_3
in P7_3std_logic
Definition: CMX_top_Base.vhd:269
CMX_top_Base.MP1_F04_QUAD_112_TRN_0_CMP
out MP1_F04_QUAD_112_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:726
CMX_top_Base.P1_1
in P1_1std_logic
Definition: CMX_top_Base.vhd:117
CMX_system_cable_input_module
Definition: CMX_system_cable_input_module.vhd:28
CMX_top_Base.P5_14
in P5_14std_logic
Definition: CMX_top_Base.vhd:230
CMX_top_Base.P14_7
in P14_7std_logic
Definition: CMX_top_Base.vhd:448
SFP_Data_TXRX.DFECLKDLYADJMON
out DFECLKDLYADJMONstd_logic_vector (5 downto 0)
Definition: SFP_TXRX.vhd:57
CMX_top_Base.P2_19
in P2_19std_logic
Definition: CMX_top_Base.vhd:160
daq_collector.BCID_delayed
out BCID_delayedstd_logic_vector (11 downto 0)
Definition: daq_collector.vhd:34
CMX_top_Base.P8_16
in P8_16std_logic
Definition: CMX_top_Base.vhd:307
CMX_top_Base.BF_SYSMON_15_P
in BF_SYSMON_15_PSTD_LOGIC
Definition: CMX_top_Base.vhd:87
vme_inreg_async
Definition: vme_inreg_async_rtl.vhd:18
CMX_input_module.del_register
in del_registerdel_register_type
Definition: CMX_input_module.vhd:44
CMX_top_Base.D_CBL_21_B
out D_CBL_21_Bstd_logic
Definition: CMX_top_Base.vhd:627
CMX_Memory_spy_inhibit.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_Memory_spy_inhibit.vhd:47
CMX_top_Base.D_CBL_04_B
out D_CBL_04_Bstd_logic
Definition: CMX_top_Base.vhd:610
CMX_top_Base.BF_SYSMON_03_N
in BF_SYSMON_03_NSTD_LOGIC
Definition: CMX_top_Base.vhd:68
vme_inreg_async.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_async_rtl.vhd:33
CMX_top_Base.P12_24
in P12_24std_logic
Definition: CMX_top_Base.vhd:415
CMX_top_Base.BF_ROI_DATA_OUT_DIR
out BF_ROI_DATA_OUT_DIRstd_logic
Definition: CMX_top_Base.vhd:706
CMX_top_Base.P0_18
in P0_18std_logic
Definition: CMX_top_Base.vhd:109
CMX_top_Base.P15_0
in P15_0std_logic
Definition: CMX_top_Base.vhd:466
CMX_top_Base.P2_3
in P2_3std_logic
Definition: CMX_top_Base.vhd:144
CMX_top_Base.P5_24
in P5_24std_logic
Definition: CMX_top_Base.vhd:240
vme_inreg_notri.clk
in clkstd_logic
Definition: vme_inreg_rtl_notri.vhd:25
vme_inreg_async.width
widthinteger :=16
Definition: vme_inreg_async_rtl.vhd:21
CMX_top_Base.P15_2
in P15_2std_logic
Definition: CMX_top_Base.vhd:468
CMX_top_Base.P12_19
in P12_19std_logic
Definition: CMX_top_Base.vhd:410
CMX_top_Base.P8_8
in P8_8std_logic
Definition: CMX_top_Base.vhd:299
decoder.rd_nwr
in rd_nwrstd_logic
Definition: jet_decoder.vhd:65
CMX_top_Base.P6_7
in P6_7std_logic
Definition: CMX_top_Base.vhd:248
CMX_top_Base.P12_0
in P12_0std_logic
Definition: CMX_top_Base.vhd:391
vme_inreg.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl.vhd:21
daq_collector
Definition: daq_collector.vhd:22
SFP_Data_TXRX.clk120_in
in clk120_instd_logic
Definition: SFP_TXRX.vhd:49
daq_collector.din_lcl_ro
in din_lcl_roT_SL
Definition: daq_collector.vhd:29
CMX_top_Base.P12_17
in P12_17std_logic
Definition: CMX_top_Base.vhd:408
sys_monitor.BF_SYSMON_11_N
in BF_SYSMON_11_NSTD_LOGIC
Definition: sys_monitor.vhd:43
CMX_top_Base.P13_9
in P13_9std_logic
Definition: CMX_top_Base.vhd:425
vme_local_switch.data_vme_from_below
in data_vme_from_belowarr_16
--! inputs from local registers and from
Definition: vme_local_switch.vhd:35
glink_interface.CLK_40MHz
in CLK_40MHzstd_logic
Definition: glink_interface.vhd:19
vme_inreg_notri.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri.vhd:36
glink_interface
Definition: glink_interface.vhd:17
daq_collector.din_cbl
in din_cblT_SLV65
Definition: daq_collector.vhd:26
CMX_top_Base.D_CBL_80_B
out D_CBL_80_Bstd_logic
Definition: CMX_top_Base.vhd:690
vme_inreg.ncs
in ncsstd_logic
Definition: vme_inreg_rtl.vhd:27
Topo_Data_TX.ds
in dsstd_logic
Definition: Topo_Data_TX.vhd:54
SFP_Data_TXRX.GTXTEST_diag
out GTXTEST_diagstd_logic
Definition: SFP_TXRX.vhd:41
vme_main_hub.bus_drive_from_below
in bus_drive_from_belowstd_logic
--! a request to drive the outside
Definition: vme_main_hub.vhd:32
CMX_top_Base.P14_12
in P14_12std_logic
Definition: CMX_top_Base.vhd:453
CMX_top_Base
Definition: CMX_top_Base.vhd:23
CMX_version.ncs
in ncsstd_logic
Definition: CMX_version.vhd:22
CMX_version.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_version.vhd:25
CMX_top_Base.P12_2
in P12_2std_logic
Definition: CMX_top_Base.vhd:393
CMX_top_Base.D_CBL_29_B
out D_CBL_29_Bstd_logic
Definition: CMX_top_Base.vhd:637
CMX_top_Base.D_CBL_57_B
out D_CBL_57_Bstd_logic
Definition: CMX_top_Base.vhd:667
CMX_top_Base.MP1_F01_QUAD_110_TRN_0_DIR
out MP1_F01_QUAD_110_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:709
sys_monitor.BF_SYSMON_07_N
in BF_SYSMON_07_NSTD_LOGIC
Definition: sys_monitor.vhd:35
CMX_cable_clocked_80Mbps_input_module.forwarded_clock
out forwarded_clockstd_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:28
CMX_top_Base.BF_DOUT_CTP_05
out BF_DOUT_CTP_05std_logic
Definition: CMX_top_Base.vhd:543
CMX_delay_generator.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_delay_generator.vhd:38
CMX_top_Base.BF_DEBUG_4
out BF_DEBUG_4std_logic
Definition: CMX_top_Base.vhd:510
CMX_top_Base.D_CBL_14_B
out D_CBL_14_Bstd_logic
Definition: CMX_top_Base.vhd:620
CMX_clock_manager.ds
in dsstd_logic
Definition: CMX_clock_manager.vhd:46
CMX_top_Base.P10_6
in P10_6std_logic
Definition: CMX_top_Base.vhd:347
CMX_delay_generator.rd_nwr
in rd_nwrstd_logic
Definition: CMX_delay_generator.vhd:35
CMX_cable_clocked_80Mbps_input_module.upload_delays
in upload_delaysstd_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:34
CMX_top_Base.BF_DOUT_CTP_50
out BF_DOUT_CTP_50std_logic
Definition: CMX_top_Base.vhd:590
CMX_top_Base.P1_0
in P1_0std_logic
Definition: CMX_top_Base.vhd:116
CMX_top_Base.P12_9
in P12_9std_logic
Definition: CMX_top_Base.vhd:400
daq_collector.BCID_in
in BCID_instd_logic_vector (11 downto 0)
Definition: daq_collector.vhd:33
CMX_top_Base.P8_20
in P8_20std_logic
Definition: CMX_top_Base.vhd:311
CMX_top_Base.P13_2
in P13_2std_logic
Definition: CMX_top_Base.vhd:418
CMX_top_Base.P13_4
in P13_4std_logic
Definition: CMX_top_Base.vhd:420
CMX_top_Base.P11_6
in P11_6std_logic
Definition: CMX_top_Base.vhd:372
CMX_top_Base.BF_SYSMON_14_N
in BF_SYSMON_14_NSTD_LOGIC
Definition: CMX_top_Base.vhd:86
sys_monitor.BF_SYSMON_01_N
in BF_SYSMON_01_NSTD_LOGIC
Definition: sys_monitor.vhd:29
CMX_top_Base.MP2_F04_QUAD_115_TRN_0_CMP
out MP2_F04_QUAD_115_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:750
vme_outreg_notri.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri.vhd:27
adder_top.dout_lcl_ro
out dout_lcl_roT_SL
Definition: adder_top_vs.vhd:41
CMX_top_Base.P8_1
in P8_1std_logic
Definition: CMX_top_Base.vhd:292
CMX_top_Base.CLK_40MHz08_DSKW_2_BF_LOGIC_CMP
in CLK_40MHz08_DSKW_2_BF_LOGIC_CMPstd_logic
Definition: CMX_top_Base.vhd:500
CMX_top_Base.BF_SYSMON_04_N
in BF_SYSMON_04_NSTD_LOGIC
Definition: CMX_top_Base.vhd:70
CMX_top_Base.P0_15
in P0_15std_logic
Definition: CMX_top_Base.vhd:106
vme_inreg_notri_async.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:30
adder_top.ncs
in ncsstd_logic
Definition: adder_top_vs.vhd:49
CMX_clock_manager.buf_clk40_m180o
out buf_clk40_m180ostd_logic
Definition: CMX_clock_manager.vhd:34
CMX_input_module.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:62
CMX_top_Base.P12_11
in P12_11std_logic
Definition: CMX_top_Base.vhd:402
CMX_top_Base.BF_SYSMON_12_P
in BF_SYSMON_12_PSTD_LOGIC
Definition: CMX_top_Base.vhd:81
CMX_top_Base.MP2_F04_QUAD_115_TRN_0_DIR
out MP2_F04_QUAD_115_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:749
vme_inreg.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl.vhd:31
CMX_top_Base.P3_22
in P3_22std_logic
Definition: CMX_top_Base.vhd:188
sys_monitor.ncs
in ncsstd_logic
Definition: sys_monitor.vhd:53
CMX_top_Base.Behavioral.vme_address
std_logic_vector (23 downto 1) vme_address
Definition: CMX_top_Base.vhd:795
CMX_top_Base.P3_2
in P3_2std_logic
Definition: CMX_top_Base.vhd:168
CMX_top_Base.BF_DOUT_CTP_57
out BF_DOUT_CTP_57std_logic
Definition: CMX_top_Base.vhd:597
CMX_top_Base.P14_1
in P14_1std_logic
Definition: CMX_top_Base.vhd:442
CMX_top_Base.D_CBL_25_B
out D_CBL_25_Bstd_logic
Definition: CMX_top_Base.vhd:631
CMX_top_Base.P10_19
in P10_19std_logic
Definition: CMX_top_Base.vhd:360
CMX_top_Base.Behavioral.sys_monitor
sys_monitor
Definition: CMX_top_Base.vhd:961
CMX_top_Base.BF_DOUT_CTP_42
out BF_DOUT_CTP_42std_logic
Definition: CMX_top_Base.vhd:582
CMX_top_Base.P3_13
in P3_13std_logic
Definition: CMX_top_Base.vhd:179
CMX_top_Base.P15_24
in P15_24std_logic
Definition: CMX_top_Base.vhd:490
CMX_top_Base.P9_22
in P9_22std_logic
Definition: CMX_top_Base.vhd:338
CMX_top_Base.OCB_A12
in OCB_A12std_logic
Definition: CMX_top_Base.vhd:43
CMX_top_Base.P3_4
in P3_4std_logic
Definition: CMX_top_Base.vhd:170
CMX_top_Base.P6_18
in P6_18std_logic
Definition: CMX_top_Base.vhd:259
sys_monitor.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: sys_monitor.vhd:56
CMX_system_cable_input_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_system_cable_input_module.vhd:45
decoder.max_tobs_tot
max_tobs_totinteger :=64
Definition: jet_decoder.vhd:31
CMX_top_Base.P3_0
in P3_0std_logic
Definition: CMX_top_Base.vhd:166
CMX_clock_manager.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_clock_manager.vhd:48
Topo_Data_TX.send_align
in send_alignstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:41
BCID_counter.rd_nwr
in rd_nwrstd_logic
Definition: BCID_counter.vhd:35
CMX_top_Base.P2_17
in P2_17std_logic
Definition: CMX_top_Base.vhd:158
CMX_top_Base.P2_13
in P2_13std_logic
Definition: CMX_top_Base.vhd:154
adder_top.dout
out doutT_SLV62
Definition: adder_top_vs.vhd:42
CMX_top_Base.OCB_A07
in OCB_A07std_logic
Definition: CMX_top_Base.vhd:38
CMX_top_Base.P10_9
in P10_9std_logic
Definition: CMX_top_Base.vhd:350
CMX_top_Base.BF_DOUT_CTP_51
out BF_DOUT_CTP_51std_logic
Definition: CMX_top_Base.vhd:591
vme_outreg.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl.vhd:30
CMX_top_Base.D_CBL_33_B
out D_CBL_33_Bstd_logic
Definition: CMX_top_Base.vhd:641
CMX_top_Base.BF_DOUT_CTP_54
out BF_DOUT_CTP_54std_logic
Definition: CMX_top_Base.vhd:594
CMX_top_Base.OCB_A03
in OCB_A03std_logic
Definition: CMX_top_Base.vhd:34
CMX_top_Base.MP1_F02_QUAD_112_TRN_2_DIR
out MP1_F02_QUAD_112_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:729
CMX_top_Base.BF_TO_FROM_BSPT_1
in BF_TO_FROM_BSPT_1std_logic
Definition: CMX_top_Base.vhd:529
CMX_top_Base.OCB_A22
in OCB_A22std_logic
Definition: CMX_top_Base.vhd:53
CMX_top_Base.BF_DOUT_CTP_45
out BF_DOUT_CTP_45std_logic
Definition: CMX_top_Base.vhd:585
sys_monitor.BF_SYSMON_07_P
in BF_SYSMON_07_PSTD_LOGIC
Definition: sys_monitor.vhd:34
CMX_top_Base.P4_22
in P4_22std_logic
Definition: CMX_top_Base.vhd:213
vme_main_hub
Definition: vme_main_hub.vhd:21
Topo_Data_TX.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:57
decoder.BCID_delayed
out BCID_delayedstd_logic_vector (11 downto 0)
Definition: jet_decoder.vhd:57
vme_inreg_notri.write_detect
out write_detectstd_logic
Definition: vme_inreg_rtl_notri.vhd:40
CMX_top_Base.P10_10
in P10_10std_logic
Definition: CMX_top_Base.vhd:351
CMX_top_Base.P12_20
in P12_20std_logic
Definition: CMX_top_Base.vhd:411
CMX_top_Base.P14_8
in P14_8std_logic
Definition: CMX_top_Base.vhd:449
CMX_top_Base.MP2_F08_QUAD_114_TRN_3_DIR
out MP2_F08_QUAD_114_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:747
CMX_top_Base.P0_10
in P0_10std_logic
Definition: CMX_top_Base.vhd:101
CMX_top_Base.P6_14
in P6_14std_logic
Definition: CMX_top_Base.vhd:255
CMX_top_Base.Behavioral.data_vme_from_below_top
arr_16 (1762 downto 0) data_vme_from_below_top
Definition: CMX_top_Base.vhd:863
adder_top.din_cbl_ro
in din_cbl_roT_SL
Definition: adder_top_vs.vhd:39
CMX_top_Base.P5_16
in P5_16std_logic
Definition: CMX_top_Base.vhd:232
CMX_top_Base.P3_8
in P3_8std_logic
Definition: CMX_top_Base.vhd:174
CMX_BASE_VME_BSPT.n_ds0_int
in n_ds0_intstd_logic
Definition: cmx_base_vme_bspt.vhd:28
CMX_top_Base.P13_19
in P13_19std_logic
Definition: CMX_top_Base.vhd:435
CMX_top_Base.BF_DOUT_CTP_60
out BF_DOUT_CTP_60std_logic
Definition: CMX_top_Base.vhd:600
CMX_top_Base.Behavioral.bus_drive_up_top
std_logic bus_drive_up_top
Definition: CMX_top_Base.vhd:865
CMX_top_Base.P4_19
in P4_19std_logic
Definition: CMX_top_Base.vhd:210
vme_inreg_notri_async.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl_notri_async.vhd:20
adder_top.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: adder_top_vs.vhd:54
CMX_top_Base.P4_23
in P4_23std_logic
Definition: CMX_top_Base.vhd:214
SFP_Data_TXRX.gtx_reset
in gtx_resetstd_logic
Definition: SFP_TXRX.vhd:34
CMX_top_Base.BF_DOUT_CTP_07
out BF_DOUT_CTP_07std_logic
Definition: CMX_top_Base.vhd:545
CMX_top_Base.BF_TO_FROM_BSPT_5
out BF_TO_FROM_BSPT_5std_logic
Definition: CMX_top_Base.vhd:533
CMX_top_Base.MP2_F01_QUAD_113_TRN_0_DIR
out MP2_F01_QUAD_113_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:733
CMX_top_Base.P11_2
in P11_2std_logic
Definition: CMX_top_Base.vhd:368
CMX_top_Base.P2_0
in P2_0std_logic
Definition: CMX_top_Base.vhd:141
CMX_top_Base.D_CBL_07_B
out D_CBL_07_Bstd_logic
Definition: CMX_top_Base.vhd:613
vme_outreg
Definition: vme_outreg_rtl.vhd:15
CMX_top_Base.P15_10
in P15_10std_logic
Definition: CMX_top_Base.vhd:476
SFP_Data_TXRX.local_mmcm_reset_diag
out local_mmcm_reset_diagstd_logic
Definition: SFP_TXRX.vhd:40
CMX_Memory_spy_inhibit.ncs
in ncsstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:42
vme_inreg.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl.vhd:36
CMX_top_Base.D_CBL_62_B
out D_CBL_62_Bstd_logic
Definition: CMX_top_Base.vhd:672
CMX_input_module.quiet
in quietstd_logic
Definition: CMX_input_module.vhd:48
CMX_top_Base.P12_3
in P12_3std_logic
Definition: CMX_top_Base.vhd:394
SFP_Data_TXRX.DFETAP3
in DFETAP3std_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:65
CMX_crate_cable_output_module
Definition: CMX_crate_cable_output_module.vhd:24
CMX_top_Base.P13_24
in P13_24std_logic
Definition: CMX_top_Base.vhd:440
CMX_system_cable_input_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_system_cable_input_module.vhd:35
CMX_top_Base.OCB_A16
in OCB_A16std_logic
Definition: CMX_top_Base.vhd:47
CMX_top_Base.P7_2
in P7_2std_logic
Definition: CMX_top_Base.vhd:268
vme_inreg_notri
Definition: vme_inreg_rtl_notri.vhd:19
CMX_top_Base.P1_5
in P1_5std_logic
Definition: CMX_top_Base.vhd:121
CMX_top_Base.P4_24
in P4_24std_logic
Definition: CMX_top_Base.vhd:215
CMX_top_Base.MP1_F07_QUAD_110_TRN_2_CMP
out MP1_F07_QUAD_110_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:714
CMX_top_Base.Behavioral.start_playback
std_logic start_playback
Definition: CMX_top_Base.vhd:941
vme_inreg_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_async_rtl.vhd:29
CMX_top_Base.P12_8
in P12_8std_logic
Definition: CMX_top_Base.vhd:399
CMX_top_Base.P2_24
in P2_24std_logic
Definition: CMX_top_Base.vhd:165
CMX_top_Base.BF_SYSMON_09_P
in BF_SYSMON_09_PSTD_LOGIC
Definition: CMX_top_Base.vhd:75
vme_inreg_async.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_async_rtl.vhd:20
CMX_top_Base.P4_9
in P4_9std_logic
Definition: CMX_top_Base.vhd:200
SFP_Data_TXRX.DFEEYEDACMON
out DFEEYEDACMONstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:59
CMX_crate_cable_output_module.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_crate_cable_output_module.vhd:43
CMX_top_Base.Behavioral.ds
std_logic ds
Definition: CMX_top_Base.vhd:792
CMX_top_Base.BF_DOUT_CTP_17
out BF_DOUT_CTP_17std_logic
Definition: CMX_top_Base.vhd:555
vme_outreg_notri.ncs
in ncsstd_logic
Definition: vme_outreg_rtl_notri.vhd:22
CMX_top_Base.D_CBL_09_B
out D_CBL_09_Bstd_logic
Definition: CMX_top_Base.vhd:615
CMX_top_Base.P7_17
in P7_17std_logic
Definition: CMX_top_Base.vhd:283
CMX_top_Base.BF_SYSMON_01_P
in BF_SYSMON_01_PSTD_LOGIC
Definition: CMX_top_Base.vhd:65
CMX_BASE_VME_BSPT.geoadd_0
in geoadd_0std_logic
Definition: cmx_base_vme_bspt.vhd:27
CMX_input_module.start_playback
in start_playbackstd_logic
Definition: CMX_input_module.vhd:51
CMX_top_Base.BF_DOUT_CTP_31
out BF_DOUT_CTP_31std_logic
Definition: CMX_top_Base.vhd:569
CMX_top_Base.BF_DOUT_CTP_38
out BF_DOUT_CTP_38std_logic
Definition: CMX_top_Base.vhd:578
CMX_top_Base.D_CBL_22_B
out D_CBL_22_Bstd_logic
Definition: CMX_top_Base.vhd:628
CMX_top_Base.P1_24
in P1_24std_logic
Definition: CMX_top_Base.vhd:140
CMX_top_Base.BF_DOUT_CTP_37
out BF_DOUT_CTP_37std_logic
Definition: CMX_top_Base.vhd:577
CMX_top_Base.P10_14
in P10_14std_logic
Definition: CMX_top_Base.vhd:355
CMX_top_Base.P1_23
in P1_23std_logic
Definition: CMX_top_Base.vhd:139
CMX_clock_manager.bus_drive
out bus_drivestd_logic
Definition: CMX_clock_manager.vhd:50
CMX_top_Base.MP2_F08_QUAD_114_TRN_3_CMP
out MP2_F08_QUAD_114_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:748
CMX_top_Base.P11_10
in P11_10std_logic
Definition: CMX_top_Base.vhd:376
CMX_top_Base.D_CBL_83_B
out D_CBL_83_Bstd_logic
Definition: CMX_top_Base.vhd:691
CMX_top_Base.P6_3
in P6_3std_logic
Definition: CMX_top_Base.vhd:244
CMX_Memory_spy_inhibit.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_Memory_spy_inhibit.vhd:45
CMX_top_Base.BF_DEBUG_8
out BF_DEBUG_8std_logic
Definition: CMX_top_Base.vhd:514
decoder.ds
in dsstd_logic
Definition: jet_decoder.vhd:66
CMX_top_Base.BF_DOUT_CTP_29
out BF_DOUT_CTP_29std_logic
Definition: CMX_top_Base.vhd:567
SFP_Data_TXRX.DFEDLYOVRD
in DFEDLYOVRDstd_logic
Definition: SFP_TXRX.vhd:58
sys_monitor.ds
in dsstd_logic
Definition: sys_monitor.vhd:55
decoder.thresholds_num
thresholds_numinteger :=25
Definition: jet_decoder.vhd:38
CMX_top_Base.BF_REQ_CABLE_3_INPUT
out BF_REQ_CABLE_3_INPUTstd_logic
Definition: CMX_top_Base.vhd:522
CMX_top_Base.D_CBL_82_B
out D_CBL_82_Bstd_logic
Definition: CMX_top_Base.vhd:662
CMX_top_Base.BF_DOUT_CTP_35
out BF_DOUT_CTP_35std_logic
Definition: CMX_top_Base.vhd:575
CMX_top_Base.D_CBL_69_B
out D_CBL_69_Bstd_logic
Definition: CMX_top_Base.vhd:679
CMX_top_Base.P3_1
in P3_1std_logic
Definition: CMX_top_Base.vhd:167
daq_glink.nslices
in nslicesunsigned (7 downto 0)
Definition: daq_glink.vhd:36
CMX_top_Base.BF_DOUT_CTP_26
out BF_DOUT_CTP_26std_logic
Definition: CMX_top_Base.vhd:564
CMX_top_Base.P14_4
in P14_4std_logic
Definition: CMX_top_Base.vhd:445
CMX_top_Base.BF_DOUT_CTP_39
out BF_DOUT_CTP_39std_logic
Definition: CMX_top_Base.vhd:579
CMX_top_Base.P4_15
in P4_15std_logic
Definition: CMX_top_Base.vhd:206
Topo_Data_TX.GTX_RX_READY_OUT
out GTX_RX_READY_OUTstd_logic
Definition: Topo_Data_TX.vhd:32
CMX_top_Base.P1_22
in P1_22std_logic
Definition: CMX_top_Base.vhd:138
CMX_top_Base.BF_DOUT_CTP_23
out BF_DOUT_CTP_23std_logic
Definition: CMX_top_Base.vhd:561
CMX_top_Base.P15_23
in P15_23std_logic
Definition: CMX_top_Base.vhd:489
SFP_Data_TXRX.DFECLKDLYADJ
in DFECLKDLYADJstd_logic_vector (5 downto 0)
Definition: SFP_TXRX.vhd:56
CMX_top_Base.P6_8
in P6_8std_logic
Definition: CMX_top_Base.vhd:249
CMX_top_Base.P5_0
in P5_0std_logic
Definition: CMX_top_Base.vhd:216
CMX_top_Base.P1_15
in P1_15std_logic
Definition: CMX_top_Base.vhd:131
CMX_top_Base.MP2_F09_QUAD_114_TRN_0_DIR
out MP2_F09_QUAD_114_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:741
CMX_top_Base.BF_DOUT_CTP_16
out BF_DOUT_CTP_16std_logic
Definition: CMX_top_Base.vhd:554
CMX_input_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_input_module.vhd:31
CMX_clock_manager.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_clock_manager.vhd:49
CMX_top_Base.P4_8
in P4_8std_logic
Definition: CMX_top_Base.vhd:199
CMX_top_Base.P4_4
in P4_4std_logic
Definition: CMX_top_Base.vhd:195
vme_inreg_notri_async.ncs
in ncsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:25
CMX_top_Base.P3_7
in P3_7std_logic
Definition: CMX_top_Base.vhd:173
SFP_Data_TXRX.local_pll_lock_out
out local_pll_lock_outstd_logic
Definition: SFP_TXRX.vhd:35
CMX_rate_counter_inhibit.bus_drive
out bus_drivestd_logic
Definition: CMX_rate_counter_inhibit.vhd:41
CMX_top_Base.P5_11
in P5_11std_logic
Definition: CMX_top_Base.vhd:227
CMX_top_Base.P10_12
in P10_12std_logic
Definition: CMX_top_Base.vhd:353
CMX_top_Base.P5_18
in P5_18std_logic
Definition: CMX_top_Base.vhd:234
CMX_top_Base.D_CBL_03_B
out D_CBL_03_Bstd_logic
Definition: CMX_top_Base.vhd:609
CMX_top_Base.P10_13
in P10_13std_logic
Definition: CMX_top_Base.vhd:354
CMX_top_Base.P0_13
in P0_13std_logic
Definition: CMX_top_Base.vhd:104
CMX_rate_counter_inhibit.ncs
in ncsstd_logic
Definition: CMX_rate_counter_inhibit.vhd:35
CMX_top_Base.P8_3
in P8_3std_logic
Definition: CMX_top_Base.vhd:294
CMX_top_Base.Behavioral.counter_values
std_logic_vector (numactchan - 1 downto 0) counter_values
Definition: CMX_top_Base.vhd:1027
CMX_system_cable_input_module.ddr_data_in
in ddr_data_inarr_RTM (num_RTM_cables - 1 downto 0)
Definition: CMX_system_cable_input_module.vhd:34
adder_top.dout_cbla_mux1
out dout_cbla_mux1std_logic_vector (33 downto 0)
Definition: adder_top_vs.vhd:45
sys_monitor.BF_SYSMON_10_N
in BF_SYSMON_10_NSTD_LOGIC
Definition: sys_monitor.vhd:41
CMX_delay_generator.upload_delays
out upload_delaysstd_logic
Definition: CMX_delay_generator.vhd:42
SFP_Data_TXRX.RXN_IN
in RXN_INstd_logic
Definition: SFP_TXRX.vhd:42
CMX_top_Base.P0_19
in P0_19std_logic
Definition: CMX_top_Base.vhd:110
CMX_top_Base.D_CBL_54_B
out D_CBL_54_Bstd_logic
Definition: CMX_top_Base.vhd:664
CMX_top_Base.P7_0
in P7_0std_logic
Definition: CMX_top_Base.vhd:266
decoder.clk40MHz_m90o
in clk40MHz_m90ostd_logic
Definition: jet_decoder.vhd:43
CMX_top_Base.D_CBL_30_B
out D_CBL_30_Bstd_logic
Definition: CMX_top_Base.vhd:638
CMX_top_Base.P3_10
in P3_10std_logic
Definition: CMX_top_Base.vhd:176
CMX_CTP_output_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_CTP_output_module.vhd:36
CMX_top_Base.P12_7
in P12_7std_logic
Definition: CMX_top_Base.vhd:398
CMX_input_module.counter_values
out counter_valuesstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:42
CMX_clock_manager.ncs
in ncsstd_logic
Definition: CMX_clock_manager.vhd:44
CMX_top_Base.P7_15
in P7_15std_logic
Definition: CMX_top_Base.vhd:281
vme_outreg_notri.ds
in dsstd_logic
Definition: vme_outreg_rtl_notri.vhd:24
CMX_top_Base.P3_24
in P3_24std_logic
Definition: CMX_top_Base.vhd:190
CMX_top_Base.P13_22
in P13_22std_logic
Definition: CMX_top_Base.vhd:438
vme_main_hub.data_vme_going_below
out data_vme_going_belowstd_logic_vector (15 downto 0)
Definition: vme_main_hub.vhd:34
CMX_top_Base.P14_5
in P14_5std_logic
Definition: CMX_top_Base.vhd:446
SFP_Data_TXRX.TXPOSTEMPHASIS_IN
in TXPOSTEMPHASIS_INstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:53
CMX_BASE_VME_BSPT.vme_address
in vme_addressstd_logic_vector (23 downto 1)
Definition: cmx_base_vme_bspt.vhd:30
CMX_top_Base.D_CBL_23_B
out D_CBL_23_Bstd_logic
Definition: CMX_top_Base.vhd:629
CMX_top_Base.Behavioral.start_playback_r1
std_logic start_playback_r1
Definition: CMX_top_Base.vhd:941
CMX_top_Base.D_CBL_73_B
out D_CBL_73_Bstd_logic
Definition: CMX_top_Base.vhd:683
BCID_counter.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: BCID_counter.vhd:39
CMX_top_Base.Behavioral.data_vme_going_below
std_logic_vector (15 downto 0) data_vme_going_below
Definition: CMX_top_Base.vhd:867
CMX_top_Base.P0_17
in P0_17std_logic
Definition: CMX_top_Base.vhd:108
vme_outreg_notri.width
widthinteger :=16
Definition: vme_outreg_rtl_notri.vhd:17
CMX_CTP_output_module.ncs
in ncsstd_logic
Definition: CMX_CTP_output_module.vhd:43
CMX_top_Base.P15_20
in P15_20std_logic
Definition: CMX_top_Base.vhd:486
CMX_top_Base.P4_10
in P4_10std_logic
Definition: CMX_top_Base.vhd:201
vme_inreg_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_async_rtl.vhd:34
vme_outreg_notri.bus_drive
out bus_drivestd_logic
Definition: vme_outreg_rtl_notri.vhd:28
CMX_top_Base.P11_14
in P11_14std_logic
Definition: CMX_top_Base.vhd:380
CMX_delay_generator.bus_drive
out bus_drivestd_logic
Definition: CMX_delay_generator.vhd:40
CMX_top_Base.P2_11
in P2_11std_logic
Definition: CMX_top_Base.vhd:152
CMX_top_Base.MP1_F00_QUAD_112_TRN_3_CMP
out MP1_F00_QUAD_112_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:732
CMX_top_Base.Behavioral.IOB
string IOB
Definition: CMX_top_Base.vhd:774
SFP_Data_TXRX.direction
directionstd_logic
Definition: SFP_TXRX.vhd:24
CMX_top_Base.P9_4
in P9_4std_logic
Definition: CMX_top_Base.vhd:320
CMX_top_Base.P5_7
in P5_7std_logic
Definition: CMX_top_Base.vhd:223
CMX_top_Base.Behavioral.quiet
std_logic quiet
Definition: CMX_top_Base.vhd:1033
CMX_top_Base.BF_DOUT_CTP_28
out BF_DOUT_CTP_28std_logic
Definition: CMX_top_Base.vhd:566
vme_inreg_notri_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:35
vme_outreg.width
widthinteger :=16
Definition: vme_outreg_rtl.vhd:18
CMX_top_Base.P7_16
in P7_16std_logic
Definition: CMX_top_Base.vhd:282
Topo_Data_TX.GTXRXRESET_IN
in GTXRXRESET_INstd_logic
Definition: Topo_Data_TX.vhd:30
Topo_Data_TX.MGTREFCLK_PAD_P_IN
in MGTREFCLK_PAD_P_INstd_logic_vector (num_GTX_groups - 1 downto 0)
Definition: Topo_Data_TX.vhd:28
sys_monitor.BF_SYSMON_04_N
in BF_SYSMON_04_NSTD_LOGIC
Definition: sys_monitor.vhd:33
CMX_top_Base.P11_19
in P11_19std_logic
Definition: CMX_top_Base.vhd:385
CMX_top_Base.P0_1
in P0_1std_logic
Definition: CMX_top_Base.vhd:92
CMX_top_Base.P15_12
in P15_12std_logic
Definition: CMX_top_Base.vhd:478
glink_interface.DAQ_DAV
in DAQ_DAVstd_logic
Definition: glink_interface.vhd:24
CMX_version.bus_drive
out bus_drivestd_logic
Definition: CMX_version.vhd:27
vme_outreg_notri_async.bus_drive
out bus_drivestd_logic
Definition: vme_outreg_rtl_notri_async.vhd:28
CMX_top_Base.P2_23
in P2_23std_logic
Definition: CMX_top_Base.vhd:164
CMX_top_Base.D_CBL_08_B
in D_CBL_08_Bstd_logic
Definition: CMX_top_Base.vhd:614
CMX_top_Base.OCB_A05
in OCB_A05std_logic
Definition: CMX_top_Base.vhd:36
CMX_top_Base.P2_22
in P2_22std_logic
Definition: CMX_top_Base.vhd:163
CMX_delay_generator.ds
in dsstd_logic
Definition: CMX_delay_generator.vhd:36
CMX_top_Base.Behavioral.vme_outreg_notri
vme_outreg_notri
Definition: CMX_top_Base.vhd:918
sys_monitor.BF_SYSMON_14_P
in BF_SYSMON_14_PSTD_LOGIC
Definition: sys_monitor.vhd:48
CMX_top_Base.Behavioral.data_from_vme_test_rw
std_logic_vector (15 downto 0) data_from_vme_test_rw
Definition: CMX_top_Base.vhd:934
CMX_top_Base.P2_21
in P2_21std_logic
Definition: CMX_top_Base.vhd:162
CMX_top_Base.P8_15
in P8_15std_logic
Definition: CMX_top_Base.vhd:306
vme_local_switch.data_vme_up
out data_vme_upstd_logic_vector (15 downto 0)
--! connect this to
Definition: vme_local_switch.vhd:24
CMX_cable_clocked_80Mbps_input_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:30
Topo_Data_TX.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:55
CMX_top_Base.P1_17
in P1_17std_logic
Definition: CMX_top_Base.vhd:133
CMX_top_Base.P12_18
in P12_18std_logic
Definition: CMX_top_Base.vhd:409
CMX_top_Base.P8_6
in P8_6std_logic
Definition: CMX_top_Base.vhd:297
CMX_cable_clocked_80Mbps_input_module.del_array
in del_arraycable_del_array_type (numbits_in_cable_connector downto 0)
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:33
CMX_rate_counter_inhibit.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_rate_counter_inhibit.vhd:38
CMX_top_Base.BF_DOUT_CTP_24
out BF_DOUT_CTP_24std_logic
Definition: CMX_top_Base.vhd:562
daq_glink.bc_counter
in bc_counterunsigned (11 downto 0)
Definition: daq_glink.vhd:27
CMX_top_Base.BF_TO_TP_DAQ_SLINK_RETURN_CMP
in BF_TO_TP_DAQ_SLINK_RETURN_CMPstd_logic
Definition: CMX_top_Base.vhd:694
CMX_top_Base.P3_5
in P3_5std_logic
Definition: CMX_top_Base.vhd:171
Topo_Data_TX.GTX_TX_READY_OUT
out GTX_TX_READY_OUTstd_logic
Definition: Topo_Data_TX.vhd:31
CMX_top_Base.P4_6
in P4_6std_logic
Definition: CMX_top_Base.vhd:197
CMX_top_Base.BF_SYSMON_09_N
in BF_SYSMON_09_NSTD_LOGIC
Definition: CMX_top_Base.vhd:76
CMX_top_Base.P14_14
in P14_14std_logic
Definition: CMX_top_Base.vhd:455
CMX_top_Base.D_CBL_78_B
out D_CBL_78_Bstd_logic
Definition: CMX_top_Base.vhd:688
CMX_top_Base.P13_23
in P13_23std_logic
Definition: CMX_top_Base.vhd:439
CMX_top_Base.OCB_A18
in OCB_A18std_logic
Definition: CMX_top_Base.vhd:49
vme_inreg_notri_async.bus_drive
out bus_drivestd_logic
Definition: vme_inreg_rtl_notri_async.vhd:32
CMX_top_Base.BF_DOUT_CTP_53
out BF_DOUT_CTP_53std_logic
Definition: CMX_top_Base.vhd:593
CMX_top_Base.MP2_F02_QUAD_115_TRN_2_DIR
out MP2_F02_QUAD_115_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:753
CMX_top_Base.P15_16
in P15_16std_logic
Definition: CMX_top_Base.vhd:482
adder_top.clk
in clkT_SL
Definition: adder_top_vs.vhd:35
CMX_CTP_output_module.data
in datastd_logic_vector ((numbits_in_CTP_connector * 2) - 1 downto 0)
Definition: CMX_CTP_output_module.vhd:31
CMX_clock_manager.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_clock_manager.vhd:47
CMX_top_Base.P15_14
in P15_14std_logic
Definition: CMX_top_Base.vhd:480
CMX_top_Base.P13_0
in P13_0std_logic
Definition: CMX_top_Base.vhd:416
CMX_top_Base.P7_14
in P7_14std_logic
Definition: CMX_top_Base.vhd:280
BCID_counter.clk_40
in clk_40std_logic
Definition: BCID_counter.vhd:31
CMX_top_Base.BF_REQ_CABLE_1_INPUT
out BF_REQ_CABLE_1_INPUTstd_logic
Definition: CMX_top_Base.vhd:520
CMX_top_Base.P11_16
in P11_16std_logic
Definition: CMX_top_Base.vhd:382
CMX_top_Base.Behavioral.read_detect_outreg_test
std_logic read_detect_outreg_test
Definition: CMX_top_Base.vhd:812
CMX_top_Base.OCB_A17
in OCB_A17std_logic
Definition: CMX_top_Base.vhd:48
CMX_top_Base.Behavioral.del_register
del_register_type del_register
Definition: CMX_top_Base.vhd:1028
CMX_top_Base.OCB_A23
in OCB_A23std_logic
Definition: CMX_top_Base.vhd:54
CMX_top_Base.OCB_A01
in OCB_A01std_logic
Definition: CMX_top_Base.vhd:32
decoder.et2_width
et2_widthinteger :=10
Definition: jet_decoder.vhd:35
vme_outreg_notri_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:26
CMX_top_Base.MP2_F09_QUAD_114_TRN_0_CMP
out MP2_F09_QUAD_114_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:742
CMX_top_Base.P9_20
in P9_20std_logic
Definition: CMX_top_Base.vhd:336
CMX_top_Base.P0_7
in P0_7std_logic
Definition: CMX_top_Base.vhd:98
daq_glink.clk4000
in clk4000std_logic
Definition: daq_glink.vhd:31
sys_monitor.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: sys_monitor.vhd:57
CMX_crate_cable_output_module.data
in datastd_logic_vector (numbits_in_RTM_connector * 2 * num_RTM_cables - 1 downto 0)
Definition: CMX_crate_cable_output_module.vhd:28
CMX_top_Base.D_CBL_15_B
out D_CBL_15_Bstd_logic
Definition: CMX_top_Base.vhd:621
CMX_top_Base.P0_22
in P0_22std_logic
Definition: CMX_top_Base.vhd:113
SFP_Data_TXRX.clk120_out
out clk120_outstd_logic
Definition: SFP_TXRX.vhd:47
CMX_top_Base.P14_20
in P14_20std_logic
Definition: CMX_top_Base.vhd:461
CMX_top_Base.CLK_120MHz000_XTAL_1_BF_TRNCV_CMP
in CLK_120MHz000_XTAL_1_BF_TRNCV_CMPstd_logic
Definition: CMX_top_Base.vhd:703
CMX_top_Base.P8_13
in P8_13std_logic
Definition: CMX_top_Base.vhd:304
CMX_system_cable_input_module.ncs
in ncsstd_logic
Definition: CMX_system_cable_input_module.vhd:44
CMX_top_Base.BF_DOUT_CTP_18
out BF_DOUT_CTP_18std_logic
Definition: CMX_top_Base.vhd:556
CMX_top_Base.BF_DOUT_CTP_06
out BF_DOUT_CTP_06std_logic
Definition: CMX_top_Base.vhd:544
vme_inreg.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl.vhd:28
CMX_delay_generator.clk40
in clk40std_logic
Definition: CMX_delay_generator.vhd:33
CMX_top_Base.BF_DOUT_CTP_27
out BF_DOUT_CTP_27std_logic
Definition: CMX_top_Base.vhd:565
CMX_top_Base.BF_DOUT_CTP_43
out BF_DOUT_CTP_43std_logic
Definition: CMX_top_Base.vhd:583
CMX_clock_manager.buf_clk200
out buf_clk200std_logic
Definition: CMX_clock_manager.vhd:38
CMX_top_Base.MP2_F03_QUAD_113_TRN_1_DIR
out MP2_F03_QUAD_113_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:735
CMX_top_Base.D_CBL_49_B
out D_CBL_49_Bstd_logic
Definition: CMX_top_Base.vhd:657
decoder.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: jet_decoder.vhd:68
Topo_Data_TX.ext_trigger
in ext_triggerstd_logic
Definition: Topo_Data_TX.vhd:50
CMX_top_Base.BF_SYSMON_11_N
in BF_SYSMON_11_NSTD_LOGIC
Definition: CMX_top_Base.vhd:80
CMX_top_Base.RXN_IN
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: CMX_top_Base.vhd:762
decoder.max_tobs_pjem
max_tobs_pjeminteger :=4
Definition: jet_decoder.vhd:34
CMX_top_Base.P3_19
in P3_19std_logic
Definition: CMX_top_Base.vhd:185
CMX_top_Base.Behavioral.data_to_vme_test_r
std_logic_vector (15 downto 0) data_to_vme_test_r
Definition: CMX_top_Base.vhd:939
CMX_top_Base.MP2_F11_QUAD_114_TRN_1_CMP
out MP2_F11_QUAD_114_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:744
CMX_top_Base.P2_16
in P2_16std_logic
Definition: CMX_top_Base.vhd:157
decoder.datai
in dataiarr_4Xword (max_jems - 1 downto 0)
Definition: jet_decoder.vhd:47
CMX_top_Base.P9_14
in P9_14std_logic
Definition: CMX_top_Base.vhd:330
SFP_Data_TXRX.DFETAP3MONITOR
out DFETAP3MONITORstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:66
vme_local_switch
Definition: vme_local_switch.vhd:22
CMX_top_Base.D_CBL_11_B
out D_CBL_11_Bstd_logic
Definition: CMX_top_Base.vhd:617
CMX_top_Base.P2_7
in P2_7std_logic
Definition: CMX_top_Base.vhd:148
CMX_top_Base.P12_10
in P12_10std_logic
Definition: CMX_top_Base.vhd:401
BCID_counter.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: BCID_counter.vhd:38
CMX_top_Base.P10_24
in P10_24std_logic
Definition: CMX_top_Base.vhd:365
Topo_Data_TX.TXP_OUT
out TXP_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:37
CMX_top_Base.P0_0
in P0_0std_logic
Definition: CMX_top_Base.vhd:91
daq_collector.dout_ro
in dout_roT_SL
Definition: daq_collector.vhd:31
daq_glink.l1a
in l1astd_logic
Definition: daq_glink.vhd:28
vme_outreg_notri_async
Definition: vme_outreg_rtl_notri_async.vhd:16
CMX_top_Base.P9_1
in P9_1std_logic
Definition: CMX_top_Base.vhd:317
CMX_top_Base.MP1_F00_QUAD_112_TRN_3_DIR
out MP1_F00_QUAD_112_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:731
BCID_counter.reset
in resetstd_logic
Definition: BCID_counter.vhd:30
CMX_top_Base.P11_5
in P11_5std_logic
Definition: CMX_top_Base.vhd:371
CMX_top_Base.MP1_F06_QUAD_112_TRN_1_CMP
out MP1_F06_QUAD_112_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:728
CMX_top_Base.P14_16
in P14_16std_logic
Definition: CMX_top_Base.vhd:457
CMX_top_Base.BF_SYSMON_11_P
in BF_SYSMON_11_PSTD_LOGIC
Definition: CMX_top_Base.vhd:79
decoder.ncs
in ncsstd_logic
Definition: jet_decoder.vhd:64
SFP_Data_TXRX.GTX_RX_READY_OUT
out GTX_RX_READY_OUTstd_logic
Definition: SFP_TXRX.vhd:37
sys_monitor.BF_SYSMON_01_P
in BF_SYSMON_01_PSTD_LOGIC
Definition: sys_monitor.vhd:28
CMX_delay_generator.ncs
in ncsstd_logic
Definition: CMX_delay_generator.vhd:34
CMX_top_Base.D_CBL_34_B
out D_CBL_34_Bstd_logic
Definition: CMX_top_Base.vhd:642
CMX_top_Base.BF_DOUT_CTP_58
out BF_DOUT_CTP_58std_logic
Definition: CMX_top_Base.vhd:598
CMX_top_Base.P8_2
in P8_2std_logic
Definition: CMX_top_Base.vhd:293
CMX_top_Base.BF_DOUT_CTP_10
out BF_DOUT_CTP_10std_logic
Definition: CMX_top_Base.vhd:548
vme_outreg_notri.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl_notri.vhd:30
CMX_top_Base.OCB_SYS_RESET_B
in OCB_SYS_RESET_Bstd_logic
Definition: CMX_top_Base.vhd:60
CMX_top_Base.P10_1
in P10_1std_logic
Definition: CMX_top_Base.vhd:342
CMX_top_Base.P7_22
in P7_22std_logic
Definition: CMX_top_Base.vhd:288
decoder.BCID_in
in BCID_instd_logic_vector (11 downto 0)
Definition: jet_decoder.vhd:56
SFP_Data_TXRX.DFETAP1
in DFETAP1std_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:61
CMX_BASE_VME_BSPT
Definition: cmx_base_vme_bspt.vhd:24
CMX_top_Base.P15_4
in P15_4std_logic
Definition: CMX_top_Base.vhd:470
CMX_top_Base.D_CBL_70_B
out D_CBL_70_Bstd_logic
Definition: CMX_top_Base.vhd:680
CMX_top_Base.P3_3
in P3_3std_logic
Definition: CMX_top_Base.vhd:169
BCID_counter.ncs
in ncsstd_logic
Definition: BCID_counter.vhd:34
vme_outreg.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl.vhd:27
vme_local_switch.bus_drive_up
out bus_drive_upstd_logic
or of all bus drive requests from below
Definition: vme_local_switch.vhd:38
CMX_top_Base.BF_DOUT_CTP_03
out BF_DOUT_CTP_03std_logic
Definition: CMX_top_Base.vhd:541
CMX_top_Base.D_CBL_65_B
out D_CBL_65_Bstd_logic
Definition: CMX_top_Base.vhd:675
CMX_clock_manager.buf_clk40
out buf_clk40std_logic
Definition: CMX_clock_manager.vhd:32
CMX_top_Base.P14_22
in P14_22std_logic
Definition: CMX_top_Base.vhd:463
CMX_top_Base.BUF_TTC_BNCH_CNT_RES
in BUF_TTC_BNCH_CNT_RESstd_logic
Definition: CMX_top_Base.vhd:699
CMX_top_Base.BF_DEBUG_9
out BF_DEBUG_9std_logic
Definition: CMX_top_Base.vhd:515
CMX_top_Base.P12_22
in P12_22std_logic
Definition: CMX_top_Base.vhd:413
CMX_system_cable_input_module.ds
in dsstd_logic
Definition: CMX_system_cable_input_module.vhd:46
CMX_top_Base.D_CBL_51_B
out D_CBL_51_Bstd_logic
Definition: CMX_top_Base.vhd:659
CMX_top_Base.P6_22
in P6_22std_logic
Definition: CMX_top_Base.vhd:263
CMX_top_Base.P11_22
in P11_22std_logic
Definition: CMX_top_Base.vhd:388
CMX_top_Base.P13_15
in P13_15std_logic
Definition: CMX_top_Base.vhd:431
CMX_Memory_spy_inhibit.buf_clk40
in buf_clk40std_logic
Definition: CMX_Memory_spy_inhibit.vhd:40
CMX_top_Base.P10_8
in P10_8std_logic
Definition: CMX_top_Base.vhd:349
CMX_top_Base.D_CBL_72_B
out D_CBL_72_Bstd_logic
Definition: CMX_top_Base.vhd:682
CMX_top_Base.D_CBL_00_B
out D_CBL_00_Bstd_logic
Definition: CMX_top_Base.vhd:606
CMX_top_Base.BF_DEBUG_5
out BF_DEBUG_5std_logic
Definition: CMX_top_Base.vhd:511
CMX_top_Base.MP2_F10_QUAD_114_TRN_2_CMP
out MP2_F10_QUAD_114_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:746
adder_top.gen_system
gen_systemstd_logic :='1'
Definition: adder_top_vs.vhd:32
daq_glink.RAM_global_offset
in RAM_global_offsetunsigned (7 downto 0)
Definition: daq_glink.vhd:34
CMX_top_Base.P11_21
in P11_21std_logic
Definition: CMX_top_Base.vhd:387
CMX_top_Base.P12_16
in P12_16std_logic
Definition: CMX_top_Base.vhd:407
CMX_system_cable_input_module.data
out datastd_logic_vector (numbits_in_RTM_connector * 2 * num_RTM_cables - 1 downto 0)
Definition: CMX_system_cable_input_module.vhd:32
CMX_top_Base.MP1_F10_QUAD_111_TRN_2_CMP
out MP1_F10_QUAD_111_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:722
CMX_top_Base.P9_16
in P9_16std_logic
Definition: CMX_top_Base.vhd:332
CMX_top_Base.P0_21
in P0_21std_logic
Definition: CMX_top_Base.vhd:112
CMX_top_Base.BF_SYSMON_07_P
in BF_SYSMON_07_PSTD_LOGIC
Definition: CMX_top_Base.vhd:71
CMX_input_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:60
CMX_top_Base.D_CBL_77_B
out D_CBL_77_Bstd_logic
Definition: CMX_top_Base.vhd:687
CMX_top_Base.D_CBL_41_B
out D_CBL_41_Bstd_logic
Definition: CMX_top_Base.vhd:649
CMX_top_Base.P1_6
in P1_6std_logic
Definition: CMX_top_Base.vhd:122
CMX_top_Base.P13_8
in P13_8std_logic
Definition: CMX_top_Base.vhd:424
CMX_top_Base.D_CBL_53_B
out D_CBL_53_Bstd_logic
Definition: CMX_top_Base.vhd:661
CMX_input_module.ncs
in ncsstd_logic
Definition: CMX_input_module.vhd:57
CMX_top_Base.P15_13
in P15_13std_logic
Definition: CMX_top_Base.vhd:479
CMX_rate_counter_inhibit.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_rate_counter_inhibit.vhd:39
CMX_crate_cable_output_module.ddr_data_out
out ddr_data_outarr_RTM (num_RTM_cables - 1 downto 0)
Definition: CMX_crate_cable_output_module.vhd:30
CMX_top_Base.P8_5
in P8_5std_logic
Definition: CMX_top_Base.vhd:296
CMX_top_Base.BF_DEBUG_0
out BF_DEBUG_0std_logic
Definition: CMX_top_Base.vhd:506
sys_monitor.BF_SYSMON_08_N
in BF_SYSMON_08_NSTD_LOGIC
Definition: sys_monitor.vhd:37
CMX_cable_clocked_80Mbps_input_module.buf_clk200
in buf_clk200std_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:31
CMX_rate_counter_inhibit.counter_inhibit
out counter_inhibitstd_logic
Definition: CMX_rate_counter_inhibit.vhd:31
CMX_top_Base.P3_20
in P3_20std_logic
Definition: CMX_top_Base.vhd:186
CMX_top_Base.P10_21
in P10_21std_logic
Definition: CMX_top_Base.vhd:362
CMX_top_Base.P11_12
in P11_12std_logic
Definition: CMX_top_Base.vhd:378
adder_top.par_err
in par_errT_SLV2
Definition: adder_top_vs.vhd:57
CMX_top_Base.MP1_F09_QUAD_111_TRN_0_DIR
out MP1_F09_QUAD_111_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:717
CMX_top_Base.OCB_A08
in OCB_A08std_logic
Definition: CMX_top_Base.vhd:39
CMX_top_Base.BF_REQ_CTP_1_INPUT
out BF_REQ_CTP_1_INPUTstd_logic
Definition: CMX_top_Base.vhd:518
CMX_top_Base.BF_LED_REQ_3
out BF_LED_REQ_3std_logic
Definition: CMX_top_Base.vhd:526
CMX_top_Base.Behavioral.upload_delays
std_logic upload_delays
Definition: CMX_top_Base.vhd:1029
CMX_rate_counter_inhibit.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_rate_counter_inhibit.vhd:40
CMX_top_Base.BF_TO_FROM_BSPT_7
out BF_TO_FROM_BSPT_7std_logic
Definition: CMX_top_Base.vhd:535
CMX_top_Base.P4_11
in P4_11std_logic
Definition: CMX_top_Base.vhd:202
CMX_top_Base.BF_DOUT_CTP_25
out BF_DOUT_CTP_25std_logic
Definition: CMX_top_Base.vhd:563
CMX_top_Base.D_CBL_63_B
out D_CBL_63_Bstd_logic
Definition: CMX_top_Base.vhd:673
CMX_input_module.ODATA_first_half
out ODATA_first_halfarr_2Xword (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:35
CMX_rate_counter_inhibit.ds
in dsstd_logic
Definition: CMX_rate_counter_inhibit.vhd:37
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_114_CMP
in CLK_320MHz64_LHC_BF_QUAD_114_CMPstd_logic
Definition: CMX_top_Base.vhd:760
sys_monitor.BF_SYSMON_14_N
in BF_SYSMON_14_NSTD_LOGIC
Definition: sys_monitor.vhd:49
CMX_Memory_spy_inhibit.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_Memory_spy_inhibit.vhd:46
CMX_rate_counter_inhibit
Definition: CMX_rate_counter_inhibit.vhd:29
CMX_top_Base.BF_SYSMON_07_N
in BF_SYSMON_07_NSTD_LOGIC
Definition: CMX_top_Base.vhd:72
CMX_top_Base.P14_24
in P14_24std_logic
Definition: CMX_top_Base.vhd:465
glink_interface.ROI_BYTE
out ROI_BYTEstd_logic_vector (7 downto 0)
Definition: glink_interface.vhd:27
vme_inreg.ds
in dsstd_logic
Definition: vme_inreg_rtl.vhd:29
SFP_Data_TXRX.clk40_in
in clk40_instd_logic
Definition: SFP_TXRX.vhd:48
CMX_top_Base.P14_18
in P14_18std_logic
Definition: CMX_top_Base.vhd:459
CMX_top_Base.P7_23
in P7_23std_logic
Definition: CMX_top_Base.vhd:289
sys_monitor.BF_SYSMON_08_P
in BF_SYSMON_08_PSTD_LOGIC
Definition: sys_monitor.vhd:36
CMX_flavor_package
Definition: CMX_flavor_package.vhd:19
CMX_top_Base.P5_12
in P5_12std_logic
Definition: CMX_top_Base.vhd:228
CMX_top_Base.P13_11
in P13_11std_logic
Definition: CMX_top_Base.vhd:427
daq_glink.reset
in resetstd_logic
Definition: daq_glink.vhd:33
SFP_Data_TXRX.DFETAP4MONITOR
out DFETAP4MONITORstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:68
vme_inreg_notri.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl_notri.vhd:21
CMX_top_Base.MP1_F05_QUAD_110_TRN_3_DIR
out MP1_F05_QUAD_110_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:715
decoder.et1_width
et1_widthinteger :=9
Definition: jet_decoder.vhd:36
CMX_top_Base.P2_10
in P2_10std_logic
Definition: CMX_top_Base.vhd:151
CMX_top_Base.P3_18
in P3_18std_logic
Definition: CMX_top_Base.vhd:184
CMX_top_Base.P3_12
in P3_12std_logic
Definition: CMX_top_Base.vhd:178
CMX_top_Base.P8_17
in P8_17std_logic
Definition: CMX_top_Base.vhd:308
CMX_top_Base.BF_DOUT_CTP_20
out BF_DOUT_CTP_20std_logic
Definition: CMX_top_Base.vhd:558
CMX_top_Base.BF_SYSMON_15_N
in BF_SYSMON_15_NSTD_LOGIC
Definition: CMX_top_Base.vhd:88
CMX_top_Base.P13_5
in P13_5std_logic
Definition: CMX_top_Base.vhd:421
CMX_top_Base.P13_14
in P13_14std_logic
Definition: CMX_top_Base.vhd:430
vme_main_hub.data_vme_from_below
in data_vme_from_belowstd_logic_vector (15 downto 0)
--! input: ORed
Definition: vme_main_hub.vhd:25
CMX_top_Base.P11_11
in P11_11std_logic
Definition: CMX_top_Base.vhd:377
CMX_clock_manager.buf_clk40_m90o
out buf_clk40_m90ostd_logic
Definition: CMX_clock_manager.vhd:35
CMX_top_Base.OCB_A06
in OCB_A06std_logic
Definition: CMX_top_Base.vhd:37
CMX_top_Base.D_CBL_05_B
out D_CBL_05_Bstd_logic
Definition: CMX_top_Base.vhd:611
CMX_top_Base.P1_9
in P1_9std_logic
Definition: CMX_top_Base.vhd:125
glink_interface.ROI_IN
in ROI_INstd_logic_vector (19 downto 0)
Definition: glink_interface.vhd:23
CMX_top_Base.P9_9
in P9_9std_logic
Definition: CMX_top_Base.vhd:325
CMX_top_Base.P15_6
in P15_6std_logic
Definition: CMX_top_Base.vhd:472
CMX_top_Base.P0_16
in P0_16std_logic
Definition: CMX_top_Base.vhd:107
CMX_top_Base.P11_4
in P11_4std_logic
Definition: CMX_top_Base.vhd:370
CMX_top_Base.MP1_F06_QUAD_112_TRN_1_DIR
out MP1_F06_QUAD_112_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:727
CMX_top_Base.P14_3
in P14_3std_logic
Definition: CMX_top_Base.vhd:444
CMX_BASE_VME_BSPT.board_ds
out board_dsstd_logic
Definition: cmx_base_vme_bspt.vhd:31
CMX_top_Base.BF_DOUT_CTP_30
out BF_DOUT_CTP_30std_logic
Definition: CMX_top_Base.vhd:568
CMX_top_Base.P13_13
in P13_13std_logic
Definition: CMX_top_Base.vhd:429
sys_monitor.BF_SYSMON_11_P
in BF_SYSMON_11_PSTD_LOGIC
Definition: sys_monitor.vhd:42
CMX_top_Base.MP2_F05_QUAD_113_TRN_3_DIR
out MP2_F05_QUAD_113_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:739
CMX_top_Base.P4_1
in P4_1std_logic
Definition: CMX_top_Base.vhd:192
sys_monitor.clk
in clkstd_logic
Definition: sys_monitor.vhd:27
CMX_top_Base.P0_5
in P0_5std_logic
Definition: CMX_top_Base.vhd:96
CMX_rate_counter_inhibit.rd_nwr
in rd_nwrstd_logic
Definition: CMX_rate_counter_inhibit.vhd:36
CMX_input_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_input_module.vhd:54
BCID_counter.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: BCID_counter.vhd:37
CMX_top_Base.P6_6
in P6_6std_logic
Definition: CMX_top_Base.vhd:247
CMX_top_Base.P5_15
in P5_15std_logic
Definition: CMX_top_Base.vhd:231
CMX_top_Base.MP1_F09_QUAD_111_TRN_0_CMP
out MP1_F09_QUAD_111_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:718
CMX_top_Base.P5_1
in P5_1std_logic
Definition: CMX_top_Base.vhd:217
CMX_top_Base.MP1_F05_QUAD_110_TRN_3_CMP
out MP1_F05_QUAD_110_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:716
CMX_top_Base.BUF_TTC_L1_ACCEPT
in BUF_TTC_L1_ACCEPTstd_logic
Definition: CMX_top_Base.vhd:698
CMX_top_Base.P6_10
in P6_10std_logic
Definition: CMX_top_Base.vhd:251
vme_inreg_notri.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:31
CMX_top_Base.BF_DEBUG_3
out BF_DEBUG_3std_logic
Definition: CMX_top_Base.vhd:509
Topo_Data_TX.ncs
in ncsstd_logic
Definition: Topo_Data_TX.vhd:52
CMX_top_Base.BF_SYSMON_08_N
in BF_SYSMON_08_NSTD_LOGIC
Definition: CMX_top_Base.vhd:74
CMX_top_Base.P2_4
in P2_4std_logic
Definition: CMX_top_Base.vhd:145
CMX_top_Base.P12_14
in P12_14std_logic
Definition: CMX_top_Base.vhd:405
CMX_top_Base.P8_7
in P8_7std_logic
Definition: CMX_top_Base.vhd:298
CMX_top_Base.BF_SYSMON_10_P
in BF_SYSMON_10_PSTD_LOGIC
Definition: CMX_top_Base.vhd:77
CMX_top_Base.P12_1
in P12_1std_logic
Definition: CMX_top_Base.vhd:392
CMX_top_Base.P7_12
in P7_12std_logic
Definition: CMX_top_Base.vhd:278
SFP_Data_TXRX.RXEQMIX_IN
in RXEQMIX_INstd_logic_vector (2 downto 0)
Definition: SFP_TXRX.vhd:55
CMX_top_Base.P14_11
in P14_11std_logic
Definition: CMX_top_Base.vhd:452
CMX_top_Base.P0_14
in P0_14std_logic
Definition: CMX_top_Base.vhd:105
CMX_top_Base.D_CBL_37_B
out D_CBL_37_Bstd_logic
Definition: CMX_top_Base.vhd:645
CMX_top_Base.P8_10
in P8_10std_logic
Definition: CMX_top_Base.vhd:301
Topo_Data_TX.clk320
in clk320std_logic
Definition: Topo_Data_TX.vhd:39
CMX_top_Base.BF_DAQ_DATA_OUT_DIR
out BF_DAQ_DATA_OUT_DIRstd_logic
Definition: CMX_top_Base.vhd:704
CMX_top_Base.BF_DOUT_CTP_22
out BF_DOUT_CTP_22std_logic
Definition: CMX_top_Base.vhd:560
SFP_Data_TXRX.indata
in indatastd_logic_vector (7 downto 0)
Definition: SFP_TXRX.vhd:50
CMX_top_Base.P5_17
in P5_17std_logic
Definition: CMX_top_Base.vhd:233
CMX_top_Base.BF_DOUT_CTP_08
out BF_DOUT_CTP_08std_logic
Definition: CMX_top_Base.vhd:546
CMX_top_Base.P7_19
in P7_19std_logic
Definition: CMX_top_Base.vhd:285
daq_collector.din_cbl_ro
in din_cbl_roT_SL
Definition: daq_collector.vhd:27
CMX_top_Base.D_CBL_44_B
out D_CBL_44_Bstd_logic
Definition: CMX_top_Base.vhd:652
vme_inreg.clk
in clkstd_logic
Definition: vme_inreg_rtl.vhd:25
CMX_top_Base.P15_8
in P15_8std_logic
Definition: CMX_top_Base.vhd:474
glink_interface.daq_byte_out
out daq_byte_outstd_logic_vector (1 downto 0)
Definition: glink_interface.vhd:29
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_111_CMP
in CLK_320MHz64_LHC_BF_QUAD_111_CMPstd_logic
Definition: CMX_top_Base.vhd:758
CMX_top_Base.P14_2
in P14_2std_logic
Definition: CMX_top_Base.vhd:443
sys_monitor.ADDR_REG_RO_SYSMON_DATA_BLOCK
ADDR_REG_RO_SYSMON_DATA_BLOCKinteger :=16#1364#
Definition: sys_monitor.vhd:22
CMX_rate_counter_inhibit.counter_reset
out counter_resetstd_logic
Definition: CMX_rate_counter_inhibit.vhd:32
vme_inreg_notri.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri.vhd:37
CMX_top_Base.P8_0
in P8_0std_logic
Definition: CMX_top_Base.vhd:291
CMX_top_Base.BF_TO_FROM_BSPT_4
out BF_TO_FROM_BSPT_4std_logic
Definition: CMX_top_Base.vhd:532
CMX_top_Base.BF_DEBUG_6
out BF_DEBUG_6std_logic
Definition: CMX_top_Base.vhd:512
vme_outreg.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl.vhd:28
CMX_top_Base.P15_22
in P15_22std_logic
Definition: CMX_top_Base.vhd:488
CMX_top_Base.BF_DOUT_CTP_09
out BF_DOUT_CTP_09std_logic
Definition: CMX_top_Base.vhd:547
CMX_top_Base.P8_14
in P8_14std_logic
Definition: CMX_top_Base.vhd:305
SFP_Data_TXRX.odata
out odatastd_logic_vector (7 downto 0)
Definition: SFP_TXRX.vhd:51
vme_outreg_notri_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:23
decoder.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: jet_decoder.vhd:67
CMX_top_Base.MP1_F08_QUAD_111_TRN_3_CMP
out MP1_F08_QUAD_111_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:724
vme_outreg_notri.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl_notri.vhd:23
CMX_CTP_output_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_CTP_output_module.vhd:39
CMX_top_Base.P15_3
in P15_3std_logic
Definition: CMX_top_Base.vhd:469
CMX_top_Base.P11_24
in P11_24std_logic
Definition: CMX_top_Base.vhd:390
CMX_top_Base.P9_15
in P9_15std_logic
Definition: CMX_top_Base.vhd:331
CMX_top_Base.P4_16
in P4_16std_logic
Definition: CMX_top_Base.vhd:207
SFP_Data_TXRX.GTX_TX_READY_OUT
out GTX_TX_READY_OUTstd_logic
Definition: SFP_TXRX.vhd:36
CMX_top_Base.P15_21
in P15_21std_logic
Definition: CMX_top_Base.vhd:487
BCID_counter.bus_drive
out bus_drivestd_logic
Definition: BCID_counter.vhd:40
sys_monitor.BF_SYSMON_15_P
in BF_SYSMON_15_PSTD_LOGIC
Definition: sys_monitor.vhd:50
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_111_DIR
in CLK_320MHz64_LHC_BF_QUAD_111_DIRstd_logic
Definition: CMX_top_Base.vhd:757
CMX_top_Base.P12_21
in P12_21std_logic
Definition: CMX_top_Base.vhd:412
CMX_top_Base.P7_13
in P7_13std_logic
Definition: CMX_top_Base.vhd:279
CMX_top_Base.P13_21
in P13_21std_logic
Definition: CMX_top_Base.vhd:437
CMX_top_Base.P0_12
in P0_12std_logic
Definition: CMX_top_Base.vhd:103
CMX_top_Base.OCB_A13
in OCB_A13std_logic
Definition: CMX_top_Base.vhd:44
vme_inreg_notri_async.ds
in dsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:27
CMX_top_Base.D_CBL_16_B
in D_CBL_16_Bstd_logic
Definition: CMX_top_Base.vhd:622
CMX_top_Base.MP1_F11_QUAD_111_TRN_1_DIR
out MP1_F11_QUAD_111_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:719
CMX_top_Base.P7_4
in P7_4std_logic
Definition: CMX_top_Base.vhd:270
vme_inreg_notri_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:26
CMX_top_Base.MP1_F03_QUAD_110_TRN_1_CMP
out MP1_F03_QUAD_110_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:712
CMX_top_Base.P7_24
in P7_24std_logic
Definition: CMX_top_Base.vhd:290
CMX_top_Base.OCB_A04
in OCB_A04std_logic
Definition: CMX_top_Base.vhd:35
CMX_top_Base.BF_REQ_CABLE_2_INPUT
out BF_REQ_CABLE_2_INPUTstd_logic
Definition: CMX_top_Base.vhd:521
CMX_top_Base.MP2_F03_QUAD_113_TRN_1_CMP
out MP2_F03_QUAD_113_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:736
CMX_top_Base.P8_23
in P8_23std_logic
Definition: CMX_top_Base.vhd:314
glink_interface.readout_rst_out
out readout_rst_outstd_logic
Definition: glink_interface.vhd:32
CMX_top_Base.P9_8
in P9_8std_logic
Definition: CMX_top_Base.vhd:324
vme_inreg_notri_async.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:31
CMX_clock_manager.pll_locked_ds2
out pll_locked_ds2std_logic
Definition: CMX_clock_manager.vhd:43
CMX_top_Base.OCB_WRITE_B
in OCB_WRITE_Bstd_logic
Definition: CMX_top_Base.vhd:58
CMX_top_Base.P4_2
in P4_2std_logic
Definition: CMX_top_Base.vhd:193
CMX_top_Base.OCB_GEO_ADRS_0
in OCB_GEO_ADRS_0std_logic
Definition: CMX_top_Base.vhd:30
CMX_top_Base.P13_3
in P13_3std_logic
Definition: CMX_top_Base.vhd:419
CMX_version.rd_nwr
in rd_nwrstd_logic
Definition: CMX_version.vhd:23
CMX_Memory_spy_inhibit.spy_write_inhibit
out spy_write_inhibitstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:39
CMX_top_Base.P5_9
in P5_9std_logic
Definition: CMX_top_Base.vhd:225
CMX_cable_clocked_80Mbps_input_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:32
CMX_top_Base.P10_4
in P10_4std_logic
Definition: CMX_top_Base.vhd:345
CMX_clock_manager.IB_DS2
in IB_DS2std_logic
Definition: CMX_clock_manager.vhd:41
CMX_top_Base.P2_9
in P2_9std_logic
Definition: CMX_top_Base.vhd:150
glink_interface.CLK_120MHz
in CLK_120MHzstd_logic
Definition: glink_interface.vhd:20
CMX_top_Base.P0_20
in P0_20std_logic
Definition: CMX_top_Base.vhd:111
SFP_Data_TXRX.DFETAP1MONITOR
out DFETAP1MONITORstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:62
CMX_top_Base.MP2_F10_QUAD_114_TRN_2_DIR
out MP2_F10_QUAD_114_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:745
decoder.max_tobs_topo
max_tobs_topointeger :=24
Definition: jet_decoder.vhd:32
CMX_top_Base.P1_14
in P1_14std_logic
Definition: CMX_top_Base.vhd:130
SFP_Data_TXRX.DFETAP2
in DFETAP2std_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:63
CMX_top_Base.P12_13
in P12_13std_logic
Definition: CMX_top_Base.vhd:404
Topo_Data_TX.indata
in indatastd_logic_vector (TX_indata_length - 1 downto 0)
Definition: Topo_Data_TX.vhd:48
CMX_top_Base.BF_DOUT_CTP_63
out BF_DOUT_CTP_63std_logic
Definition: CMX_top_Base.vhd:603
CMX_top_Base.Behavioral.vme_outreg_notri_async
vme_outreg_notri_async
Definition: CMX_top_Base.vhd:885
CMX_top_Base.D_CBL_75_B
out D_CBL_75_Bstd_logic
Definition: CMX_top_Base.vhd:685
CMX_top_Base.P6_20
in P6_20std_logic
Definition: CMX_top_Base.vhd:261
CMX_top_Base.BF_SYSMON_03_P
in BF_SYSMON_03_PSTD_LOGIC
Definition: CMX_top_Base.vhd:67
vme_outreg_notri.clk
in clkstd_logic
Definition: vme_outreg_rtl_notri.vhd:20
CMX_top_Base.P1_13
in P1_13std_logic
Definition: CMX_top_Base.vhd:129
adder_top.bus_drive
out bus_drivestd_logic
Definition: adder_top_vs.vhd:55
CMX_clock_manager.rd_nwr
in rd_nwrstd_logic
Definition: CMX_clock_manager.vhd:45
CMX_crate_cable_output_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_crate_cable_output_module.vhd:36
CMX_top_Base.P2_12
in P2_12std_logic
Definition: CMX_top_Base.vhd:153
CMX_top_Base.P5_19
in P5_19std_logic
Definition: CMX_top_Base.vhd:235
CMX_top_Base.P6_23
in P6_23std_logic
Definition: CMX_top_Base.vhd:264
CMX_top_Base.P11_13
in P11_13std_logic
Definition: CMX_top_Base.vhd:379
daq_glink
Definition: daq_glink.vhd:21
sys_monitor.BF_SYSMON_04_P
in BF_SYSMON_04_PSTD_LOGIC
Definition: sys_monitor.vhd:32
CMX_top_Base.Behavioral.vme_inreg_async
vme_inreg_async
Definition: CMX_top_Base.vhd:833
adder_top.dout_ro
out dout_roT_SL
Definition: adder_top_vs.vhd:43
Topo_Data_TX.BCID
in BCIDstd_logic_vector (11 downto 0)
Definition: Topo_Data_TX.vhd:42
CMX_top_Base.BF_DOUT_CTP_40
out BF_DOUT_CTP_40std_logic
Definition: CMX_top_Base.vhd:580
CMX_input_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_input_module.vhd:28
daq_collector.datai
in dataiarr_4Xword (max_jems - 1 downto 0)
Definition: daq_collector.vhd:25
SFP_Data_TXRX.PLLLKDET_diag
out PLLLKDET_diagstd_logic
Definition: SFP_TXRX.vhd:38
CMX_top_Base.P5_20
in P5_20std_logic
Definition: CMX_top_Base.vhd:236
CMX_top_Base.P5_22
in P5_22std_logic
Definition: CMX_top_Base.vhd:238
CMX_top_Base.BF_SYSMON_04_P
in BF_SYSMON_04_PSTD_LOGIC
Definition: CMX_top_Base.vhd:69
CMX_top_Base.D_CBL_60_B
out D_CBL_60_Bstd_logic
Definition: CMX_top_Base.vhd:670
CMX_top_Base.BF_ROI_DATA_OUT_CMP
out BF_ROI_DATA_OUT_CMPstd_logic
Definition: CMX_top_Base.vhd:707
CMX_top_Base.BF_DOUT_CTP_15
out BF_DOUT_CTP_15std_logic
Definition: CMX_top_Base.vhd:553
CMX_top_Base.P6_9
in P6_9std_logic
Definition: CMX_top_Base.vhd:250
CMX_top_Base.D_CBL_43_B
in D_CBL_43_Bstd_logic
Definition: CMX_top_Base.vhd:651
CMX_top_Base.P2_5
in P2_5std_logic
Definition: CMX_top_Base.vhd:146
CMX_top_Base.BF_DOUT_CTP_62
out BF_DOUT_CTP_62std_logic
Definition: CMX_top_Base.vhd:602
CMX_top_Base.P10_2
in P10_2std_logic
Definition: CMX_top_Base.vhd:343
daq_glink.dav
out davstd_logic
Definition: daq_glink.vhd:30
glink_interface.byte_pos_out
out byte_pos_outstd_logic_vector (5 downto 0)
Definition: glink_interface.vhd:30
CMX_top_Base.P14_19
in P14_19std_logic
Definition: CMX_top_Base.vhd:460
decoder.overflow
out overflowstd_logic_vector (num_copies - 1 downto 0)
Definition: jet_decoder.vhd:51
CMX_BASE_VME_BSPT.brdsel_n
out brdsel_nstd_logic
Definition: cmx_base_vme_bspt.vhd:32
CMX_crate_cable_output_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_crate_cable_output_module.vhd:33
CMX_top_Base.Behavioral.vme_main_hub
vme_main_hub
Definition: CMX_top_Base.vhd:855
SFP_Data_TXRX.clock_source
clock_sourcestd_logic
Definition: SFP_TXRX.vhd:27
CMX_top_Base.BF_DOUT_CTP_33
out BF_DOUT_CTP_33std_logic
Definition: CMX_top_Base.vhd:573
CMX_top_Base.P0_23
in P0_23std_logic
Definition: CMX_top_Base.vhd:114
CMX_top_Base.D_CBL_26_B
out D_CBL_26_Bstd_logic
Definition: CMX_top_Base.vhd:632
vme_inreg_notri.bus_drive
out bus_drivestd_logic
Definition: vme_inreg_rtl_notri.vhd:34
CMX_top_Base.P12_5
in P12_5std_logic
Definition: CMX_top_Base.vhd:396
CMX_top_Base.P8_18
in P8_18std_logic
Definition: CMX_top_Base.vhd:309
CMX_top_Base.P0_24
in P0_24std_logic
Definition: CMX_top_Base.vhd:115
Topo_Data_TX.bus_drive
out bus_drivestd_logic
Definition: Topo_Data_TX.vhd:58
vme_outreg_notri.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri.vhd:26
CMX_cable_clocked_80Mbps_input_module.ddr_data_in
in ddr_data_instd_logic_vector (numbits_in_cable_connector downto 0)
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:29
sys_monitor.BF_SYSMON_15_N
in BF_SYSMON_15_NSTD_LOGIC
Definition: sys_monitor.vhd:51
CMX_top_Base.MP2_F00_QUAD_115_TRN_3_DIR
out MP2_F00_QUAD_115_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:755
decoder.clk40MHz
in clk40MHzstd_logic
Definition: jet_decoder.vhd:42
CMX_crate_cable_output_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_crate_cable_output_module.vhd:41
Topo_Data_TX.RXN_IN
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:34
BCID_counter
Definition: BCID_counter.vhd:28
CMX_top_Base.D_CBL_47_B
out D_CBL_47_Bstd_logic
Definition: CMX_top_Base.vhd:655
CMX_top_Base.P8_11
in P8_11std_logic
Definition: CMX_top_Base.vhd:302
CMX_input_module.bus_drive
out bus_drivestd_logic
Definition: CMX_input_module.vhd:63
glink_interface.word_sel_out
out word_sel_outstd_logic_vector (1 downto 0)
Definition: glink_interface.vhd:31
CMX_top_Base.D_CBL_68_B
out D_CBL_68_Bstd_logic
Definition: CMX_top_Base.vhd:678
vme_outreg.ncs
in ncsstd_logic
Definition: vme_outreg_rtl.vhd:23
CMX_top_Base.P12_15
in P12_15std_logic
Definition: CMX_top_Base.vhd:406
Topo_Data_TX.RXP_IN
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:35
CMX_Memory_spy_inhibit.ds
in dsstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:44
CMX_top_Base.Behavioral.test_rw_counter
unsigned (15 downto 0) test_rw_counter
Definition: CMX_top_Base.vhd:938
CMX_top_Base.P7_11
in P7_11std_logic
Definition: CMX_top_Base.vhd:277
CMX_CTP_output_module.sdr_data_out
out sdr_data_outarr_CTP
Definition: CMX_CTP_output_module.vhd:34
CMX_top_Base.P8_12
in P8_12std_logic
Definition: CMX_top_Base.vhd:303
CMX_top_Base.D_CBL_55_B
out D_CBL_55_Bstd_logic
Definition: CMX_top_Base.vhd:665
glink_interface.DAQ_IN
in DAQ_INstd_logic_vector (19 downto 0)
Definition: glink_interface.vhd:22
CMX_top_Base.P4_3
in P4_3std_logic
Definition: CMX_top_Base.vhd:194
daq_glink.clk4008
in clk4008std_logic
Definition: daq_glink.vhd:32
CMX_top_Base.P0_9
in P0_9std_logic
Definition: CMX_top_Base.vhd:100
SFP_Data_TXRX.DFESENSCAL
out DFESENSCALstd_logic_vector (2 downto 0)
Definition: SFP_TXRX.vhd:60
CMX_top_Base.P11_9
in P11_9std_logic
Definition: CMX_top_Base.vhd:375
vme_inreg_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_async_rtl.vhd:26
CMX_top_Base.P6_12
in P6_12std_logic
Definition: CMX_top_Base.vhd:253
CMX_top_Base.P13_7
in P13_7std_logic
Definition: CMX_top_Base.vhd:423
CMX_top_Base.D_CBL_36_B
out D_CBL_36_Bstd_logic
Definition: CMX_top_Base.vhd:644
vme_inreg_notri.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl_notri.vhd:28
CMX_top_Base.D_CBL_56_B
out D_CBL_56_Bstd_logic
Definition: CMX_top_Base.vhd:666
CMX_top_Base.CLK_40MHz08_DSKW_1_BF_LOGIC_CMP
in CLK_40MHz08_DSKW_1_BF_LOGIC_CMPstd_logic
Definition: CMX_top_Base.vhd:497
CMX_top_Base.P9_24
in P9_24std_logic
Definition: CMX_top_Base.vhd:340
CMX_clock_manager.buf_clk40_90o
out buf_clk40_90ostd_logic
Definition: CMX_clock_manager.vhd:33
CMX_top_Base.BF_DOUT_CTP_48
out BF_DOUT_CTP_48std_logic
Definition: CMX_top_Base.vhd:588
CMX_top_Base.OCB_A02
in OCB_A02std_logic
Definition: CMX_top_Base.vhd:33
SFP_Data_TXRX.MGTREFCLK
in MGTREFCLKstd_logic
Definition: SFP_TXRX.vhd:33
CMX_top_Base.P4_0
in P4_0std_logic
Definition: CMX_top_Base.vhd:191
CMX_top_Base.D_CBL_50_B
out D_CBL_50_Bstd_logic
Definition: CMX_top_Base.vhd:658
adder_top.datai
in dataiarr_4Xword (max_jems - 1 downto 0)
Definition: adder_top_vs.vhd:37
CMX_top_Base.D_CBL_40_B
out D_CBL_40_Bstd_logic
Definition: CMX_top_Base.vhd:648
CMX_top_Base.BF_DOUT_CTP_44
out BF_DOUT_CTP_44std_logic
Definition: CMX_top_Base.vhd:584
CMX_system_cable_input_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_system_cable_input_module.vhd:37
CMX_top_Base.BF_SYSMON_08_P
in BF_SYSMON_08_PSTD_LOGIC
Definition: CMX_top_Base.vhd:73
CMX_top_Base.P9_23
in P9_23std_logic
Definition: CMX_top_Base.vhd:339
CMX_CTP_output_module.buf_clk40_center
in buf_clk40_centerstd_logic
Definition: CMX_CTP_output_module.vhd:37
CMX_top_Base.P13_12
in P13_12std_logic
Definition: CMX_top_Base.vhd:428
CMX_top_Base.BF_DOUT_CTP_52
out BF_DOUT_CTP_52std_logic
Definition: CMX_top_Base.vhd:592
CMX_top_Base.P15_9
in P15_9std_logic
Definition: CMX_top_Base.vhd:475
CMX_VME_defs
test registers
Definition: CMX_VME_defs.vhd:13
CMX_system_cable_input_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_system_cable_input_module.vhd:42
CMX_clock_manager.I_DS2
in I_DS2std_logic
Definition: CMX_clock_manager.vhd:40
CMX_local_package
Definition: CMX_local_package.vhd:13
CMX_top_Base.D_CBL_12_B
out D_CBL_12_Bstd_logic
Definition: CMX_top_Base.vhd:618
CMX_top_Base.OCB_A20
in OCB_A20std_logic
Definition: CMX_top_Base.vhd:51
CMX_top_Base.P0_4
in P0_4std_logic
Definition: CMX_top_Base.vhd:95
CMX_BASE_VME_BSPT.clk40
in clk40std_logic
Definition: cmx_base_vme_bspt.vhd:26
CMX_top_Base.P6_13
in P6_13std_logic
Definition: CMX_top_Base.vhd:254
CMX_top_Base.Behavioral.bus_drive_from_below_top
std_logic_vector (1762 downto 0) bus_drive_from_below_top
Definition: CMX_top_Base.vhd:864
CMX_CTP_output_module.ds
in dsstd_logic
Definition: CMX_CTP_output_module.vhd:45
glink_interface.DAQ_ENCODED_DIAG
out DAQ_ENCODED_DIAGstd_logic_vector (23 downto 0)
Definition: glink_interface.vhd:28
CMX_top_Base.P10_3
in P10_3std_logic
Definition: CMX_top_Base.vhd:344
CMX_top_Base.Behavioral.keep
string keep
Definition: CMX_top_Base.vhd:773
CMX_top_Base.P1_3
in P1_3std_logic
Definition: CMX_top_Base.vhd:119
CMX_top_Base.P0_3
in P0_3std_logic
Definition: CMX_top_Base.vhd:94
CMX_top_Base.BF_REQ_CTP_2_INPUT
out BF_REQ_CTP_2_INPUTstd_logic
Definition: CMX_top_Base.vhd:519
CMX_top_Base.P14_15
in P14_15std_logic
Definition: CMX_top_Base.vhd:456
CMX_top_Base.P9_5
in P9_5std_logic
Definition: CMX_top_Base.vhd:321
CMX_top_Base.Behavioral.vme_inreg_notri
vme_inreg_notri
Definition: CMX_top_Base.vhd:899
SFP_Data_TXRX.clk40_out
out clk40_outstd_logic
Definition: SFP_TXRX.vhd:46
CMX_crate_cable_output_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_crate_cable_output_module.vhd:31
CMX_top_Base.P9_19
in P9_19std_logic
Definition: CMX_top_Base.vhd:335
glink_interface.DAQ_BYTE
out DAQ_BYTEstd_logic_vector (7 downto 0)
Definition: glink_interface.vhd:26
vme_outreg_notri_async.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl_notri_async.vhd:18
CMX_top_Base.D_CBL_46_B
out D_CBL_46_Bstd_logic
Definition: CMX_top_Base.vhd:654
CMX_top_Base.P7_8
in P7_8std_logic
Definition: CMX_top_Base.vhd:274
CMX_top_Base.MP1_F02_QUAD_112_TRN_2_CMP
out MP1_F02_QUAD_112_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:730
CMX_top_Base.P14_0
in P14_0std_logic
Definition: CMX_top_Base.vhd:441
CMX_top_Base.P2_2
in P2_2std_logic
Definition: CMX_top_Base.vhd:143
CMX_top_Base.P10_0
in P10_0std_logic
Definition: CMX_top_Base.vhd:341
sys_monitor.bus_drive
out bus_drivestd_logic
Definition: sys_monitor.vhd:59
CMX_top_Base.MP2_F00_QUAD_115_TRN_3_CMP
out MP2_F00_QUAD_115_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:756
CMX_top_Base.P6_2
in P6_2std_logic
Definition: CMX_top_Base.vhd:243
vme_outreg_notri_async.ds
in dsstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:24
decoder.pll_locked
in pll_lockedstd_logic
Definition: jet_decoder.vhd:46
CMX_top_Base.P10_7
in P10_7std_logic
Definition: CMX_top_Base.vhd:348
CMX_local_package.IEEE
_library_ IEEEIEEE
Definition: CMX_local_package.vhd:7
sys_monitor.BF_SYSMON_12_N
in BF_SYSMON_12_NSTD_LOGIC
Definition: sys_monitor.vhd:45
CMX_top_Base.P10_22
in P10_22std_logic
Definition: CMX_top_Base.vhd:363
adder_top.thresholds
in thresholdsarr_16 (max_jems * 25 * 4 - 1 downto 0)
Definition: adder_top_vs.vhd:36
CMX_top_Base.P4_5
in P4_5std_logic
Definition: CMX_top_Base.vhd:196
CMX_top_Base.P8_4
in P8_4std_logic
Definition: CMX_top_Base.vhd:295
CMX_top_Base.P7_1
in P7_1std_logic
Definition: CMX_top_Base.vhd:267
Topo_Data_TX.clk40
in clk40std_logic
Definition: Topo_Data_TX.vhd:38
sys_monitor
Definition: sys_monitor.vhd:20
CMX_top_Base.MP2_F05_QUAD_113_TRN_3_CMP
out MP2_F05_QUAD_113_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:740
CMX_top_Base.MP1_F08_QUAD_111_TRN_3_DIR
out MP1_F08_QUAD_111_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:723
CMX_top_Base.Behavioral.write_detect_inreg_test
std_logic write_detect_inreg_test
Definition: CMX_top_Base.vhd:937
Topo_Data_TX.pll_locked
in pll_lockedstd_logic
Definition: Topo_Data_TX.vhd:40
decoder.clk40MHz_m180o
in clk40MHz_m180ostd_logic
Definition: jet_decoder.vhd:45
CMX_top_Base.Behavioral.vme_inreg_notri_async
vme_inreg_notri_async
Definition: CMX_top_Base.vhd:869
CMX_top_Base.P15_1
in P15_1std_logic
Definition: CMX_top_Base.vhd:467
vme_inreg_notri.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:32
CMX_top_Base.OCB_D
inout OCB_Dstd_logic_vector (15 downto 0)
Definition: CMX_top_Base.vhd:62
CMX_top_Base.P13_10
in P13_10std_logic
Definition: CMX_top_Base.vhd:426
CMX_top_Base.D_CBL_35_B
in D_CBL_35_Bstd_logic
Definition: CMX_top_Base.vhd:643
SFP_Data_TXRX.DFETAPOVRD
in DFETAPOVRDstd_logic
Definition: SFP_TXRX.vhd:69
CMX_version.ds
in dsstd_logic
Definition: CMX_version.vhd:24
adder_top.dout_cblb_mux1
out dout_cblb_mux1std_logic_vector (33 downto 0)
Definition: adder_top_vs.vhd:47
CMX_top_Base.P0_2
in P0_2std_logic
Definition: CMX_top_Base.vhd:93
CMX_top_Base.P10_20
in P10_20std_logic
Definition: CMX_top_Base.vhd:361
CMX_top_Base.P2_8
in P2_8std_logic
Definition: CMX_top_Base.vhd:149
CMX_top_Base.P5_5
in P5_5std_logic
Definition: CMX_top_Base.vhd:221
vme_inreg_async.ncs
in ncsstd_logic
Definition: vme_inreg_async_rtl.vhd:25
CMX_clock_manager.IB_DS1
in IB_DS1std_logic
Definition: CMX_clock_manager.vhd:31
CMX_top_Base.P15_11
in P15_11std_logic
Definition: CMX_top_Base.vhd:477
CMX_top_Base.BF_DOUT_CTP_02
out BF_DOUT_CTP_02std_logic
Definition: CMX_top_Base.vhd:540
decoder.bus_drive
out bus_drivestd_logic
Definition: jet_decoder.vhd:69
CMX_top_Base.MP1_F01_QUAD_110_TRN_0_CMP
out MP1_F01_QUAD_110_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:710
CMX_top_Base.P3_9
in P3_9std_logic
Definition: CMX_top_Base.vhd:175
CMX_top_Base.D_CBL_31_B
in D_CBL_31_Bstd_logic
Definition: CMX_top_Base.vhd:639
vme_inreg_async.data_vme
inout data_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_async_rtl.vhd:30
decoder.max_jems
max_jemsinteger :=16
Definition: jet_decoder.vhd:33
vme_outreg_notri.read_detect
out read_detectstd_logic
Definition: vme_outreg_rtl_notri.vhd:31
adder_top.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: adder_top_vs.vhd:53
vme_outreg_notri_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:30
CMX_top_Base.D_CBL_13_B
out D_CBL_13_Bstd_logic
Definition: CMX_top_Base.vhd:619
CMX_top_Base.CLK_40MHz08_DSKW_1_BF_LOGIC_DIR
in CLK_40MHz08_DSKW_1_BF_LOGIC_DIRstd_logic
Definition: CMX_top_Base.vhd:496
CMX_top_Base.BF_DOUT_CTP_13
out BF_DOUT_CTP_13std_logic
Definition: CMX_top_Base.vhd:551
CMX_top_Base.P13_1
in P13_1std_logic
Definition: CMX_top_Base.vhd:417
CMX_top_Base.Behavioral.CMX_version
CMX_version
Definition: CMX_top_Base.vhd:948
CMX_top_Base.MP2_F02_QUAD_115_TRN_2_CMP
out MP2_F02_QUAD_115_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:754
CMX_top_Base.P15_7
in P15_7std_logic
Definition: CMX_top_Base.vhd:473
CMX_top_Base.MP2_F06_QUAD_115_TRN_1_CMP
out MP2_F06_QUAD_115_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:752
CMX_top_Base.D_CBL_61_B
out D_CBL_61_Bstd_logic
Definition: CMX_top_Base.vhd:671
CMX_version.clk40
in clk40std_logic
Definition: CMX_version.vhd:21
CMX_clock_manager.buf_clk40_ds2
out buf_clk40_ds2std_logic
Definition: CMX_clock_manager.vhd:42
CMX_system_cable_input_module.pll_locked_ds2
in pll_locked_ds2std_logic
Definition: CMX_system_cable_input_module.vhd:38
CMX_top_Base.P6_17
in P6_17std_logic
Definition: CMX_top_Base.vhd:258
CMX_top_Base.P5_3
in P5_3std_logic
Definition: CMX_top_Base.vhd:219
CMX_top_Base.BF_DOUT_CTP_59
out BF_DOUT_CTP_59std_logic
Definition: CMX_top_Base.vhd:599
CMX_top_Base.D_CBL_71_B
out D_CBL_71_Bstd_logic
Definition: CMX_top_Base.vhd:681
glink_interface.ROI_DAV
in ROI_DAVstd_logic
Definition: glink_interface.vhd:25
CMX_input_module.buf_clk200
in buf_clk200std_logic
Definition: CMX_input_module.vhd:30
CMX_top_Base.CLK_40MHz08_DSKW_2_BF_LOGIC_DIR
in CLK_40MHz08_DSKW_2_BF_LOGIC_DIRstd_logic
Definition: CMX_top_Base.vhd:499
CMX_top_Base.BF_TO_TP_ROI_SLINK_RETURN_DIR
in BF_TO_TP_ROI_SLINK_RETURN_DIRstd_logic
Definition: CMX_top_Base.vhd:695
CMX_input_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_input_module.vhd:58
CMX_top_Base.BF_DOUT_CTP_56
out BF_DOUT_CTP_56std_logic
Definition: CMX_top_Base.vhd:596
vme_outreg_notri
Definition: vme_outreg_rtl_notri.vhd:14
CMX_top_Base.P15_17
in P15_17std_logic
Definition: CMX_top_Base.vhd:483
Topo_Data_TX.GTXTXRESET_IN
in GTXTXRESET_INstd_logic
Definition: Topo_Data_TX.vhd:29
CMX_top_Base.MP2_F07_QUAD_113_TRN_2_CMP
out MP2_F07_QUAD_113_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:738
CMX_top_Base.P4_7
in P4_7std_logic
Definition: CMX_top_Base.vhd:198
CMX_top_Base.P2_20
in P2_20std_logic
Definition: CMX_top_Base.vhd:161
CMX_top_Base.D_CBL_19_B
out D_CBL_19_Bstd_logic
Definition: CMX_top_Base.vhd:625
adder_top.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: adder_top_vs.vhd:52
CMX_top_Base.P14_23
in P14_23std_logic
Definition: CMX_top_Base.vhd:464
CMX_top_Base.BF_DOUT_CTP_11
out BF_DOUT_CTP_11std_logic
Definition: CMX_top_Base.vhd:549
CMX_top_Base.P3_17
in P3_17std_logic
Definition: CMX_top_Base.vhd:183
decoder.counter_reset
in counter_resetstd_logic
Definition: jet_decoder.vhd:62
vme_inreg
Definition: vme_inreg_rtl.vhd:19
CMX_top_Base.BF_DOUT_CTP_36
out BF_DOUT_CTP_36std_logic
Definition: CMX_top_Base.vhd:576
vme_inreg_notri.ds
in dsstd_logic
Definition: vme_inreg_rtl_notri.vhd:29
CMX_top_Base.MP1_F03_QUAD_110_TRN_1_DIR
out MP1_F03_QUAD_110_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:711
CMX_top_Base.D_CBL_66_B
out D_CBL_66_Bstd_logic
Definition: CMX_top_Base.vhd:676
daq_glink.data_out
out data_outstd_logic_vector (19 downto 0)
Definition: daq_glink.vhd:29
vme_local_switch.bus_drive_from_below
in bus_drive_from_belowstd_logic_vector
Definition: vme_local_switch.vhd:40
SFP_Data_TXRX.RXP_IN
in RXP_INstd_logic
Definition: SFP_TXRX.vhd:43
CMX_top_Base.P11_15
in P11_15std_logic
Definition: CMX_top_Base.vhd:381
CMX_top_Base.P5_23
in P5_23std_logic
Definition: CMX_top_Base.vhd:239
CMX_top_Base.P13_16
in P13_16std_logic
Definition: CMX_top_Base.vhd:432
CMX_top_Base.P9_0
in P9_0std_logic
Definition: CMX_top_Base.vhd:316
vme_inreg_notri_async
Definition: vme_inreg_rtl_notri_async.vhd:18
CMX_top_Base.P1_12
in P1_12std_logic
Definition: CMX_top_Base.vhd:128
CMX_delay_generator.start_address
start_addressinteger
Definition: CMX_delay_generator.vhd:30
CMX_top_Base.BF_SYSMON_12_N
in BF_SYSMON_12_NSTD_LOGIC
Definition: CMX_top_Base.vhd:82
adder_top.rd_nwr
in rd_nwrstd_logic
Definition: adder_top_vs.vhd:50
adder_top.ADDR_REG_RW_PIPELINE_DELAY_LENGTH
ADDR_REG_RW_PIPELINE_DELAY_LENGTHinteger :=0
Definition: adder_top_vs.vhd:31
CMX_top_Base.P8_22
in P8_22std_logic
Definition: CMX_top_Base.vhd:313
CMX_top_Base.BF_DEBUG_1
out BF_DEBUG_1std_logic
Definition: CMX_top_Base.vhd:507
CMX_top_Base.D_CBL_02_B
out D_CBL_02_Bstd_logic
Definition: CMX_top_Base.vhd:608
CMX_top_Base.D_CBL_52_B
out D_CBL_52_Bstd_logic
Definition: CMX_top_Base.vhd:660
CMX_top_Base.P11_17
in P11_17std_logic
Definition: CMX_top_Base.vhd:383
CMX_top_Base.D_CBL_18_B
out D_CBL_18_Bstd_logic
Definition: CMX_top_Base.vhd:624
CMX_top_Base.D_CBL_10_B
out D_CBL_10_Bstd_logic
Definition: CMX_top_Base.vhd:616
CMX_top_Base.P10_17
in P10_17std_logic
Definition: CMX_top_Base.vhd:358
daq_collector.din_lcl
in din_lclT_SLV60
Definition: daq_collector.vhd:28
CMX_top_Base.MP2_F06_QUAD_115_TRN_1_DIR
out MP2_F06_QUAD_115_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:751
CMX_top_Base.BF_DOUT_CTP_12
out BF_DOUT_CTP_12std_logic
Definition: CMX_top_Base.vhd:550
CMX_crate_cable_output_module.bus_drive
out bus_drivestd_logic
Definition: CMX_crate_cable_output_module.vhd:44
CMX_top_Base.D_CBL_45_B
out D_CBL_45_Bstd_logic
Definition: CMX_top_Base.vhd:653