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CMX_top_Base.vhd
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1 ----------------------------------------------------------------------------------
7 ----------------------------------------------------------------------------------
8 library IEEE;
9 use IEEE.STD_LOGIC_1164.ALL;
10 use IEEE.NUMERIC_STD.ALL;
11 
12 library UNISIM;
13 use UNISIM.VComponents.all;
14 
15 library work;
16 use work.CMXpackage.all;
17 use work.CMX_VME_defs.all;
18 use work.CMX_local_package.all;
19 use work.CMX_flavor_package.all;
20 
21 
22 
23 entity CMX_top_Base is
24  port (
25 
26  ----------------------------------------------------------------------------
27  -- VME-- backplane (65 signals)
28  ----------------------------------------------------------------------------
29  --GEOADDR0: in std_logic; -- GeoAddr0
30  OCB_GEO_ADRS_0: in std_logic;
31  --VMEADDR: in std_logic_vector(23 downto 1); -- Address bus
32  OCB_A01: in std_logic;
33  OCB_A02: in std_logic;
34  OCB_A03: in std_logic;
35  OCB_A04: in std_logic;
36  OCB_A05: in std_logic;
37  OCB_A06: in std_logic;
38  OCB_A07: in std_logic;
39  OCB_A08: in std_logic;
40  OCB_A09: in std_logic;
41  OCB_A10: in std_logic;
42  OCB_A11: in std_logic;
43  OCB_A12: in std_logic;
44  OCB_A13: in std_logic;
45  OCB_A14: in std_logic;
46  OCB_A15: in std_logic;
47  OCB_A16: in std_logic;
48  OCB_A17: in std_logic;
49  OCB_A18: in std_logic;
50  OCB_A19: in std_logic;
51  OCB_A20: in std_logic;
52  OCB_A21: in std_logic;
53  OCB_A22: in std_logic;
54  OCB_A23: in std_logic;
55  --VMEDS_L: in std_logic; -- DS strobe VMEDS_L
56  OCB_DS_B: in std_logic;
57  --VMEWR_L: in std_logic; -- VME Write VMEWR_L
58  OCB_WRITE_B: in std_logic;
59  --VMERST_L: in std_logic; -- System reset VMERST_L
60  OCB_SYS_RESET_B: in std_logic;
61  --VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA
62  OCB_D: inout std_logic_vector(15 downto 0);
63  ----------------------------------------------------------------------------
64  --system monitor
65  BF_SYSMON_01_P : in STD_LOGIC; -- Auxiliary Channel 1
66  BF_SYSMON_01_N : in STD_LOGIC;
67  BF_SYSMON_03_P : in STD_LOGIC; -- Auxiliary Channel 3
68  BF_SYSMON_03_N : in STD_LOGIC;
69  BF_SYSMON_04_P : in STD_LOGIC; -- Auxiliary Channel 4
70  BF_SYSMON_04_N : in STD_LOGIC;
71  BF_SYSMON_07_P : in STD_LOGIC; -- Auxiliary Channel 7
72  BF_SYSMON_07_N : in STD_LOGIC;
73  BF_SYSMON_08_P : in STD_LOGIC; -- Auxiliary Channel 8
74  BF_SYSMON_08_N : in STD_LOGIC;
75  BF_SYSMON_09_P : in STD_LOGIC; -- Auxiliary Channel 9
76  BF_SYSMON_09_N : in STD_LOGIC;
77  BF_SYSMON_10_P : in STD_LOGIC; -- Auxiliary Channel 10
78  BF_SYSMON_10_N : in STD_LOGIC;
79  BF_SYSMON_11_P : in STD_LOGIC; -- Auxiliary Channel 11
80  BF_SYSMON_11_N : in STD_LOGIC;
81  BF_SYSMON_12_P : in STD_LOGIC; -- Auxiliary Channel 12
82  BF_SYSMON_12_N : in STD_LOGIC;
83  BF_SYSMON_13_P : in STD_LOGIC; -- Auxiliary Channel 13
84  BF_SYSMON_13_N : in STD_LOGIC;
85  BF_SYSMON_14_P : in STD_LOGIC; -- Auxiliary Channel 14
86  BF_SYSMON_14_N : in STD_LOGIC;
87  BF_SYSMON_15_P : in STD_LOGIC; -- Auxiliary Channel 15
88  BF_SYSMON_15_N : in STD_LOGIC;
89 
90  --backplane
91  P0_0 : in std_logic;
92  P0_1 : in std_logic;
93  P0_2 : in std_logic;
94  P0_3 : in std_logic;
95  P0_4 : in std_logic;
96  P0_5 : in std_logic;
97  P0_6 : in std_logic;
98  P0_7 : in std_logic;
99  P0_8 : in std_logic;
100  P0_9 : in std_logic;
101  P0_10 : in std_logic;
102  P0_11 : in std_logic;
103  P0_12 : in std_logic;
104  P0_13 : in std_logic;
105  P0_14 : in std_logic;
106  P0_15 : in std_logic;
107  P0_16 : in std_logic;
108  P0_17 : in std_logic;
109  P0_18 : in std_logic;
110  P0_19 : in std_logic;
111  P0_20 : in std_logic;
112  P0_21 : in std_logic;
113  P0_22 : in std_logic;
114  P0_23 : in std_logic;
115  P0_24 : in std_logic;
116  P1_0 : in std_logic;
117  P1_1 : in std_logic;
118  P1_2 : in std_logic;
119  P1_3 : in std_logic;
120  P1_4 : in std_logic;
121  P1_5 : in std_logic;
122  P1_6 : in std_logic;
123  P1_7 : in std_logic;
124  P1_8 : in std_logic;
125  P1_9 : in std_logic;
126  P1_10 : in std_logic;
127  P1_11 : in std_logic;
128  P1_12 : in std_logic;
129  P1_13 : in std_logic;
130  P1_14 : in std_logic;
131  P1_15 : in std_logic;
132  P1_16 : in std_logic;
133  P1_17 : in std_logic;
134  P1_18 : in std_logic;
135  P1_19 : in std_logic;
136  P1_20 : in std_logic;
137  P1_21 : in std_logic;
138  P1_22 : in std_logic;
139  P1_23 : in std_logic;
140  P1_24 : in std_logic;
141  P2_0 : in std_logic;
142  P2_1 : in std_logic;
143  P2_2 : in std_logic;
144  P2_3 : in std_logic;
145  P2_4 : in std_logic;
146  P2_5 : in std_logic;
147  P2_6 : in std_logic;
148  P2_7 : in std_logic;
149  P2_8 : in std_logic;
150  P2_9 : in std_logic;
151  P2_10 : in std_logic;
152  P2_11 : in std_logic;
153  P2_12 : in std_logic;
154  P2_13 : in std_logic;
155  P2_14 : in std_logic;
156  P2_15 : in std_logic;
157  P2_16 : in std_logic;
158  P2_17 : in std_logic;
159  P2_18 : in std_logic;
160  P2_19 : in std_logic;
161  P2_20 : in std_logic;
162  P2_21 : in std_logic;
163  P2_22 : in std_logic;
164  P2_23 : in std_logic;
165  P2_24 : in std_logic;
166  P3_0 : in std_logic;
167  P3_1 : in std_logic;
168  P3_2 : in std_logic;
169  P3_3 : in std_logic;
170  P3_4 : in std_logic;
171  P3_5 : in std_logic;
172  P3_6 : in std_logic;
173  P3_7 : in std_logic;
174  P3_8 : in std_logic;
175  P3_9 : in std_logic;
176  P3_10 : in std_logic;
177  P3_11 : in std_logic;
178  P3_12 : in std_logic;
179  P3_13 : in std_logic;
180  P3_14 : in std_logic;
181  P3_15 : in std_logic;
182  P3_16 : in std_logic;
183  P3_17 : in std_logic;
184  P3_18 : in std_logic;
185  P3_19 : in std_logic;
186  P3_20 : in std_logic;
187  P3_21 : in std_logic;
188  P3_22 : in std_logic;
189  P3_23 : in std_logic;
190  P3_24 : in std_logic;
191  P4_0 : in std_logic;
192  P4_1 : in std_logic;
193  P4_2 : in std_logic;
194  P4_3 : in std_logic;
195  P4_4 : in std_logic;
196  P4_5 : in std_logic;
197  P4_6 : in std_logic;
198  P4_7 : in std_logic;
199  P4_8 : in std_logic;
200  P4_9 : in std_logic;
201  P4_10 : in std_logic;
202  P4_11 : in std_logic;
203  P4_12 : in std_logic;
204  P4_13 : in std_logic;
205  P4_14 : in std_logic;
206  P4_15 : in std_logic;
207  P4_16 : in std_logic;
208  P4_17 : in std_logic;
209  P4_18 : in std_logic;
210  P4_19 : in std_logic;
211  P4_20 : in std_logic;
212  P4_21 : in std_logic;
213  P4_22 : in std_logic;
214  P4_23 : in std_logic;
215  P4_24 : in std_logic;
216  P5_0 : in std_logic;
217  P5_1 : in std_logic;
218  P5_2 : in std_logic;
219  P5_3 : in std_logic;
220  P5_4 : in std_logic;
221  P5_5 : in std_logic;
222  P5_6 : in std_logic;
223  P5_7 : in std_logic;
224  P5_8 : in std_logic;
225  P5_9 : in std_logic;
226  P5_10 : in std_logic;
227  P5_11 : in std_logic;
228  P5_12 : in std_logic;
229  P5_13 : in std_logic;
230  P5_14 : in std_logic;
231  P5_15 : in std_logic;
232  P5_16 : in std_logic;
233  P5_17 : in std_logic;
234  P5_18 : in std_logic;
235  P5_19 : in std_logic;
236  P5_20 : in std_logic;
237  P5_21 : in std_logic;
238  P5_22 : in std_logic;
239  P5_23 : in std_logic;
240  P5_24 : in std_logic;
241  P6_0 : in std_logic;
242  P6_1 : in std_logic;
243  P6_2 : in std_logic;
244  P6_3 : in std_logic;
245  P6_4 : in std_logic;
246  P6_5 : in std_logic;
247  P6_6 : in std_logic;
248  P6_7 : in std_logic;
249  P6_8 : in std_logic;
250  P6_9 : in std_logic;
251  P6_10 : in std_logic;
252  P6_11 : in std_logic;
253  P6_12 : in std_logic;
254  P6_13 : in std_logic;
255  P6_14 : in std_logic;
256  P6_15 : in std_logic;
257  P6_16 : in std_logic;
258  P6_17 : in std_logic;
259  P6_18 : in std_logic;
260  P6_19 : in std_logic;
261  P6_20 : in std_logic;
262  P6_21 : in std_logic;
263  P6_22 : in std_logic;
264  P6_23 : in std_logic;
265  P6_24 : in std_logic;
266  P7_0 : in std_logic;
267  P7_1 : in std_logic;
268  P7_2 : in std_logic;
269  P7_3 : in std_logic;
270  P7_4 : in std_logic;
271  P7_5 : in std_logic;
272  P7_6 : in std_logic;
273  P7_7 : in std_logic;
274  P7_8 : in std_logic;
275  P7_9 : in std_logic;
276  P7_10 : in std_logic;
277  P7_11 : in std_logic;
278  P7_12 : in std_logic;
279  P7_13 : in std_logic;
280  P7_14 : in std_logic;
281  P7_15 : in std_logic;
282  P7_16 : in std_logic;
283  P7_17 : in std_logic;
284  P7_18 : in std_logic;
285  P7_19 : in std_logic;
286  P7_20 : in std_logic;
287  P7_21 : in std_logic;
288  P7_22 : in std_logic;
289  P7_23 : in std_logic;
290  P7_24 : in std_logic;
291  P8_0 : in std_logic;
292  P8_1 : in std_logic;
293  P8_2 : in std_logic;
294  P8_3 : in std_logic;
295  P8_4 : in std_logic;
296  P8_5 : in std_logic;
297  P8_6 : in std_logic;
298  P8_7 : in std_logic;
299  P8_8 : in std_logic;
300  P8_9 : in std_logic;
301  P8_10 : in std_logic;
302  P8_11 : in std_logic;
303  P8_12 : in std_logic;
304  P8_13 : in std_logic;
305  P8_14 : in std_logic;
306  P8_15 : in std_logic;
307  P8_16 : in std_logic;
308  P8_17 : in std_logic;
309  P8_18 : in std_logic;
310  P8_19 : in std_logic;
311  P8_20 : in std_logic;
312  P8_21 : in std_logic;
313  P8_22 : in std_logic;
314  P8_23 : in std_logic;
315  P8_24 : in std_logic;
316  P9_0 : in std_logic;
317  P9_1 : in std_logic;
318  P9_2 : in std_logic;
319  P9_3 : in std_logic;
320  P9_4 : in std_logic;
321  P9_5 : in std_logic;
322  P9_6 : in std_logic;
323  P9_7 : in std_logic;
324  P9_8 : in std_logic;
325  P9_9 : in std_logic;
326  P9_10 : in std_logic;
327  P9_11 : in std_logic;
328  P9_12 : in std_logic;
329  P9_13 : in std_logic;
330  P9_14 : in std_logic;
331  P9_15 : in std_logic;
332  P9_16 : in std_logic;
333  P9_17 : in std_logic;
334  P9_18 : in std_logic;
335  P9_19 : in std_logic;
336  P9_20 : in std_logic;
337  P9_21 : in std_logic;
338  P9_22 : in std_logic;
339  P9_23 : in std_logic;
340  P9_24 : in std_logic;
341  P10_0 : in std_logic;
342  P10_1 : in std_logic;
343  P10_2 : in std_logic;
344  P10_3 : in std_logic;
345  P10_4 : in std_logic;
346  P10_5 : in std_logic;
347  P10_6 : in std_logic;
348  P10_7 : in std_logic;
349  P10_8 : in std_logic;
350  P10_9 : in std_logic;
351  P10_10 : in std_logic;
352  P10_11 : in std_logic;
353  P10_12 : in std_logic;
354  P10_13 : in std_logic;
355  P10_14 : in std_logic;
356  P10_15 : in std_logic;
357  P10_16 : in std_logic;
358  P10_17 : in std_logic;
359  P10_18 : in std_logic;
360  P10_19 : in std_logic;
361  P10_20 : in std_logic;
362  P10_21 : in std_logic;
363  P10_22 : in std_logic;
364  P10_23 : in std_logic;
365  P10_24 : in std_logic;
366  P11_0 : in std_logic;
367  P11_1 : in std_logic;
368  P11_2 : in std_logic;
369  P11_3 : in std_logic;
370  P11_4 : in std_logic;
371  P11_5 : in std_logic;
372  P11_6 : in std_logic;
373  P11_7 : in std_logic;
374  P11_8 : in std_logic;
375  P11_9 : in std_logic;
376  P11_10 : in std_logic;
377  P11_11 : in std_logic;
378  P11_12 : in std_logic;
379  P11_13 : in std_logic;
380  P11_14 : in std_logic;
381  P11_15 : in std_logic;
382  P11_16 : in std_logic;
383  P11_17 : in std_logic;
384  P11_18 : in std_logic;
385  P11_19 : in std_logic;
386  P11_20 : in std_logic;
387  P11_21 : in std_logic;
388  P11_22 : in std_logic;
389  P11_23 : in std_logic;
390  P11_24 : in std_logic;
391  P12_0 : in std_logic;
392  P12_1 : in std_logic;
393  P12_2 : in std_logic;
394  P12_3 : in std_logic;
395  P12_4 : in std_logic;
396  P12_5 : in std_logic;
397  P12_6 : in std_logic;
398  P12_7 : in std_logic;
399  P12_8 : in std_logic;
400  P12_9 : in std_logic;
401  P12_10 : in std_logic;
402  P12_11 : in std_logic;
403  P12_12 : in std_logic;
404  P12_13 : in std_logic;
405  P12_14 : in std_logic;
406  P12_15 : in std_logic;
407  P12_16 : in std_logic;
408  P12_17 : in std_logic;
409  P12_18 : in std_logic;
410  P12_19 : in std_logic;
411  P12_20 : in std_logic;
412  P12_21 : in std_logic;
413  P12_22 : in std_logic;
414  P12_23 : in std_logic;
415  P12_24 : in std_logic;
416  P13_0 : in std_logic;
417  P13_1 : in std_logic;
418  P13_2 : in std_logic;
419  P13_3 : in std_logic;
420  P13_4 : in std_logic;
421  P13_5 : in std_logic;
422  P13_6 : in std_logic;
423  P13_7 : in std_logic;
424  P13_8 : in std_logic;
425  P13_9 : in std_logic;
426  P13_10 : in std_logic;
427  P13_11 : in std_logic;
428  P13_12 : in std_logic;
429  P13_13 : in std_logic;
430  P13_14 : in std_logic;
431  P13_15 : in std_logic;
432  P13_16 : in std_logic;
433  P13_17 : in std_logic;
434  P13_18 : in std_logic;
435  P13_19 : in std_logic;
436  P13_20 : in std_logic;
437  P13_21 : in std_logic;
438  P13_22 : in std_logic;
439  P13_23 : in std_logic;
440  P13_24 : in std_logic;
441  P14_0 : in std_logic;
442  P14_1 : in std_logic;
443  P14_2 : in std_logic;
444  P14_3 : in std_logic;
445  P14_4 : in std_logic;
446  P14_5 : in std_logic;
447  P14_6 : in std_logic;
448  P14_7 : in std_logic;
449  P14_8 : in std_logic;
450  P14_9 : in std_logic;
451  P14_10 : in std_logic;
452  P14_11 : in std_logic;
453  P14_12 : in std_logic;
454  P14_13 : in std_logic;
455  P14_14 : in std_logic;
456  P14_15 : in std_logic;
457  P14_16 : in std_logic;
458  P14_17 : in std_logic;
459  P14_18 : in std_logic;
460  P14_19 : in std_logic;
461  P14_20 : in std_logic;
462  P14_21 : in std_logic;
463  P14_22 : in std_logic;
464  P14_23 : in std_logic;
465  P14_24 : in std_logic;
466  P15_0 : in std_logic;
467  P15_1 : in std_logic;
468  P15_2 : in std_logic;
469  P15_3 : in std_logic;
470  P15_4 : in std_logic;
471  P15_5 : in std_logic;
472  P15_6 : in std_logic;
473  P15_7 : in std_logic;
474  P15_8 : in std_logic;
475  P15_9 : in std_logic;
476  P15_10 : in std_logic;
477  P15_11 : in std_logic;
478  P15_12 : in std_logic;
479  P15_13 : in std_logic;
480  P15_14 : in std_logic;
481  P15_15 : in std_logic;
482  P15_16 : in std_logic;
483  P15_17 : in std_logic;
484  P15_18 : in std_logic;
485  P15_19 : in std_logic;
486  P15_20 : in std_logic;
487  P15_21 : in std_logic;
488  P15_22 : in std_logic;
489  P15_23 : in std_logic;
490  P15_24 : in std_logic;
491 
492 
493  --CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
494  --CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
495 
496  CLK_40MHz08_DSKW_1_BF_LOGIC_DIR : in std_logic;
497  CLK_40MHz08_DSKW_1_BF_LOGIC_CMP : in std_logic;
498 
499  CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
500  CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
501 
502 
503  --CLK_320MHz64_LHC_BF_LOGIC_DIR : in std_logic;
504  --CLK_320MHz64_LHC_BF_LOGIC_CMP : in std_logic;
505 
506  BF_DEBUG_0 : out std_logic;
507  BF_DEBUG_1 : out std_logic;
508  BF_DEBUG_2 : out std_logic;
509  BF_DEBUG_3 : out std_logic;
510  BF_DEBUG_4 : out std_logic;
511  BF_DEBUG_5 : out std_logic;
512  BF_DEBUG_6 : out std_logic;
513  BF_DEBUG_7 : out std_logic;
514  BF_DEBUG_8 : out std_logic;
515  BF_DEBUG_9 : out std_logic;
516 
517 
518  BF_REQ_CTP_1_INPUT : out std_logic;
519  BF_REQ_CTP_2_INPUT : out std_logic;
520  BF_REQ_CABLE_1_INPUT: out std_logic;
521  BF_REQ_CABLE_2_INPUT: out std_logic;
522  BF_REQ_CABLE_3_INPUT: out std_logic;
523  BF_LED_REQ_0 : out std_logic;
524  BF_LED_REQ_1 : out std_logic;
525  BF_LED_REQ_2 : out std_logic;
526  BF_LED_REQ_3 : out std_logic;
527  BF_LED_REQ_4 : out std_logic;
528  BF_TO_FROM_BSPT_0 : in std_logic;
529  BF_TO_FROM_BSPT_1 : in std_logic;
530  BF_TO_FROM_BSPT_2 : out std_logic;
531  BF_TO_FROM_BSPT_3 : out std_logic;
532  BF_TO_FROM_BSPT_4 : out std_logic;
533  BF_TO_FROM_BSPT_5 : out std_logic;
534  BF_TO_FROM_BSPT_6 : out std_logic;
535  BF_TO_FROM_BSPT_7 : out std_logic;
536 
537 
538  BF_DOUT_CTP_00 : out std_logic;
539  BF_DOUT_CTP_01 : out std_logic;
540  BF_DOUT_CTP_02 : out std_logic;
541  BF_DOUT_CTP_03 : out std_logic;
542  BF_DOUT_CTP_04 : out std_logic;
543  BF_DOUT_CTP_05 : out std_logic;
544  BF_DOUT_CTP_06 : out std_logic;
545  BF_DOUT_CTP_07 : out std_logic;
546  BF_DOUT_CTP_08 : out std_logic;
547  BF_DOUT_CTP_09 : out std_logic;
548  BF_DOUT_CTP_10 : out std_logic;
549  BF_DOUT_CTP_11 : out std_logic;
550  BF_DOUT_CTP_12 : out std_logic;
551  BF_DOUT_CTP_13 : out std_logic;
552  BF_DOUT_CTP_14 : out std_logic;
553  BF_DOUT_CTP_15 : out std_logic;
554  BF_DOUT_CTP_16 : out std_logic;
555  BF_DOUT_CTP_17 : out std_logic;
556  BF_DOUT_CTP_18 : out std_logic;
557  BF_DOUT_CTP_19 : out std_logic;
558  BF_DOUT_CTP_20 : out std_logic;
559  BF_DOUT_CTP_21 : out std_logic;
560  BF_DOUT_CTP_22 : out std_logic;
561  BF_DOUT_CTP_23 : out std_logic;
562  BF_DOUT_CTP_24 : out std_logic;
563  BF_DOUT_CTP_25 : out std_logic;
564  BF_DOUT_CTP_26 : out std_logic;
565  BF_DOUT_CTP_27 : out std_logic;
566  BF_DOUT_CTP_28 : out std_logic;
567  BF_DOUT_CTP_29 : out std_logic;
568  BF_DOUT_CTP_30 : out std_logic;
569  BF_DOUT_CTP_31 : out std_logic;
570  BF_DOUT_CTP_64 : out std_logic;
571 
572  BF_DOUT_CTP_32 : out std_logic;
573  BF_DOUT_CTP_33 : out std_logic;
574  BF_DOUT_CTP_34 : out std_logic;
575  BF_DOUT_CTP_35 : out std_logic;
576  BF_DOUT_CTP_36 : out std_logic;
577  BF_DOUT_CTP_37 : out std_logic;
578  BF_DOUT_CTP_38 : out std_logic;
579  BF_DOUT_CTP_39 : out std_logic;
580  BF_DOUT_CTP_40 : out std_logic;
581  BF_DOUT_CTP_41 : out std_logic;
582  BF_DOUT_CTP_42 : out std_logic;
583  BF_DOUT_CTP_43 : out std_logic;
584  BF_DOUT_CTP_44 : out std_logic;
585  BF_DOUT_CTP_45 : out std_logic;
586  BF_DOUT_CTP_46 : out std_logic;
587  BF_DOUT_CTP_47 : out std_logic;
588  BF_DOUT_CTP_48 : out std_logic;
589  BF_DOUT_CTP_49 : out std_logic;
590  BF_DOUT_CTP_50 : out std_logic;
591  BF_DOUT_CTP_51 : out std_logic;
592  BF_DOUT_CTP_52 : out std_logic;
593  BF_DOUT_CTP_53 : out std_logic;
594  BF_DOUT_CTP_54 : out std_logic;
595  BF_DOUT_CTP_55 : out std_logic;
596  BF_DOUT_CTP_56 : out std_logic;
597  BF_DOUT_CTP_57 : out std_logic;
598  BF_DOUT_CTP_58 : out std_logic;
599  BF_DOUT_CTP_59 : out std_logic;
600  BF_DOUT_CTP_60 : out std_logic;
601  BF_DOUT_CTP_61 : out std_logic;
602  BF_DOUT_CTP_62 : out std_logic;
603  BF_DOUT_CTP_63 : out std_logic;
604  BF_DOUT_CTP_65 : out std_logic;
605 
606  D_CBL_00_B : in std_logic;
607  D_CBL_01_B : in std_logic;
608  D_CBL_02_B : in std_logic;
609  D_CBL_03_B : in std_logic;
610  D_CBL_04_B : in std_logic;
611  D_CBL_05_B : in std_logic;
612  D_CBL_06_B : in std_logic;
613  D_CBL_07_B : in std_logic;
614  D_CBL_08_B : in std_logic;
615  D_CBL_09_B : in std_logic;
616  D_CBL_10_B : in std_logic;
617  D_CBL_11_B : in std_logic;
618  D_CBL_12_B : in std_logic;
619  D_CBL_13_B : in std_logic;
620  D_CBL_14_B : in std_logic;
621  D_CBL_15_B : in std_logic;
622  D_CBL_16_B : in std_logic;
623  D_CBL_17_B : in std_logic;
624  D_CBL_18_B : in std_logic;
625  D_CBL_19_B : in std_logic;
626  D_CBL_20_B : in std_logic;
627  D_CBL_21_B : in std_logic;
628  D_CBL_22_B : in std_logic;
629  D_CBL_23_B : in std_logic;
630  D_CBL_24_B : in std_logic;
631  D_CBL_25_B : in std_logic;
632  D_CBL_26_B : in std_logic;
633  D_CBL_81_B : in std_logic;
634 
635  D_CBL_27_B : in std_logic;
636  D_CBL_28_B : in std_logic;
637  D_CBL_29_B : in std_logic;
638  D_CBL_30_B : in std_logic;
639  D_CBL_31_B : in std_logic;
640  D_CBL_32_B : in std_logic;
641  D_CBL_33_B : in std_logic;
642  D_CBL_34_B : in std_logic;
643  D_CBL_35_B : in std_logic;
644  D_CBL_36_B : in std_logic;
645  D_CBL_37_B : in std_logic;
646  D_CBL_38_B : in std_logic;
647  D_CBL_39_B : in std_logic;
648  D_CBL_40_B : in std_logic;
649  D_CBL_41_B : in std_logic;
650  D_CBL_42_B : in std_logic;
651  D_CBL_43_B : in std_logic;
652  D_CBL_44_B : in std_logic;
653  D_CBL_45_B : in std_logic;
654  D_CBL_46_B : in std_logic;
655  D_CBL_47_B : in std_logic;
656  D_CBL_48_B : in std_logic;
657  D_CBL_49_B : in std_logic;
658  D_CBL_50_B : in std_logic;
659  D_CBL_51_B : in std_logic;
660  D_CBL_52_B : in std_logic;
661  D_CBL_53_B : in std_logic;
662  D_CBL_82_B : in std_logic;
663 
664  D_CBL_54_B : in std_logic;
665  D_CBL_55_B : in std_logic;
666  D_CBL_56_B : in std_logic;
667  D_CBL_57_B : in std_logic;
668  D_CBL_58_B : in std_logic;
669  D_CBL_59_B : in std_logic;
670  D_CBL_60_B : in std_logic;
671  D_CBL_61_B : in std_logic;
672  D_CBL_62_B : in std_logic;
673  D_CBL_63_B : in std_logic;
674  D_CBL_64_B : in std_logic;
675  D_CBL_65_B : in std_logic;
676  D_CBL_66_B : in std_logic;
677  D_CBL_67_B : in std_logic;
678  D_CBL_68_B : in std_logic;
679  D_CBL_69_B : in std_logic;
680  D_CBL_70_B : in std_logic;
681  D_CBL_71_B : in std_logic;
682  D_CBL_72_B : in std_logic;
683  D_CBL_73_B : in std_logic;
684  D_CBL_74_B : in std_logic;
685  D_CBL_75_B : in std_logic;
686  D_CBL_76_B : in std_logic;
687  D_CBL_77_B : in std_logic;
688  D_CBL_78_B : in std_logic;
689  D_CBL_79_B : in std_logic;
690  D_CBL_80_B : in std_logic;
691  D_CBL_83_B : in std_logic;
692 
693  BF_TO_TP_DAQ_SLINK_RETURN_DIR : in std_logic;
694  BF_TO_TP_DAQ_SLINK_RETURN_CMP : in std_logic;
695  BF_TO_TP_ROI_SLINK_RETURN_DIR : in std_logic;
696  BF_TO_TP_ROI_SLINK_RETURN_CMP : in std_logic;
697 
698  BUF_TTC_L1_ACCEPT : in std_logic;
699  BUF_TTC_BNCH_CNT_RES : in std_logic;
700 
701  -- sfp
702  CLK_120MHz000_XTAL_1_BF_TRNCV_DIR: in std_logic;
703  CLK_120MHz000_XTAL_1_BF_TRNCV_CMP: in std_logic;
704  BF_DAQ_DATA_OUT_DIR : out std_logic;
705  BF_DAQ_DATA_OUT_CMP : out std_logic;
706  BF_ROI_DATA_OUT_DIR : out std_logic;
707  BF_ROI_DATA_OUT_CMP : out std_logic;
708 
709  MP1_F01_QUAD_110_TRN_0_DIR : out std_logic;
710  MP1_F01_QUAD_110_TRN_0_CMP : out std_logic;
711  MP1_F03_QUAD_110_TRN_1_DIR : out std_logic;
712  MP1_F03_QUAD_110_TRN_1_CMP : out std_logic;
713  MP1_F07_QUAD_110_TRN_2_DIR : out std_logic;
714  MP1_F07_QUAD_110_TRN_2_CMP : out std_logic;
715  MP1_F05_QUAD_110_TRN_3_DIR : out std_logic;
716  MP1_F05_QUAD_110_TRN_3_CMP : out std_logic;
717  MP1_F09_QUAD_111_TRN_0_DIR : out std_logic;
718  MP1_F09_QUAD_111_TRN_0_CMP : out std_logic;
719  MP1_F11_QUAD_111_TRN_1_DIR : out std_logic;
720  MP1_F11_QUAD_111_TRN_1_CMP : out std_logic;
721  MP1_F10_QUAD_111_TRN_2_DIR : out std_logic;
722  MP1_F10_QUAD_111_TRN_2_CMP : out std_logic;
723  MP1_F08_QUAD_111_TRN_3_DIR : out std_logic;
724  MP1_F08_QUAD_111_TRN_3_CMP : out std_logic;
725  MP1_F04_QUAD_112_TRN_0_DIR : out std_logic;
726  MP1_F04_QUAD_112_TRN_0_CMP : out std_logic;
727  MP1_F06_QUAD_112_TRN_1_DIR : out std_logic;
728  MP1_F06_QUAD_112_TRN_1_CMP : out std_logic;
729  MP1_F02_QUAD_112_TRN_2_DIR : out std_logic;
730  MP1_F02_QUAD_112_TRN_2_CMP : out std_logic;
731  MP1_F00_QUAD_112_TRN_3_DIR : out std_logic;
732  MP1_F00_QUAD_112_TRN_3_CMP : out std_logic;
733  MP2_F01_QUAD_113_TRN_0_DIR : out std_logic;
734  MP2_F01_QUAD_113_TRN_0_CMP : out std_logic;
735  MP2_F03_QUAD_113_TRN_1_DIR : out std_logic;
736  MP2_F03_QUAD_113_TRN_1_CMP : out std_logic;
737  MP2_F07_QUAD_113_TRN_2_DIR : out std_logic;
738  MP2_F07_QUAD_113_TRN_2_CMP : out std_logic;
739  MP2_F05_QUAD_113_TRN_3_DIR : out std_logic;
740  MP2_F05_QUAD_113_TRN_3_CMP : out std_logic;
741  MP2_F09_QUAD_114_TRN_0_DIR : out std_logic;
742  MP2_F09_QUAD_114_TRN_0_CMP : out std_logic;
743  MP2_F11_QUAD_114_TRN_1_DIR : out std_logic;
744  MP2_F11_QUAD_114_TRN_1_CMP : out std_logic;
745  MP2_F10_QUAD_114_TRN_2_DIR : out std_logic;
746  MP2_F10_QUAD_114_TRN_2_CMP : out std_logic;
747  MP2_F08_QUAD_114_TRN_3_DIR : out std_logic;
748  MP2_F08_QUAD_114_TRN_3_CMP : out std_logic;
749  MP2_F04_QUAD_115_TRN_0_DIR : out std_logic;
750  MP2_F04_QUAD_115_TRN_0_CMP : out std_logic;
751  MP2_F06_QUAD_115_TRN_1_DIR : out std_logic;
752  MP2_F06_QUAD_115_TRN_1_CMP : out std_logic;
753  MP2_F02_QUAD_115_TRN_2_DIR : out std_logic;
754  MP2_F02_QUAD_115_TRN_2_CMP : out std_logic;
755  MP2_F00_QUAD_115_TRN_3_DIR : out std_logic;
756  MP2_F00_QUAD_115_TRN_3_CMP : out std_logic;
757  CLK_320MHz64_LHC_BF_QUAD_111_DIR : in std_logic;
758  CLK_320MHz64_LHC_BF_QUAD_111_CMP : in std_logic;
759  CLK_320MHz64_LHC_BF_QUAD_114_DIR : in std_logic;
760  CLK_320MHz64_LHC_BF_QUAD_114_CMP : in std_logic;
761  --clk40 : in std_logic;
762  RXN_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
763  RXP_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0)
764 
765 
766  );
767 
768 
769 end CMX_top_Base;
770 
771 architecture Behavioral of CMX_top_Base is
772 
773  attribute keep : string; -- keep signals in synthesis
774  attribute IOB : string;
775 
776 
777  ------------------------------------------------------------------------------
778  -- VME interface component used in BSPT FPGA (Ian's vme_interface)
779  ------------------------------------------------------------------------------
780  component CMX_BASE_VME_BSPT is
781  port (
782  clk40 : IN std_logic; -- 40MHz Clk
783  geoadd_0 : IN std_logic; -- GeoAddr0
784  n_ds0_int : IN std_logic; -- DS strobe
785  n_write : IN std_logic; -- VME Write
786  vme_address : IN std_logic_vector (23 DOWNTO 1); -- Address bus
787  board_ds : OUT std_logic; -- Board ds
788  brdsel_n : OUT std_logic -- Board select
789  );
790  end component;
791  -- signals for CMX_BASE_VME_INTERFACE component
792  signal ds: std_logic; -- board_ds output from VME (Ian model)
793  signal ncs: std_logic; -- brdsel_n output from VME (Ian model)
794 
795  signal vme_address : std_logic_vector(23 downto 1);
796 
797  component vme_outreg
798  generic (
799  ia_vme : integer;
800  width : integer);
801  port (
802  clk : in std_logic;
803  addr_vme : in std_logic_vector (15 downto 0);
804  ncs : in std_logic;
805  rd_nwr : in std_logic;
806  ds : in std_logic;
807  data_to_vme : in std_logic_vector (width-1 downto 0);
808  read_detect : out std_logic;
809  data_vme : out std_logic_vector (15 downto 0));
810  end component;
811 
812  signal read_detect_outreg_test : std_logic;
813  signal data_to_vme_outreg_test : std_logic_vector (15 downto 0);
814 
815 
816  component vme_inreg
817  generic (
818  ia_vme : integer;
819  width : integer);
820  port (
821  clk : in std_logic;
822  ncs : in std_logic;
823  rd_nwr : in std_logic;
824  ds : in std_logic;
825  data_from_vme : out std_logic_vector (width-1 downto 0);
826  data_to_vme : in std_logic_vector (width-1 downto 0);
827  addr_vme : in std_logic_vector (15 downto 0);
828  read_detect : out std_logic;
829  write_detect : out std_logic;
830  data_vme : inout std_logic_vector (15 downto 0));
831  end component;
832 
833  component vme_inreg_async is
834  generic (
835  ia_vme : integer;
836  width : integer);
837  port (
838  ncs : in std_logic;
839  rd_nwr : in std_logic;
840  ds : in std_logic;
841  addr_vme : in std_logic_vector (15 downto 0);
842  data_vme : inout std_logic_vector (15 downto 0);
843  data_from_vme : out std_logic_vector (width-1 downto 0);
844  data_to_vme : in std_logic_vector (width-1 downto 0));
845  end component vme_inreg_async;
846 
847 
848  component vme_local_switch is
849  port (
850  data_vme_up : out std_logic_vector (15 downto 0);
851  data_vme_from_below : in arr_16;
852  bus_drive_up : out std_logic;
853  bus_drive_from_below : in std_logic_vector);
854  end component vme_local_switch;
855 
856  component vme_main_hub is
857  port (
858  data_vme : inout std_logic_vector(15 downto 0);
859  data_vme_from_below : in std_logic_vector (15 downto 0);
860  bus_drive_from_below : in std_logic;
861  data_vme_going_below : out std_logic_vector(15 downto 0));
862  end component vme_main_hub;
863 
864  signal data_vme_from_below_top : arr_16(1762 downto 0);
865  signal bus_drive_from_below_top : std_logic_vector(1762 downto 0);
866  signal bus_drive_up_top : std_logic;
867  signal data_vme_up_top : std_logic_vector(15 downto 0);
868  signal data_vme_going_below : std_logic_vector(15 downto 0);
869 
870  component vme_inreg_notri_async is
871  generic (
872  ia_vme : integer;
873  width : integer);
874  port (
875  ncs : in std_logic;
876  rd_nwr : in std_logic;
877  ds : in std_logic;
878  addr_vme : in std_logic_vector (15 downto 0);
879  data_vme_in : in std_logic_vector (15 downto 0);
880  data_vme_out : out std_logic_vector (15 downto 0);
881  bus_drive : out std_logic;
882  data_from_vme : out std_logic_vector (width-1 downto 0);
883  data_to_vme : in std_logic_vector (width-1 downto 0));
884  end component vme_inreg_notri_async;
885 
886  component vme_outreg_notri_async is
887  generic (
888  ia_vme : integer;
889  width : integer);
890  port (
891  ncs : in std_logic;
892  rd_nwr : in std_logic;
893  ds : in std_logic;
894  addr_vme : in std_logic_vector (15 downto 0);
895  data_vme : out std_logic_vector (15 downto 0);
896  bus_drive : out std_logic;
897  data_to_vme : in std_logic_vector (width-1 downto 0));
898  end component vme_outreg_notri_async;
899 
900  component vme_inreg_notri is
901  generic (
902  ia_vme : integer;
903  width : integer);
904  port (
905  clk : in std_logic;
906  ncs : in std_logic;
907  rd_nwr : in std_logic;
908  ds : in std_logic;
909  addr_vme : in std_logic_vector (15 downto 0);
910  data_vme_in : in std_logic_vector (15 downto 0);
911  data_vme_out : out std_logic_vector (15 downto 0);
912  bus_drive : out std_logic;
913  data_from_vme : out std_logic_vector (width-1 downto 0);
914  data_to_vme : in std_logic_vector (width-1 downto 0);
915  read_detect : out std_logic;
916  write_detect : out std_logic);
917  end component vme_inreg_notri;
918 
919  component vme_outreg_notri is
920  generic (
921  ia_vme : integer;
922  width : integer);
923  port (
924  clk : in std_logic;
925  ncs : in std_logic;
926  rd_nwr : in std_logic;
927  ds : in std_logic;
928  addr_vme : in std_logic_vector (15 downto 0);
929  data_vme : out std_logic_vector (15 downto 0);
930  bus_drive : out std_logic;
931  data_to_vme : in std_logic_vector (width-1 downto 0);
932  read_detect : out std_logic);
933  end component vme_outreg_notri;
934 
935  signal data_from_vme_test_rw : std_logic_vector (15 downto 0);
936  signal data_to_vme_test_rw : std_logic_vector (15 downto 0);
937  signal read_detect_inreg_test : std_logic;
938  signal write_detect_inreg_test : std_logic;
939  signal test_rw_counter : unsigned(15 downto 0);
940  signal data_to_vme_test_r : std_logic_vector (15 downto 0);
941 
942 
943 
944  signal start_playback, start_playback_r1: std_logic; --r1 is the the
945  --BF_TO_FROM_BSPT_0
946  --registered once
947  -- the first variable is
948  -- yet one more register
949  -- (so synchroniser)
950 
951  component CMX_version is
952  port (
953  clk40 : in std_logic;
954  ncs : in std_logic;
955  rd_nwr : in std_logic;
956  ds : in std_logic;
957  addr_vme : in std_logic_vector (15 downto 0);
958  data_vme_out : out std_logic_vector (15 downto 0);
959  bus_drive : out std_logic);
960  end component CMX_version;
961 
962 
963 
964  component sys_monitor is
965  generic (
966  ADDR_REG_RO_SYSMON_DATA_BLOCK : integer);
967  port (
968  clk : in std_logic;
969  BF_SYSMON_01_P : in STD_LOGIC;
970  BF_SYSMON_01_N : in STD_LOGIC;
971  BF_SYSMON_03_P : in STD_LOGIC;
972  BF_SYSMON_03_N : in STD_LOGIC;
973  BF_SYSMON_04_P : in STD_LOGIC;
974  BF_SYSMON_04_N : in STD_LOGIC;
975  BF_SYSMON_07_P : in STD_LOGIC;
976  BF_SYSMON_07_N : in STD_LOGIC;
977  BF_SYSMON_08_P : in STD_LOGIC;
978  BF_SYSMON_08_N : in STD_LOGIC;
979  BF_SYSMON_09_P : in STD_LOGIC;
980  BF_SYSMON_09_N : in STD_LOGIC;
981  BF_SYSMON_10_P : in STD_LOGIC;
982  BF_SYSMON_10_N : in STD_LOGIC;
983  BF_SYSMON_11_P : in STD_LOGIC;
984  BF_SYSMON_11_N : in STD_LOGIC;
985  BF_SYSMON_12_P : in STD_LOGIC;
986  BF_SYSMON_12_N : in STD_LOGIC;
987  BF_SYSMON_13_P : in STD_LOGIC;
988  BF_SYSMON_13_N : in STD_LOGIC;
989  BF_SYSMON_14_P : in STD_LOGIC;
990  BF_SYSMON_14_N : in STD_LOGIC;
991  BF_SYSMON_15_P : in STD_LOGIC;
992  BF_SYSMON_15_N : in STD_LOGIC;
993  ncs : in std_logic;
994  rd_nwr : in std_logic;
995  ds : in std_logic;
996  addr_vme : in std_logic_vector (15 downto 0);
997  data_vme_in : in std_logic_vector (15 downto 0);
998  data_vme_out : out std_logic_vector (15 downto 0);
999  bus_drive : out std_logic);
1000  end component sys_monitor;
1001 
1002 
1003  component CMX_input_module
1004  port (
1005  P : in mat_var (numactchan-1 downto 0);
1006  buf_clk40 : in std_logic;
1007  buf_clk40_m180o : in std_logic;
1008  buf_clk200 : in std_logic;
1009  pll_locked : in std_logic;
1010  ODATA : out arr_4Xword (numactchan-1 downto 0);
1011  ODATA_first_half : out arr_2Xword(numactchan -1 downto 0);
1012  PAR_ERROR_total : out std_logic;--_vector(numactchan-1 downto 0);
1013  counter_enable_out : out std_logic_vector(numactchan-1 downto 0);
1014  counter_values : out std_logic_vector(numactchan-1 downto 0);
1015  del_register : in del_register_type;
1016  upload_delays : in std_logic;
1017  quiet : in std_logic;
1018  start_playback : in std_logic;
1019  spy_write_inhibit : in std_logic;
1020  ncs : in std_logic;
1021  rd_nwr : in std_logic;
1022  ds : in std_logic;
1023  addr_vme : in std_logic_vector (15 downto 0);
1024  data_vme_in : in std_logic_vector (15 downto 0);
1025  data_vme_out : out std_logic_vector (15 downto 0);
1026  bus_drive : out std_logic
1027  );
1028  end component;
1029 
1030  signal counter_values : std_logic_vector(numactchan-1 downto 0);
1031  signal del_register : del_register_type;
1032  signal upload_delays : std_logic;
1033 
1034  --signal PAR_ERROR: std_logic_vector(numactchan-1 downto 0);
1035 
1036  signal quiet : std_logic;
1037  signal force : std_logic;
1038 
1039  signal data_from_vme_REG_RW_QUIET_FORCE : std_logic_vector(15 downto 0);
1040  signal data_to_vme_REG_RW_QUIET_FORCE : std_logic_vector(15 downto 0);
1041 
1042  signal DATA96 : arr_4Xword (numactchan-1 downto 0); --96 bit data at 40MHz
1043  signal ODATA_first_half : arr_2Xword(numactchan-1 downto 0);
1044 
1045  signal P : mat_var (numactchan-1 downto 0);
1046 
1047  signal BF_DEBUG : std_logic_vector(9 downto 0);
1048 
1049  signal counter_enable_inputmod_sig: std_logic_vector(numactchan-1 downto 0);
1050 
1051 
1052  component CMX_Memory_spy_inhibit is
1053  port (
1054  spy_write_inhibit : out std_logic;
1055  buf_clk40 : in std_logic;
1056  ncs : in std_logic;
1057  rd_nwr : in std_logic;
1058  ds : in std_logic;
1059  addr_vme : in std_logic_vector (15 downto 0);
1060  data_vme_in : in std_logic_vector (15 downto 0);
1061  data_vme_out : out std_logic_vector (15 downto 0);
1062  bus_drive : out std_logic);
1063  end component CMX_Memory_spy_inhibit;
1064 
1065  signal spy_write_inhibit : std_logic;
1066 
1067 
1068  component decoder is
1069  port (
1070  clk40MHz : in std_logic;
1071  clk40MHz_m90o : in std_logic;
1072  clk40MHz_90o : in std_logic;
1073  clk40MHz_m180o : in std_logic;
1074  pll_locked : in std_logic;
1075  datai : in arr_4Xword(max_cps-1 downto 0);
1076  datai_first_half : in arr_2Xword(max_cps-1 downto 0);
1077  Tobs_to_TOPO : out copy_arr_TOB;
1078  overflow : out std_logic_vector(num_copies-1 downto 0);
1079  BCID_in : in std_logic_vector(11 downto 0);
1080  BCID_delayed : out std_logic_vector(11 downto 0);
1081  --tob rate counter contol
1082  counter_inhibit : in std_logic;
1083  counter_reset : in std_logic;
1084  --VME control:
1085  ncs : in std_logic;
1086  rd_nwr : in std_logic;
1087  ds : in std_logic;
1088  addr_vme : in std_logic_vector (15 downto 0);
1089  data_vme_out : out std_logic_vector (15 downto 0);
1090  bus_drive : out std_logic
1091  );
1092  end component decoder;
1093 
1094  signal Tobs_to_TOPO : copy_arr_TOB;
1095  signal overflow : std_logic_vector(num_copies-1 downto 0);
1096 
1097 
1098  signal data_from_vme_REG_RW_JET_THRESHOLD_BLOCK : arr_16(1599 downto 0);
1099  signal data_to_vme_REG_RW_JET_THRESHOLD_BLOCK : arr_16(1599 downto 0);
1100 
1101  component adder_top is
1102  generic (
1103  ADDR_REG_RW_PIPELINE_DELAY_LENGTH : integer;
1104  gen_system : std_logic);
1105  port (
1106  clk : in T_SL; -- clock
1107  thresholds : in arr_16(max_cps*16*4-1 downto 0); -- thresholds
1108  datai : in arr_4Xword(max_cps-1 downto 0); -- input data
1109  din_cbl : in T_SLV150; -- remote input (multiplicty)
1110  din_cbla_ro : in T_SL; -- remote overflow
1111  din_cblb_ro : in T_SL; -- remote overflow
1112  din_cblc_ro : in T_SL; -- remote overflow
1113  dout_lcl : out T_SLV48; -- local multiplicity
1114  dout_lcl_ro : out T_SL; -- local overflow
1115  dout : out T_SLV62; -- global output data (multiplicity), including parity
1116  dout_ro : out T_SL; -- global overflow
1117  dout_cbla_mux0 : out std_logic_vector(33 downto 0); -- cable output data (multiplicity), including parity
1118  dout_cbla_mux1 : out std_logic_vector(33 downto 0); -- cable output data (multiplicity), including parity
1119  --VME control:
1120  ncs : in std_logic;
1121  rd_nwr : in std_logic;
1122  ds : in std_logic;
1123  addr_vme : in std_logic_vector (15 downto 0);
1124  data_vme_in : in std_logic_vector (15 downto 0);
1125  data_vme_out : out std_logic_vector (15 downto 0);
1126  bus_drive : out std_logic;
1127  par_err : in T_SLV2; -- parity error (input module - 0, RTM - 1)
1128  force : in T_SL; -- force
1129  -- counter signals
1130  reset : in T_SL;
1131  inhibit : in T_SL
1132  );
1133  end component;
1134 
1135  signal par_err : T_SLV2;
1136 
1137  component daq_collector is
1138  port (
1139  clk : in std_logic;
1140  datai : in arr_4Xword(max_cps-1 downto 0);
1141  din_cbl : in T_SLV150;
1142  din_cbla_ro : in T_SL;
1143  din_cblb_ro : in T_SL;
1144  din_cblc_ro : in T_SL;
1145  din_lcl : in T_SLV48;
1146  din_lcl_ro : in T_SL;
1147  dout : in T_SLV62;
1148  dout_ro : in T_SL;
1149  data_in_daq : out arr_96(19 downto 0);
1150  BCID_in : in std_logic_vector(11 downto 0);
1151  BCID_delayed : out std_logic_vector(11 downto 0));
1152  end component;
1153 
1154 
1155  signal thresholds : arr_16(16*25*4-1 downto 0); -- thresholds
1156 
1157 
1158 -- signal p_d : nx121_array(numactchan-1 downto 0); --120 bits + parity -
1159 -- --will be connected to
1160 -- --the decoder output
1161 -- --threshold mask 25
1162 -- --threshold times 4
1163 -- --TOBs + 5 bits position/TOB
1164 
1165  signal din_cbl : T_SLV150;
1166  signal din_cbla_ro : T_SL; -- remote overflow
1167  signal din_cblb_ro : T_SL; -- remote overflow
1168  signal din_cblc_ro : T_SL; -- remote overflow
1169  signal dout_lcl : T_SLV48; -- local multiplicity
1170  signal dout_lcl_ro : T_SL; -- local overflow
1171  signal dout : T_SLV62; -- data to CTP from adder
1172  signal dout_ro : T_SL; -- global overflow
1173 
1174  component CMX_cable_clocked_80Mbps_output_module
1175  generic (
1176  numbits_in_cable_connector : integer);
1177  port (
1178  data : in std_logic_vector((numbits_in_cable_connector*2)-1 downto 0);
1179  ddr_data_out : out std_logic_vector(numbits_in_cable_connector downto 0);
1180  buf_clk40 : in std_logic;
1181  buf_clk40_center : in std_logic;
1182  buf_clk200 : in std_logic;
1183  pll_locked : in std_logic;
1184  del_array : in cable_del_array_type(numbits_in_cable_connector downto 0);
1185  upload_delays : in std_logic);
1186  end component;
1187 
1188 
1189  signal sdr_data_out_CTP1 : std_logic_vector(31 downto 0);
1190  signal sdr_data_out_CTP2 : std_logic_vector(31 downto 0);
1191  --signal sdr_data_out : std_logic_vector(31 downto 0);
1192 
1193 
1194  signal ddr_data_in_RTM1 : std_logic_vector(numbits_in_RTM_connector downto 0);
1195  signal ddr_data_in_RTM2 : std_logic_vector(numbits_in_RTM_connector downto 0);
1196  signal ddr_data_in_RTM3 : std_logic_vector(numbits_in_RTM_connector downto 0);
1197  signal sig_arr_RTM: arr_RTM(num_RTM_cables-1 downto 0);
1198  signal data_from_RTM : std_logic_vector(numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1199 
1200  component CMX_system_cable_input_module is
1201  port (
1202  data : out std_logic_vector(numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1203  parity_error_total : out std_logic_vector(num_RTM_cables-1 downto 0);
1204  ddr_data_in : in arr_RTM(num_RTM_cables-1 downto 0);
1205  buf_clk40 : in std_logic;
1206  buf_clk40_ds2 : in std_logic;
1207  pll_locked : in std_logic;
1208  pll_locked_ds2 : in std_logic;
1209  start_playback : in std_logic;
1210  spy_write_inhibit : in std_logic;
1211  ncs : in std_logic;
1212  rd_nwr : in std_logic;
1213  ds : in std_logic;
1214  addr_vme : in std_logic_vector (15 downto 0);
1215  data_vme_in : in std_logic_vector (15 downto 0);
1216  data_vme_out : out std_logic_vector (15 downto 0);
1217  bus_drive : out std_logic);
1218  end component CMX_system_cable_input_module;
1219 
1220  component CMX_cable_clocked_80Mbps_input_module
1221  generic (
1222  numbits_in_cable_connector : integer);
1223  port (
1224  data : out std_logic_vector((numbits_in_cable_connector*2)-1 downto 0);
1225  parity : out std_logic;
1226  forwarded_clock : out std_logic;
1227  ddr_data_in : in std_logic_vector(numbits_in_cable_connector downto 0);
1228  buf_clk40 : in std_logic;
1229  buf_clk200 : in std_logic;
1230  pll_locked : in std_logic;
1231  del_array : in cable_del_array_type(numbits_in_cable_connector downto 0);
1232  upload_delays : in std_logic);
1233  end component;
1234 
1235  --signal forwarded_clock_CTP2 : std_logic;
1236  --signal data_CTP2 : std_logic_vector((numbits_in_CTP_connector*2)-1 downto 0);
1237  --signal parity_CTP2 : std_logic;
1238  --signal ddr_data_in_CTP2 : std_logic_vector(numbits_in_CTP_connector downto 0);
1239  --
1240  --signal forwarded_clock_RTM3 : std_logic;
1241  --signal data_RTM3 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1242  --signal parity_RTM3 : std_logic;
1243  --signal ddr_data_in_RTM3 : std_logic_vector(numbits_in_RTM_connector downto 0);
1244 
1245  component BCID_counter
1246  port (
1247  reset : in std_logic;
1248  clk_40 : in std_logic;
1249  BCID_out : out std_logic_vector(11 downto 0);
1250  --VME control:
1251 
1252  ncs : in std_logic; --ports forwarded to the vme register instances
1253  rd_nwr : in std_logic;
1254  ds : in std_logic;
1255  addr_vme : in std_logic_vector (15 downto 0);
1256  data_vme_in : in std_logic_vector (15 downto 0);
1257  data_vme_out : out std_logic_vector (15 downto 0);
1258  bus_drive : out std_logic
1259  );
1260  end component;
1261  signal BCID_counter_sig : std_logic_vector(11 downto 0);
1262  signal BCID_delayed_decoder : std_logic_vector(11 downto 0);
1263  signal BCID_delayed_daq : std_logic_vector(11 downto 0);
1264 
1265 
1266 
1267  --component PRNG_LFSR_BIG is
1268  -- port (
1269  -- clk : in std_logic;
1270  -- rst : in std_logic;
1271  -- DATA_PRN : out std_logic_vector(63 downto 0));
1272  --end component PRNG_LFSR_BIG;
1273  --signal DATA_PRN: arr_64((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1274 
1275  component Topo_Data_TX is
1276  port (
1277  MGTREFCLK_PAD_N_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1278  MGTREFCLK_PAD_P_IN : in std_logic_vector(num_GTX_groups-1 downto 0);
1279  GTXTXRESET_IN : in std_logic;
1280  GTXRXRESET_IN : in std_logic;
1281  GTX_TX_READY_OUT : out std_logic;
1282  GTX_RX_READY_OUT : out std_logic;
1283  RXN_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1284  RXP_IN : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1285  TXN_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1286  TXP_OUT : out std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1287  clk40 : in std_logic;
1288  clk320 : in std_logic;
1289  pll_locked : in std_logic;
1290  send_align : in std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1291  BCID : in std_logic_vector(11 downto 0);
1292  indata : in std_logic_vector(TX_indata_length-1 downto 0);
1293  ext_trigger : in std_logic;
1294  ncs : in std_logic;
1295  rd_nwr : in std_logic;
1296  ds : in std_logic;
1297  addr_vme : in std_logic_vector (15 downto 0);
1298  data_vme_in : in std_logic_vector (15 downto 0);
1299  data_vme_out : out std_logic_vector (15 downto 0);
1300  bus_drive : out std_logic);
1301  end component Topo_Data_TX;
1302 
1303  component CMX_CP_Topo_Encoder is
1304  port (
1305  Tobs_to_TOPO : in copy_arr_TOB;
1306  overflow : in std_logic_vector(num_copies-1 downto 0);
1307  send_align_out : out std_logic_vector(num_GTX_groups*num_GTX_per_group - 1 downto 0);
1308  Data_out : out std_logic_vector(TX_indata_length - 1 downto 0));
1309  end component CMX_CP_Topo_Encoder;
1310 
1311  signal TXN_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1312  signal TXP_OUT : std_logic_vector((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1313 
1314  signal MGTREFCLK_PAD_N_IN : std_logic_vector(num_GTX_groups-1 downto 0);
1315  signal MGTREFCLK_PAD_P_IN : std_logic_vector(num_GTX_groups-1 downto 0);
1316 
1317  signal GTX_RX_READY_OUT : std_logic;
1318  signal GTX_TX_READY_OUT : std_logic;
1319 
1320 
1321  signal GTXTXRESET_IN : std_logic;
1322  signal GTXRXRESET_IN : std_logic;
1323 
1324  signal send_align : std_logic_vector(23 downto 0);
1325 
1326  signal indata_Topo_TX : std_logic_vector(TX_indata_length-1 downto 0);
1327 
1328  signal data_to_vme_REG_RW_TOPOTR_GTX_RESET : std_logic_vector(15 downto 0);
1329  signal data_from_vme_REG_RW_TOPOTR_GTX_RESET : std_logic_vector(15 downto 0);
1330 
1331  signal data_to_vme_REG_RO_TOPOTR_GTX_STATUS : std_logic_vector(15 downto 0);
1332 
1333  signal data_from_vme_REG_RW_DAQ_ROI_RESET : std_logic_vector(15 downto 0);
1334  signal data_to_vme_REG_RW_DAQ_ROI_RESET : std_logic_vector(15 downto 0);
1335 
1336  signal data_to_vme_REG_RO_DAQ_ROI_STATUS : std_logic_vector(15 downto 0);
1337 
1338  signal data_from_vme_REG_RW_DAQ_ROI_GTX_RESET: std_logic_vector(15 downto 0);
1339  signal data_to_vme_REG_RW_DAQ_ROI_GTX_RESET: std_logic_vector(15 downto 0);
1340  signal gtx_reset_SFP_DAQ, gtx_reset_SFP_ROI : std_logic;
1341 
1342  signal BUF_TTC_L1_ACCEPT_r: std_logic;
1343  signal l1a_synced: std_logic;
1344 
1345 
1346  signal bc_reset_synced : std_logic;
1347  signal BUF_TTC_BNCH_CNT_RES_r : std_logic;
1348 
1349  component CMX_rate_counter_inhibit is
1350  port (
1351  counter_inhibit : out std_logic;
1352  counter_reset : out std_logic;
1353  buf_clk40 : in std_logic;
1354  ncs : in std_logic;
1355  rd_nwr : in std_logic;
1356  ds : in std_logic;
1357  addr_vme : in std_logic_vector (15 downto 0);
1358  data_vme_in : in std_logic_vector (15 downto 0);
1359  data_vme_out : out std_logic_vector (15 downto 0);
1360  bus_drive : out std_logic);
1361  end component CMX_rate_counter_inhibit;
1362 
1363  signal counter_inhibit : std_logic;
1364  signal counter_reset : std_logic;
1365 
1366  --
1367  --
1368  --component chipscope_ila_CMX_top_inputmodclk
1369  -- port (
1370  -- CONTROL : inout std_logic_vector(35 downto 0);
1371  -- CLK : in std_logic;
1372  -- DATA : in std_logic_vector(2375 downto 0);
1373  -- TRIG0 : in std_logic_vector(35 downto 0));
1374  --end component;
1375  --
1376  --signal DATA_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(2375 downto 0);
1377  --signal TRIG0_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(35 downto 0);
1378  ----signal TRIG_forward_inputmodclk_outputmodclk : std_logic_vector(0 downto 0);
1379 
1380 
1381  --component chipscope_ila_IDELAY
1382  -- port (
1383  -- CONTROL : inout std_logic_vector(35 downto 0);
1384  -- CLK : in std_logic;
1385  -- DATA : in std_logic_vector(2000 downto 0);
1386  -- TRIG0 : in std_logic_vector(0 to 0));
1387  --end component;
1388 
1389  --signal DATA_chipscope_ila_IDELAY : std_logic_vector(2000 downto 0);
1390 
1391 
1392  --component chipscope_ila_CTP2
1393  -- port (
1394  -- CONTROL : inout std_logic_vector(35 downto 0);
1395  -- CLK : in std_logic;
1396  -- DATA : in std_logic_vector(64 downto 0);
1397  -- TRIG0 : in std_logic_vector(0 to 0));
1398  --end component;
1399  --
1400  --component chipscope_ila_RTM
1401  -- port (
1402  -- CONTROL : inout std_logic_vector(35 downto 0);
1403  -- CLK : in std_logic;
1404  -- DATA : in std_logic_vector(52 downto 0);
1405  -- TRIG0 : in std_logic_vector(0 to 0));
1406  --end component;
1407 
1408  --component chipscope_ila_LVDS_TX_CTP_RTM
1409  -- port (
1410  -- CONTROL : inout std_logic_vector(35 downto 0);
1411  -- CLK : in std_logic;
1412  -- DATA : in std_logic_vector(117 downto 0);
1413  -- TRIG0 : in std_logic_vector(1 downto 0));
1414  --end component;
1415 
1416 
1417  component CMX_clock_manager is
1418  port (
1419  I_DS1 : in std_logic;
1420  IB_DS1 : in std_logic;
1421  buf_clk40 : out std_logic;
1422  buf_clk40_90o : out std_logic;
1423  buf_clk40_m180o : out std_logic;
1424  buf_clk40_m90o : out std_logic;
1425  buf_clk320 : out std_logic;
1426  buf_clk160 : out std_logic;
1427  buf_clk200 : out std_logic;
1428  pll_locked : out std_logic;
1429  I_DS2 : in std_logic;
1430  IB_DS2 : in std_logic;
1431  buf_clk40_ds2 : out std_logic;
1432  pll_locked_ds2 : out std_logic;
1433  ncs : in std_logic;
1434  rd_nwr : in std_logic;
1435  ds : in std_logic;
1436  addr_vme : in std_logic_vector (15 downto 0);
1437  data_vme_in : in std_logic_vector (15 downto 0);
1438  data_vme_out : out std_logic_vector (15 downto 0);
1439  bus_drive : out std_logic);
1440  end component CMX_clock_manager;
1441 
1442 
1443  signal buf_clk40 : std_logic;
1444  signal buf_clk40_m180o : std_logic;
1445  signal buf_clk40_90o : std_logic;
1446  signal buf_clk40_m90o : std_logic;
1447 
1448  signal buf_clk320 : std_logic;
1449  signal buf_clk160 : std_logic;
1450  signal buf_clk200 : std_logic;
1451  signal pll_locked : std_logic;
1452 
1453  signal buf_clk40_ds2 : std_logic;
1454  signal pll_locked_ds2 : std_logic;
1455 
1456  component CMX_delay_generator
1457  generic (
1458  start_address : integer);
1459  port (
1460  clk40 : in std_logic;
1461  ncs : in std_logic;
1462  rd_nwr : in std_logic;
1463  ds : in std_logic;
1464  addr_vme : in std_logic_vector (15 downto 0);
1465  data_vme_in : in std_logic_vector (15 downto 0);
1466  data_vme_out : out std_logic_vector (15 downto 0);
1467  bus_drive : out std_logic;
1468  del_register : out del_register_type;
1469  upload_delays : out std_logic);
1470  end component;
1471 
1472  component CMX_CTP_output_module is
1473  port (
1474  data : in std_logic_vector((numbits_in_CTP_connector*2)-1 downto 0);
1475  sdr_data_out : out arr_CTP;
1476  buf_clk40 : in std_logic;
1477  buf_clk40_center : in std_logic;
1478  buf_clk200 : in std_logic;
1479  pll_locked : in std_logic;
1480  start_playback : in std_logic;
1481  spy_write_inhibit : in std_logic;
1482  ncs : in std_logic;
1483  rd_nwr : in std_logic;
1484  ds : in std_logic;
1485  addr_vme : in std_logic_vector (15 downto 0);
1486  data_vme_in : in std_logic_vector (15 downto 0);
1487  data_vme_out : out std_logic_vector (15 downto 0);
1488  bus_drive : out std_logic);
1489  end component CMX_CTP_output_module;
1490 
1491  signal sdr_data_CTP: arr_CTP;
1492 
1493  component CMX_CTP_out_tester
1494  port (
1495  sdr_data_out : out std_logic_vector(31 downto 0);
1496  buf_clk40 : in std_logic;
1497  pll_locked : in std_logic;
1498  ncs : in std_logic;
1499  rd_nwr : in std_logic;
1500  ds : in std_logic;
1501  addr_vme : in std_logic_vector (15 downto 0);
1502  data_vme : inout std_logic_vector (15 downto 0));
1503  end component;
1504 
1505 
1506 
1507  component SFP_Data_TXRX
1508  generic (
1509  direction : std_logic;
1510  clock_source : std_logic);
1511  port (
1512  MGTREFCLK : in std_logic;
1513  gtx_reset : in std_logic;
1514  local_pll_lock_out: out std_logic;
1515  GTX_TX_READY_OUT : out std_logic;
1516  GTX_RX_READY_OUT : out std_logic;
1517  PLLLKDET_diag : out std_logic;
1518  local_gtx_reset_diag : out std_logic;
1519  local_mmcm_reset_diag : out std_logic;
1520  GTXTEST_diag : out std_logic;
1521  RXN_IN : in std_logic;
1522  RXP_IN : in std_logic;
1523  TXN_OUT : out std_logic;
1524  TXP_OUT : out std_logic;
1525  clk40_out : out std_logic;
1526  clk120_out : out std_logic;
1527  clk40_in : in std_logic;
1528  clk120_in : in std_logic;
1529  indata : in std_logic_vector(7 downto 0);
1530  odata : out std_logic_vector(7 downto 0);
1531  TXPREEMPHASIS_IN : in std_logic_vector(3 downto 0);
1532  TXPOSTEMPHASIS_IN : in std_logic_vector(4 downto 0);
1533  TXDIFFCTRL_IN : in std_logic_vector(3 downto 0);
1534  RXEQMIX_IN : in std_logic_vector(2 downto 0);
1535  DFECLKDLYADJ : in std_logic_vector(5 downto 0);
1536  DFECLKDLYADJMON : out std_logic_vector(5 downto 0);
1537  DFEDLYOVRD : in std_logic;
1538  DFEEYEDACMON : out std_logic_vector(4 downto 0);
1539  DFESENSCAL : out std_logic_vector(2 downto 0);
1540  DFETAP1 : in std_logic_vector(4 downto 0);
1541  DFETAP1MONITOR : out std_logic_vector(4 downto 0);
1542  DFETAP2 : in std_logic_vector(4 downto 0);
1543  DFETAP2MONITOR : out std_logic_vector(4 downto 0);
1544  DFETAP3 : in std_logic_vector(3 downto 0);
1545  DFETAP3MONITOR : out std_logic_vector(3 downto 0);
1546  DFETAP4 : in std_logic_vector(3 downto 0);
1547  DFETAP4MONITOR : out std_logic_vector(3 downto 0);
1548  DFETAPOVRD : in std_logic);
1549  end component;
1550 
1551  signal MGTREFCLK_Q118 : std_logic;
1552 
1553  signal GTXTXRESET_IN_TX_SFP_DAQ : std_logic;
1554  signal GTXRXRESET_IN_TX_SFP_DAQ : std_logic;
1555  signal local_pll_lock_out_SFP_DAQ : std_logic;
1556  signal GTX_TX_READY_OUT_TX_SFP_DAQ : std_logic;
1557  signal GTX_RX_READY_OUT_TX_SFP_DAQ : std_logic;
1558  signal PLLLKDET_diag_TX_SFP_DAQ : std_logic;
1559  signal local_gtx_reset_diag_TX_SFP_DAQ : std_logic;
1560  signal local_mmcm_reset_diag_TX_SFP_DAQ : std_logic;
1561  signal GTXTEST_diag_TX_SFP_DAQ : std_logic;
1562  signal RXN_IN_TX_SFP_DAQ : std_logic;
1563  signal RXP_IN_TX_SFP_DAQ : std_logic;
1564  signal TXN_OUT_TX_SFP_DAQ : std_logic;
1565  signal TXP_OUT_TX_SFP_DAQ : std_logic;
1566  signal clk40_out_TX_SFP_DAQ : std_logic;
1567  signal clk120_out_TX_SFP_DAQ : std_logic;
1568  signal clk40_in_TX_SFP_DAQ : std_logic;
1569  signal clk120_in_TX_SFP_DAQ : std_logic;
1570  signal indata_TX_SFP_DAQ : std_logic_vector(7 downto 0);
1571  signal odata_TX_SFP_DAQ : std_logic_vector(7 downto 0);
1572  signal TXPREEMPHASIS_IN_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1573  signal TXPOSTEMPHASIS_IN_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1574  signal TXDIFFCTRL_IN_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1575  signal RXEQMIX_IN_TX_SFP_DAQ : std_logic_vector(2 downto 0);
1576  signal DFECLKDLYADJ_TX_SFP_DAQ : std_logic_vector(5 downto 0);
1577  signal DFECLKDLYADJMON_TX_SFP_DAQ : std_logic_vector(5 downto 0);
1578  signal DFEDLYOVRD_TX_SFP_DAQ : std_logic;
1579  signal DFEEYEDACMON_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1580  signal DFESENSCAL_TX_SFP_DAQ : std_logic_vector(2 downto 0);
1581  signal DFETAP1_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1582  signal DFETAP1MONITOR_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1583  signal DFETAP2_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1584  signal DFETAP2MONITOR_TX_SFP_DAQ : std_logic_vector(4 downto 0);
1585  signal DFETAP3_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1586  signal DFETAP3MONITOR_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1587  signal DFETAP4_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1588  signal DFETAP4MONITOR_TX_SFP_DAQ : std_logic_vector(3 downto 0);
1589  signal DFETAPOVRD_TX_SFP_DAQ : std_logic;
1590 
1591  signal GTXTXRESET_IN_TX_SFP_ROI : std_logic;
1592  signal GTXRXRESET_IN_TX_SFP_ROI : std_logic;
1593  signal local_pll_lock_out_SFP_ROI : std_logic;
1594  signal GTX_TX_READY_OUT_TX_SFP_ROI : std_logic;
1595  signal GTX_RX_READY_OUT_TX_SFP_ROI : std_logic;
1596  signal PLLLKDET_diag_TX_SFP_ROI : std_logic;
1597  signal local_gtx_reset_diag_TX_SFP_ROI : std_logic;
1598  signal local_mmcm_reset_diag_TX_SFP_ROI : std_logic;
1599  signal GTXTEST_diag_TX_SFP_ROI : std_logic;
1600  signal RXN_IN_TX_SFP_ROI : std_logic;
1601  signal RXP_IN_TX_SFP_ROI : std_logic;
1602  signal TXN_OUT_TX_SFP_ROI : std_logic;
1603  signal TXP_OUT_TX_SFP_ROI : std_logic;
1604  signal clk40_out_TX_SFP_ROI : std_logic;
1605  signal clk120_out_TX_SFP_ROI : std_logic;
1606  signal clk40_in_TX_SFP_ROI : std_logic;
1607  signal clk120_in_TX_SFP_ROI : std_logic;
1608  signal indata_TX_SFP_ROI : std_logic_vector(7 downto 0);
1609  signal odata_TX_SFP_ROI : std_logic_vector(7 downto 0);
1610  signal TXPREEMPHASIS_IN_TX_SFP_ROI : std_logic_vector(3 downto 0);
1611  signal TXPOSTEMPHASIS_IN_TX_SFP_ROI : std_logic_vector(4 downto 0);
1612  signal TXDIFFCTRL_IN_TX_SFP_ROI : std_logic_vector(3 downto 0);
1613  signal RXEQMIX_IN_TX_SFP_ROI : std_logic_vector(2 downto 0);
1614  signal DFECLKDLYADJ_TX_SFP_ROI : std_logic_vector(5 downto 0);
1615  signal DFECLKDLYADJMON_TX_SFP_ROI : std_logic_vector(5 downto 0);
1616  signal DFEDLYOVRD_TX_SFP_ROI : std_logic;
1617  signal DFEEYEDACMON_TX_SFP_ROI : std_logic_vector(4 downto 0);
1618  signal DFESENSCAL_TX_SFP_ROI : std_logic_vector(2 downto 0);
1619  signal DFETAP1_TX_SFP_ROI : std_logic_vector(4 downto 0);
1620  signal DFETAP1MONITOR_TX_SFP_ROI : std_logic_vector(4 downto 0);
1621  signal DFETAP2_TX_SFP_ROI : std_logic_vector(4 downto 0);
1622  signal DFETAP2MONITOR_TX_SFP_ROI : std_logic_vector(4 downto 0);
1623  signal DFETAP3_TX_SFP_ROI : std_logic_vector(3 downto 0);
1624  signal DFETAP3MONITOR_TX_SFP_ROI : std_logic_vector(3 downto 0);
1625  signal DFETAP4_TX_SFP_ROI : std_logic_vector(3 downto 0);
1626  signal DFETAP4MONITOR_TX_SFP_ROI : std_logic_vector(3 downto 0);
1627  signal DFETAPOVRD_TX_SFP_ROI : std_logic;
1628 
1629 
1630 -- glink emulator
1631 
1632  component glink_interface
1633  port (
1634  CLK_40MHz : in std_logic;
1635  CLK_120MHz : in std_logic;
1636  RST : in std_logic;
1637  DAQ_IN : in std_logic_vector (19 DOWNTO 0);
1638  ROI_IN : in std_logic_vector (19 DOWNTO 0);
1639  DAQ_DAV : in std_logic;
1640  ROI_DAV : in std_logic;
1641  DAQ_BYTE : OUT std_logic_vector (7 downto 0);
1642  ROI_BYTE : OUT std_logic_vector (7 downto 0);
1643  DAQ_ENCODED_DIAG : OUT std_logic_vector (23 downto 0);
1644  daq_byte_out : out std_logic_vector (1 downto 0);
1645  byte_pos_out : OUT std_logic_vector (5 downto 0);
1646  word_sel_out : OUT std_logic_vector(1 downto 0);
1647  readout_rst_out : OUT std_logic
1648  );
1649  end component;
1650 
1651  -- Glink emulator signals
1652 
1653  signal daq_in : std_logic_vector (19 DOWNTO 0);
1654  signal roi_in : std_logic_vector (19 DOWNTO 0);
1655  signal daq_dav : std_logic;
1656  signal roi_dav : std_logic;
1657  signal daq_byte : std_logic_vector (7 downto 0);
1658  signal roi_byte : std_logic_vector (7 downto 0);
1659  signal reset_daq : std_logic;
1660  signal daq_encoded_diag : std_logic_vector (23 downto 0);
1661  signal daq_byte_out : std_logic_vector (1 downto 0);
1662 
1663  signal byte_pos_out : std_logic_vector (5 downto 0);
1664  signal word_sel_out : std_logic_vector(1 downto 0);
1665  signal readout_rst_out : std_logic;
1666 
1667  --component chipscope_icon_u2_c3
1668  -- port (
1669  -- CONTROL0 : inout std_logic_vector(35 downto 0);
1670  -- CONTROL1 : inout std_logic_vector(35 downto 0);
1671  -- CONTROL2 : inout std_logic_vector(35 downto 0)
1672  -- );
1673  --end component;
1674  --
1675  --signal CONTROL0 : std_logic_vector(35 downto 0);
1676  --signal CONTROL1 : std_logic_vector(35 downto 0);
1677  --signal CONTROL2 : std_logic_vector(35 downto 0);
1678  --
1679  --signal data_ila_daq : std_logic_vector (53 downto 0);
1680  --signal trig_ila_daq : std_logic_vector (33 downto 0);
1681  --
1682  --signal data_ila_encoder : std_logic_vector (20 downto 0);
1683  --signal trig_ila_encoder : std_logic_vector (11 downto 0);
1684  --
1685  --signal data_ila_gtx_start : std_logic_vector (12 downto 0);
1686  --signal trig_ila_gtx_start : std_logic_vector (2 downto 0);
1687  --
1688  --
1689  ----signal data_ila_1 : std_logic_vector (16 downto 0);
1690  --
1691  --component glink_chipscope_analyzer
1692  -- port (
1693  -- CONTROL: inout std_logic_vector(35 downto 0);
1694  -- CLK: in std_logic;
1695  -- DATA: in std_logic_vector(53 downto 0);
1696  -- TRIG0: in std_logic_vector(33 downto 0));
1697  --end component;
1698  --
1699  --component glink_chipscope_analyzer_encoder
1700  -- port (
1701  -- CONTROL: inout std_logic_vector(35 downto 0);
1702  -- CLK: in std_logic;
1703  -- DATA: in std_logic_vector(20 downto 0);
1704  -- TRIG0: in std_logic_vector(11 downto 0));
1705  --end component;
1706  --
1707  --component glink_chipscope_analyzer_gtx_start is
1708  -- port (
1709  -- CONTROL : inout std_logic_vector(35 downto 0);
1710  -- CLK : in std_logic;
1711  -- DATA : in std_logic_vector(10 downto 0);
1712  -- TRIG0 : in std_logic_vector(0 to 0));
1713  --end component glink_chipscope_analyzer_gtx_start;
1714 
1715 
1716 
1717  component daq_glink
1718  port (
1719  data_in : in arr_96(19 downto 0);
1720  bc_counter : in unsigned(11 downto 0);
1721  l1a : in std_logic;
1722  data_out : out std_logic_vector(19 downto 0);
1723  dav : out std_logic;
1724  clk4000 : in std_logic;
1725  clk4008 : in std_logic;
1726  reset : in std_logic;
1727  RAM_global_offset : in unsigned(7 downto 0);
1728  RAM_rel_offsets : in arr_ctr_8bit(18 downto 0);
1729  nslices : in unsigned(7 downto 0));
1730  end component;
1731 
1732  signal RAM_global_offset : unsigned(7 downto 0);
1733  signal RAM_rel_offsets : arr_ctr_8bit(18 downto 0);
1734  signal nslices : unsigned(7 downto 0);
1735 
1736  signal data_in_daq: arr_96(19 downto 0);
1737 
1738  --control of daq delays
1739  signal data_from_vme_REG_RW_DAQ_SLICE: std_logic_vector(15 downto 0);
1740  signal data_to_vme_REG_RW_DAQ_SLICE: std_logic_vector(15 downto 0);
1741  signal data_from_vme_REG_RW_DAQ_RAM_OFFSET: std_logic_vector(15 downto 0);
1742  signal data_to_vme_REG_RW_DAQ_RAM_OFFSET: std_logic_vector(15 downto 0);
1743 
1744  signal data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1745  signal data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1746 
1747 
1748  attribute keep of start_playback_r1, BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r, send_align, ODATA_first_half : signal is "TRUE";
1749  attribute IOB of BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r : signal is "FORCE";
1750 
1751  --attribute IOB of BF_DOUT_CTP_00 : signal is "TRUE";
1752  --attribute IOB of BF_DOUT_CTP_01 : signal is "TRUE";
1753  --attribute IOB of BF_DOUT_CTP_02 : signal is "TRUE";
1754  --attribute IOB of BF_DOUT_CTP_03 : signal is "TRUE";
1755  --attribute IOB of BF_DOUT_CTP_04 : signal is "TRUE";
1756  --attribute IOB of BF_DOUT_CTP_05 : signal is "TRUE";
1757  --attribute IOB of BF_DOUT_CTP_06 : signal is "TRUE";
1758  --attribute IOB of BF_DOUT_CTP_07 : signal is "TRUE";
1759  --attribute IOB of BF_DOUT_CTP_08 : signal is "TRUE";
1760  --attribute IOB of BF_DOUT_CTP_09 : signal is "TRUE";
1761  --attribute IOB of BF_DOUT_CTP_10 : signal is "TRUE";
1762  --attribute IOB of BF_DOUT_CTP_11 : signal is "TRUE";
1763  --attribute IOB of BF_DOUT_CTP_12 : signal is "TRUE";
1764  --attribute IOB of BF_DOUT_CTP_13 : signal is "TRUE";
1765  --attribute IOB of BF_DOUT_CTP_14 : signal is "TRUE";
1766  --attribute IOB of BF_DOUT_CTP_15 : signal is "TRUE";
1767  --attribute IOB of BF_DOUT_CTP_16 : signal is "TRUE";
1768  --attribute IOB of BF_DOUT_CTP_17 : signal is "TRUE";
1769  --attribute IOB of BF_DOUT_CTP_18 : signal is "TRUE";
1770  --attribute IOB of BF_DOUT_CTP_19 : signal is "TRUE";
1771  --attribute IOB of BF_DOUT_CTP_20 : signal is "TRUE";
1772  --attribute IOB of BF_DOUT_CTP_21 : signal is "TRUE";
1773  --attribute IOB of BF_DOUT_CTP_22 : signal is "TRUE";
1774  --attribute IOB of BF_DOUT_CTP_23 : signal is "TRUE";
1775  --attribute IOB of BF_DOUT_CTP_24 : signal is "TRUE";
1776  --attribute IOB of BF_DOUT_CTP_25 : signal is "TRUE";
1777  --attribute IOB of BF_DOUT_CTP_26 : signal is "TRUE";
1778  --attribute IOB of BF_DOUT_CTP_27 : signal is "TRUE";
1779  --attribute IOB of BF_DOUT_CTP_28 : signal is "TRUE";
1780  --attribute IOB of BF_DOUT_CTP_29 : signal is "TRUE";
1781  --attribute IOB of BF_DOUT_CTP_64 : signal is "TRUE";
1782  --
1783  --attribute IOB of BF_DOUT_CTP_32 : signal is "TRUE";
1784  --attribute IOB of BF_DOUT_CTP_33 : signal is "TRUE";
1785  --attribute IOB of BF_DOUT_CTP_34 : signal is "TRUE";
1786  --attribute IOB of BF_DOUT_CTP_35 : signal is "TRUE";
1787  --attribute IOB of BF_DOUT_CTP_36 : signal is "TRUE";
1788  --attribute IOB of BF_DOUT_CTP_37 : signal is "TRUE";
1789  --attribute IOB of BF_DOUT_CTP_38 : signal is "TRUE";
1790  --attribute IOB of BF_DOUT_CTP_39 : signal is "TRUE";
1791  --attribute IOB of BF_DOUT_CTP_40 : signal is "TRUE";
1792  --attribute IOB of BF_DOUT_CTP_41 : signal is "TRUE";
1793  --attribute IOB of BF_DOUT_CTP_42 : signal is "TRUE";
1794  --attribute IOB of BF_DOUT_CTP_43 : signal is "TRUE";
1795  --attribute IOB of BF_DOUT_CTP_44 : signal is "TRUE";
1796  --attribute IOB of BF_DOUT_CTP_45 : signal is "TRUE";
1797  --attribute IOB of BF_DOUT_CTP_46 : signal is "TRUE";
1798  --attribute IOB of BF_DOUT_CTP_47 : signal is "TRUE";
1799  --attribute IOB of BF_DOUT_CTP_48 : signal is "TRUE";
1800  --attribute IOB of BF_DOUT_CTP_49 : signal is "TRUE";
1801  --attribute IOB of BF_DOUT_CTP_50 : signal is "TRUE";
1802  --attribute IOB of BF_DOUT_CTP_51 : signal is "TRUE";
1803  --attribute IOB of BF_DOUT_CTP_52 : signal is "TRUE";
1804  --attribute IOB of BF_DOUT_CTP_53 : signal is "TRUE";
1805  --attribute IOB of BF_DOUT_CTP_54 : signal is "TRUE";
1806  --attribute IOB of BF_DOUT_CTP_55 : signal is "TRUE";
1807  --attribute IOB of BF_DOUT_CTP_56 : signal is "TRUE";
1808  --attribute IOB of BF_DOUT_CTP_57 : signal is "TRUE";
1809  --attribute IOB of BF_DOUT_CTP_58 : signal is "TRUE";
1810  --attribute IOB of BF_DOUT_CTP_59 : signal is "TRUE";
1811  --attribute IOB of BF_DOUT_CTP_60 : signal is "TRUE";
1812  --attribute IOB of BF_DOUT_CTP_61 : signal is "TRUE";
1813 
1814 
1815 
1816 
1817 
1818 
1819 
1820 
1821 
1822 Begin
1823 
1824  --safety setup
1825  BF_REQ_CTP_1_INPUT <= '0';
1826  BF_REQ_CTP_2_INPUT <= '0';
1827  BF_REQ_CABLE_1_INPUT<= '1';
1828  BF_REQ_CABLE_2_INPUT<= '1';
1829  BF_REQ_CABLE_3_INPUT<= '1';
1830  BF_LED_REQ_0 <= '0';
1831  BF_LED_REQ_1 <= '0';
1832  BF_LED_REQ_2 <= '0';
1833  BF_LED_REQ_3 <= '0';
1834  BF_LED_REQ_4 <= '0';
1835  --BF_TO_FROM_BSPT_0 <= '0';
1836  --BF_TO_FROM_BSPT_1 <= '0';
1837  BF_TO_FROM_BSPT_2 <= '0';
1838  BF_TO_FROM_BSPT_3 <= '0';
1839  BF_TO_FROM_BSPT_4 <= '0';
1840  BF_TO_FROM_BSPT_5 <= '0';
1841  BF_TO_FROM_BSPT_6 <= '0';
1842  BF_TO_FROM_BSPT_7 <= '0';
1843 
1844  --sdr_data_out_CTP1
1845  BF_DOUT_CTP_00 <= sdr_data_CTP(0)(0);
1846  BF_DOUT_CTP_01 <= sdr_data_CTP(0)(1);
1847  BF_DOUT_CTP_02 <= sdr_data_CTP(0)(2);
1848  BF_DOUT_CTP_03 <= sdr_data_CTP(0)(3);
1849  BF_DOUT_CTP_04 <= sdr_data_CTP(0)(4);
1850  BF_DOUT_CTP_05 <= sdr_data_CTP(0)(5);
1851  BF_DOUT_CTP_06 <= sdr_data_CTP(0)(6);
1852  BF_DOUT_CTP_07 <= sdr_data_CTP(0)(7);
1853  BF_DOUT_CTP_08 <= sdr_data_CTP(0)(8);
1854  BF_DOUT_CTP_09 <= sdr_data_CTP(0)(9);
1855  BF_DOUT_CTP_10 <= sdr_data_CTP(0)(10);
1856  BF_DOUT_CTP_11 <= sdr_data_CTP(0)(11);
1857  BF_DOUT_CTP_12 <= sdr_data_CTP(0)(12);
1858  BF_DOUT_CTP_13 <= sdr_data_CTP(0)(13);
1859  BF_DOUT_CTP_14 <= sdr_data_CTP(0)(14);
1860  BF_DOUT_CTP_15 <= sdr_data_CTP(0)(15);
1861  BF_DOUT_CTP_16 <= sdr_data_CTP(0)(16);
1862  BF_DOUT_CTP_17 <= sdr_data_CTP(0)(17);
1863  BF_DOUT_CTP_18 <= sdr_data_CTP(0)(18);
1864  BF_DOUT_CTP_19 <= sdr_data_CTP(0)(19);
1865  BF_DOUT_CTP_20 <= sdr_data_CTP(0)(20);
1866  BF_DOUT_CTP_21 <= sdr_data_CTP(0)(21);
1867  BF_DOUT_CTP_22 <= sdr_data_CTP(0)(22);
1868  BF_DOUT_CTP_23 <= sdr_data_CTP(0)(23);
1869  BF_DOUT_CTP_24 <= sdr_data_CTP(0)(24);
1870  BF_DOUT_CTP_25 <= sdr_data_CTP(0)(25);
1871  BF_DOUT_CTP_26 <= sdr_data_CTP(0)(26);
1872  BF_DOUT_CTP_27 <= sdr_data_CTP(0)(27);
1873  BF_DOUT_CTP_28 <= sdr_data_CTP(0)(28);
1874  BF_DOUT_CTP_29 <= sdr_data_CTP(0)(29);
1875  BF_DOUT_CTP_30 <= '0';
1876  BF_DOUT_CTP_64 <= sdr_data_CTP(0)(30);
1877  BF_DOUT_CTP_31 <= sdr_data_CTP(0)(31);
1878 
1879 
1880  BF_DOUT_CTP_32 <= sdr_data_CTP(1)(0);
1881  BF_DOUT_CTP_33 <= sdr_data_CTP(1)(1);
1882  BF_DOUT_CTP_34 <= sdr_data_CTP(1)(2);
1883  BF_DOUT_CTP_35 <= sdr_data_CTP(1)(3);
1884  BF_DOUT_CTP_36 <= sdr_data_CTP(1)(4);
1885  BF_DOUT_CTP_37 <= sdr_data_CTP(1)(5);
1886  BF_DOUT_CTP_38 <= sdr_data_CTP(1)(6);
1887  BF_DOUT_CTP_39 <= sdr_data_CTP(1)(7);
1888  BF_DOUT_CTP_40 <= sdr_data_CTP(1)(8);
1889  BF_DOUT_CTP_41 <= sdr_data_CTP(1)(9);
1890  BF_DOUT_CTP_42 <= sdr_data_CTP(1)(10);
1891  BF_DOUT_CTP_43 <= sdr_data_CTP(1)(11);
1892  BF_DOUT_CTP_44 <= sdr_data_CTP(1)(12);
1893  BF_DOUT_CTP_45 <= sdr_data_CTP(1)(13);
1894  BF_DOUT_CTP_46 <= sdr_data_CTP(1)(14);
1895  BF_DOUT_CTP_47 <= sdr_data_CTP(1)(15);
1896  BF_DOUT_CTP_48 <= sdr_data_CTP(1)(16);
1897  BF_DOUT_CTP_49 <= sdr_data_CTP(1)(17);
1898  BF_DOUT_CTP_50 <= sdr_data_CTP(1)(18);
1899  BF_DOUT_CTP_51 <= sdr_data_CTP(1)(19);
1900  BF_DOUT_CTP_52 <= sdr_data_CTP(1)(20);
1901  BF_DOUT_CTP_53 <= sdr_data_CTP(1)(21);
1902  BF_DOUT_CTP_54 <= sdr_data_CTP(1)(22);
1903  BF_DOUT_CTP_55 <= sdr_data_CTP(1)(23);
1904  BF_DOUT_CTP_56 <= sdr_data_CTP(1)(24);
1905  BF_DOUT_CTP_57 <= sdr_data_CTP(1)(25);
1906  BF_DOUT_CTP_58 <= sdr_data_CTP(1)(26);
1907  BF_DOUT_CTP_59 <= sdr_data_CTP(1)(27);
1908  BF_DOUT_CTP_60 <= sdr_data_CTP(1)(28);
1909  BF_DOUT_CTP_61 <= sdr_data_CTP(1)(29);
1910  BF_DOUT_CTP_62 <= '0';
1911  BF_DOUT_CTP_65 <= sdr_data_CTP(1)(30);
1912  BF_DOUT_CTP_63 <= sdr_data_CTP(1)(31);
1913 
1914 
1915 
1916 
1917 
1918 
1919 
1920 
1921  --ddr_data_in_CTP2(0) <=BF_DOUT_CTP_32;
1922  --ddr_data_in_CTP2(1) <=BF_DOUT_CTP_33;
1923  --ddr_data_in_CTP2(2) <=BF_DOUT_CTP_34;
1924  --ddr_data_in_CTP2(3) <=BF_DOUT_CTP_35;
1925  --ddr_data_in_CTP2(4) <=BF_DOUT_CTP_36;
1926  --ddr_data_in_CTP2(5) <=BF_DOUT_CTP_37;
1927  --ddr_data_in_CTP2(6) <=BF_DOUT_CTP_38;
1928  --ddr_data_in_CTP2(7) <=BF_DOUT_CTP_39;
1929  --ddr_data_in_CTP2(8) <=BF_DOUT_CTP_40;
1930  --ddr_data_in_CTP2(9) <=BF_DOUT_CTP_41;
1931  --ddr_data_in_CTP2(10) <=BF_DOUT_CTP_42;
1932  --ddr_data_in_CTP2(11) <=BF_DOUT_CTP_43;
1933  --ddr_data_in_CTP2(12) <=BF_DOUT_CTP_44;
1934  --ddr_data_in_CTP2(13) <=BF_DOUT_CTP_45;
1935  --ddr_data_in_CTP2(14) <=BF_DOUT_CTP_46;
1936  --ddr_data_in_CTP2(15) <=BF_DOUT_CTP_47;
1937  --ddr_data_in_CTP2(16) <=BF_DOUT_CTP_48;
1938  --ddr_data_in_CTP2(17) <=BF_DOUT_CTP_49;
1939  --ddr_data_in_CTP2(18) <=BF_DOUT_CTP_50;
1940  --ddr_data_in_CTP2(19) <=BF_DOUT_CTP_51;
1941  --ddr_data_in_CTP2(20) <=BF_DOUT_CTP_52;
1942  --ddr_data_in_CTP2(21) <=BF_DOUT_CTP_53;
1943  --ddr_data_in_CTP2(22) <=BF_DOUT_CTP_54;
1944  --ddr_data_in_CTP2(23) <=BF_DOUT_CTP_55;
1945  --ddr_data_in_CTP2(24) <=BF_DOUT_CTP_56;
1946  --ddr_data_in_CTP2(25) <=BF_DOUT_CTP_57;
1947  --ddr_data_in_CTP2(26) <=BF_DOUT_CTP_58;
1948  --ddr_data_in_CTP2(27) <=BF_DOUT_CTP_59;
1949  --ddr_data_in_CTP2(28) <=BF_DOUT_CTP_60;
1950  --ddr_data_in_CTP2(29) <=BF_DOUT_CTP_61;
1951  --ddr_data_in_CTP2(30) <=BF_DOUT_CTP_62;
1952  --ddr_data_in_CTP2(31) <=BF_DOUT_CTP_65;
1953  --ddr_data_in_CTP2(32) <=BF_DOUT_CTP_63;
1954 
1955 
1956 
1957  ddr_data_in_RTM1(0) <= D_CBL_00_B;
1958  ddr_data_in_RTM1(1) <= D_CBL_01_B;
1959  ddr_data_in_RTM1(2) <= D_CBL_02_B;
1960  ddr_data_in_RTM1(3) <= D_CBL_03_B;
1961  ddr_data_in_RTM1(4) <= D_CBL_04_B;
1962  ddr_data_in_RTM1(5) <= D_CBL_05_B;
1963  ddr_data_in_RTM1(6) <= D_CBL_06_B;
1964  ddr_data_in_RTM1(7) <= D_CBL_07_B;
1965  ddr_data_in_RTM1(8) <= D_CBL_08_B;
1966  ddr_data_in_RTM1(9) <= D_CBL_09_B;
1967  ddr_data_in_RTM1(10) <= D_CBL_10_B;
1968  ddr_data_in_RTM1(11) <= D_CBL_11_B;
1969  ddr_data_in_RTM1(12) <= D_CBL_12_B;
1970  ddr_data_in_RTM1(13) <= D_CBL_13_B;
1971  ddr_data_in_RTM1(14) <= D_CBL_14_B;
1972  ddr_data_in_RTM1(15) <= D_CBL_15_B;
1973  ddr_data_in_RTM1(16) <= D_CBL_16_B;
1974  ddr_data_in_RTM1(17) <= D_CBL_17_B;
1975  ddr_data_in_RTM1(18) <= D_CBL_18_B;
1976  ddr_data_in_RTM1(19) <= D_CBL_19_B;
1977  ddr_data_in_RTM1(20) <= D_CBL_20_B;
1978  ddr_data_in_RTM1(21) <= D_CBL_21_B;
1979  ddr_data_in_RTM1(22) <= D_CBL_22_B;
1980  ddr_data_in_RTM1(23) <= D_CBL_23_B;
1981  ddr_data_in_RTM1(24) <= D_CBL_24_B;
1982  ddr_data_in_RTM1(26) <= D_CBL_25_B;
1983  ddr_data_in_RTM1(25) <= D_CBL_26_B;
1984 
1985 
1986  ddr_data_in_RTM2(0) <= D_CBL_27_B;
1987  ddr_data_in_RTM2(1) <= D_CBL_28_B;
1988  ddr_data_in_RTM2(2) <= D_CBL_29_B;
1989  ddr_data_in_RTM2(3) <= D_CBL_30_B;
1990  ddr_data_in_RTM2(4) <= D_CBL_31_B;
1991  ddr_data_in_RTM2(5) <= D_CBL_32_B;
1992  ddr_data_in_RTM2(6) <= D_CBL_33_B;
1993  ddr_data_in_RTM2(7) <= D_CBL_34_B;
1994  ddr_data_in_RTM2(8) <= D_CBL_35_B;
1995  ddr_data_in_RTM2(9) <= D_CBL_36_B;
1996  ddr_data_in_RTM2(10) <= D_CBL_37_B;
1997  ddr_data_in_RTM2(11) <= D_CBL_38_B;
1998  ddr_data_in_RTM2(12) <= D_CBL_39_B;
1999  ddr_data_in_RTM2(13) <= D_CBL_40_B;
2000  ddr_data_in_RTM2(14) <= D_CBL_41_B;
2001  ddr_data_in_RTM2(15) <= D_CBL_42_B;
2002  ddr_data_in_RTM2(16) <= D_CBL_43_B;
2003  ddr_data_in_RTM2(17) <= D_CBL_44_B;
2004  ddr_data_in_RTM2(18) <= D_CBL_45_B;
2005  ddr_data_in_RTM2(19) <= D_CBL_46_B;
2006  ddr_data_in_RTM2(20) <= D_CBL_47_B;
2007  ddr_data_in_RTM2(21) <= D_CBL_50_B;
2008  ddr_data_in_RTM2(22) <= D_CBL_51_B;
2009  ddr_data_in_RTM2(23) <= D_CBL_52_B;
2010  ddr_data_in_RTM2(24) <= D_CBL_53_B;
2011  ddr_data_in_RTM2(26) <= D_CBL_48_B;
2012  ddr_data_in_RTM2(25) <= D_CBL_49_B;
2013 
2014  ddr_data_in_RTM3(0) <= D_CBL_54_B;
2015  ddr_data_in_RTM3(1) <= D_CBL_55_B;
2016  ddr_data_in_RTM3(2) <= D_CBL_56_B;
2017  ddr_data_in_RTM3(3) <= D_CBL_57_B;
2018  ddr_data_in_RTM3(4) <= D_CBL_58_B;
2019  ddr_data_in_RTM3(5) <= D_CBL_59_B;
2020  ddr_data_in_RTM3(6) <= D_CBL_60_B;
2021  ddr_data_in_RTM3(7) <= D_CBL_61_B;
2022  ddr_data_in_RTM3(8) <= D_CBL_62_B;
2023  ddr_data_in_RTM3(9) <= D_CBL_63_B;
2024  ddr_data_in_RTM3(10)<= D_CBL_64_B;
2025  ddr_data_in_RTM3(11)<= D_CBL_65_B;
2026  ddr_data_in_RTM3(12)<= D_CBL_66_B;
2027  ddr_data_in_RTM3(13)<= D_CBL_67_B;
2028  ddr_data_in_RTM3(14)<= D_CBL_68_B;
2029  ddr_data_in_RTM3(15)<= D_CBL_69_B;
2030  ddr_data_in_RTM3(16)<= D_CBL_70_B;
2031  ddr_data_in_RTM3(17)<= D_CBL_71_B;
2032  ddr_data_in_RTM3(18)<= D_CBL_72_B;
2033  ddr_data_in_RTM3(19)<= D_CBL_73_B;
2034  ddr_data_in_RTM3(20)<= D_CBL_74_B;
2035  ddr_data_in_RTM3(21)<= D_CBL_75_B;
2036  ddr_data_in_RTM3(22)<= D_CBL_76_B;
2037  ddr_data_in_RTM3(23)<= D_CBL_77_B;
2038  ddr_data_in_RTM3(24)<= D_CBL_80_B;
2039  ddr_data_in_RTM3(25)<= D_CBL_79_B;
2040  ddr_data_in_RTM3(26)<= D_CBL_78_B;
2041 
2042  sig_arr_RTM(0)<=ddr_data_in_RTM1;
2043  sig_arr_RTM(1)<=ddr_data_in_RTM2;
2044  sig_arr_RTM(2)<=ddr_data_in_RTM3;
2045 
2046 
2047  --D_CBL_81_B <= '0';
2048  --D_CBL_82_B <= '0';
2049 
2050  --BF_TO_TP_DAQ_SLINK_RETURN_DIR ;--<= '0';
2051  --BF_TO_TP_DAQ_SLINK_RETURN_CMP ;--<= '0';
2052  --BF_TO_TP_ROI_SLINK_RETURN_DIR ;--<= '0';
2053  --BF_TO_TP_ROI_SLINK_RETURN_CMP ;--<= '0';
2054  --end safety setup
2055 
2056  --backplane bus assignment
2057  P(0)(0) <= P0_0;
2058  P(0)(1) <= P0_1;
2059  P(0)(2) <= P0_2;
2060  P(0)(3) <= P0_3;
2061  P(0)(4) <= P0_4;
2062  P(0)(5) <= P0_5;
2063  P(0)(6) <= P0_6;
2064  P(0)(7) <= P0_7;
2065  P(0)(8) <= P0_8;
2066  P(0)(9) <= P0_9;
2067  P(0)(10) <= P0_10;
2068  P(0)(11) <= P0_11;
2069  P(0)(12) <= P0_12;
2070  P(0)(13) <= P0_13;
2071  P(0)(14) <= P0_14;
2072  P(0)(15) <= P0_15;
2073  P(0)(16) <= P0_16;
2074  P(0)(17) <= P0_17;
2075  P(0)(18) <= P0_18;
2076  P(0)(19) <= P0_19;
2077  P(0)(20) <= P0_20;
2078  P(0)(21) <= P0_21;
2079  P(0)(22) <= P0_22;
2080  P(0)(23) <= P0_23;
2081  P(0)(24) <= P0_24;
2082  P(1)(0) <= P1_0;
2083  P(1)(1) <= P1_1;
2084  P(1)(2) <= P1_2;
2085  P(1)(3) <= P1_3;
2086  P(1)(4) <= P1_4;
2087  P(1)(5) <= P1_5;
2088  P(1)(6) <= P1_6;
2089  P(1)(7) <= P1_7;
2090  P(1)(8) <= P1_8;
2091  P(1)(9) <= P1_9;
2092  P(1)(10) <= P1_10;
2093  P(1)(11) <= P1_11;
2094  P(1)(12) <= P1_12;
2095  P(1)(13) <= P1_13;
2096  P(1)(14) <= P1_14;
2097  P(1)(15) <= P1_15;
2098  P(1)(16) <= P1_16;
2099  P(1)(17) <= P1_17;
2100  P(1)(18) <= P1_18;
2101  P(1)(19) <= P1_19;
2102  P(1)(20) <= P1_20;
2103  P(1)(21) <= P1_21;
2104  P(1)(22) <= P1_22;
2105  P(1)(23) <= P1_23;
2106  P(1)(24) <= P1_24;
2107  P(2)(0) <= P2_0;
2108  P(2)(1) <= P2_1;
2109  P(2)(2) <= P2_2;
2110  P(2)(3) <= P2_3;
2111  P(2)(4) <= P2_4;
2112  P(2)(5) <= P2_5;
2113  P(2)(6) <= P2_6;
2114  P(2)(7) <= P2_7;
2115  P(2)(8) <= P2_8;
2116  P(2)(9) <= P2_9;
2117  P(2)(10) <= P2_10;
2118  P(2)(11) <= P2_11;
2119  P(2)(12) <= P2_12;
2120  P(2)(13) <= P2_13;
2121  P(2)(14) <= P2_14;
2122  P(2)(15) <= P2_15;
2123  P(2)(16) <= P2_16;
2124  P(2)(17) <= P2_17;
2125  P(2)(18) <= P2_18;
2126  P(2)(19) <= P2_19;
2127  P(2)(20) <= P2_20;
2128  P(2)(21) <= P2_21;
2129  P(2)(22) <= P2_22;
2130  P(2)(23) <= P2_23;
2131  P(2)(24) <= P2_24;
2132  P(3)(0) <= P3_0;
2133  P(3)(1) <= P3_1;
2134  P(3)(2) <= P3_2;
2135  P(3)(3) <= P3_3;
2136  P(3)(4) <= P3_4;
2137  P(3)(5) <= P3_5;
2138  P(3)(6) <= P3_6;
2139  P(3)(7) <= P3_7;
2140  P(3)(8) <= P3_8;
2141  P(3)(9) <= P3_9;
2142  P(3)(10) <= P3_10;
2143  P(3)(11) <= P3_11;
2144  P(3)(12) <= P3_12;
2145  P(3)(13) <= P3_13;
2146  P(3)(14) <= P3_14;
2147  P(3)(15) <= P3_15;
2148  P(3)(16) <= P3_16;
2149  P(3)(17) <= P3_17;
2150  P(3)(18) <= P3_18;
2151  P(3)(19) <= P3_19;
2152  P(3)(20) <= P3_20;
2153  P(3)(21) <= P3_21;
2154  P(3)(22) <= P3_22;
2155  P(3)(23) <= P3_23;
2156  P(3)(24) <= P3_24;
2157  P(4)(0) <= P4_0;
2158  P(4)(1) <= P4_1;
2159  P(4)(2) <= P4_2;
2160  P(4)(3) <= P4_3;
2161  P(4)(4) <= P4_4;
2162  P(4)(5) <= P4_5;
2163  P(4)(6) <= P4_6;
2164  P(4)(7) <= P4_7;
2165  P(4)(8) <= P4_8;
2166  P(4)(9) <= P4_9;
2167  P(4)(10) <= P4_10;
2168  P(4)(11) <= P4_11;
2169  P(4)(12) <= P4_12;
2170  P(4)(13) <= P4_13;
2171  P(4)(14) <= P4_14;
2172  P(4)(15) <= P4_15;
2173  P(4)(16) <= P4_16;
2174  P(4)(17) <= P4_17;
2175  P(4)(18) <= P4_18;
2176  P(4)(19) <= P4_19;
2177  P(4)(20) <= P4_20;
2178  P(4)(21) <= P4_21;
2179  P(4)(22) <= P4_22;
2180  P(4)(23) <= P4_23;
2181  P(4)(24) <= P4_24;
2182  P(5)(0) <= P5_0;
2183  P(5)(1) <= P5_1;
2184  P(5)(2) <= P5_2;
2185  P(5)(3) <= P5_3;
2186  P(5)(4) <= P5_4;
2187  P(5)(5) <= P5_5;
2188  P(5)(6) <= P5_6;
2189  P(5)(7) <= P5_7;
2190  P(5)(8) <= P5_8;
2191  P(5)(9) <= P5_9;
2192  P(5)(10) <= P5_10;
2193  P(5)(11) <= P5_11;
2194  P(5)(12) <= P5_12;
2195  P(5)(13) <= P5_13;
2196  P(5)(14) <= P5_14;
2197  P(5)(15) <= P5_15;
2198  P(5)(16) <= P5_16;
2199  P(5)(17) <= P5_17;
2200  P(5)(18) <= P5_18;
2201  P(5)(19) <= P5_19;
2202  P(5)(20) <= P5_20;
2203  P(5)(21) <= P5_21;
2204  P(5)(22) <= P5_22;
2205  P(5)(23) <= P5_23;
2206  P(5)(24) <= P5_24;
2207  P(6)(0) <= P6_0;
2208  P(6)(1) <= P6_1;
2209  P(6)(2) <= P6_2;
2210  P(6)(3) <= P6_3;
2211  P(6)(4) <= P6_4;
2212  P(6)(5) <= P6_5;
2213  P(6)(6) <= P6_6;
2214  P(6)(7) <= P6_7;
2215  P(6)(8) <= P6_8;
2216  P(6)(9) <= P6_9;
2217  P(6)(10) <= P6_10;
2218  P(6)(11) <= P6_11;
2219  P(6)(12) <= P6_12;
2220  P(6)(13) <= P6_13;
2221  P(6)(14) <= P6_14;
2222  P(6)(15) <= P6_15;
2223  P(6)(16) <= P6_16;
2224  P(6)(17) <= P6_17;
2225  P(6)(18) <= P6_18;
2226  P(6)(19) <= P6_19;
2227  P(6)(20) <= P6_20;
2228  P(6)(21) <= P6_21;
2229  P(6)(22) <= P6_22;
2230  P(6)(23) <= P6_23;
2231  P(6)(24) <= P6_24;
2232  P(7)(0) <= P7_0;
2233  P(7)(1) <= P7_1;
2234  P(7)(2) <= P7_2;
2235  P(7)(3) <= P7_3;
2236  P(7)(4) <= P7_4;
2237  P(7)(5) <= P7_5;
2238  P(7)(6) <= P7_6;
2239  P(7)(7) <= P7_7;
2240  P(7)(8) <= P7_8;
2241  P(7)(9) <= P7_9;
2242  P(7)(10) <= P7_10;
2243  P(7)(11) <= P7_11;
2244  P(7)(12) <= P7_12;
2245  P(7)(13) <= P7_13;
2246  P(7)(14) <= P7_14;
2247  P(7)(15) <= P7_15;
2248  P(7)(16) <= P7_16;
2249  P(7)(17) <= P7_17;
2250  P(7)(18) <= P7_18;
2251  P(7)(19) <= P7_19;
2252  P(7)(20) <= P7_20;
2253  P(7)(21) <= P7_21;
2254  P(7)(22) <= P7_22;
2255  P(7)(23) <= P7_23;
2256  P(7)(24) <= P7_24;
2257  P(8)(0) <= P8_0;
2258  P(8)(1) <= P8_1;
2259  P(8)(2) <= P8_2;
2260  P(8)(3) <= P8_3;
2261  P(8)(4) <= P8_4;
2262  P(8)(5) <= P8_5;
2263  P(8)(6) <= P8_6;
2264  P(8)(7) <= P8_7;
2265  P(8)(8) <= P8_8;
2266  P(8)(9) <= P8_9;
2267  P(8)(10) <= P8_10;
2268  P(8)(11) <= P8_11;
2269  P(8)(12) <= P8_12;
2270  P(8)(13) <= P8_13;
2271  P(8)(14) <= P8_14;
2272  P(8)(15) <= P8_15;
2273  P(8)(16) <= P8_16;
2274  P(8)(17) <= P8_17;
2275  P(8)(18) <= P8_18;
2276  P(8)(19) <= P8_19;
2277  P(8)(20) <= P8_20;
2278  P(8)(21) <= P8_21;
2279  P(8)(22) <= P8_22;
2280  P(8)(23) <= P8_23;
2281  P(8)(24) <= P8_24;
2282  P(9)(0) <= P9_0;
2283  P(9)(1) <= P9_1;
2284  P(9)(2) <= P9_2;
2285  P(9)(3) <= P9_3;
2286  P(9)(4) <= P9_4;
2287  P(9)(5) <= P9_5;
2288  P(9)(6) <= P9_6;
2289  P(9)(7) <= P9_7;
2290  P(9)(8) <= P9_8;
2291  P(9)(9) <= P9_9;
2292  P(9)(10) <= P9_10;
2293  P(9)(11) <= P9_11;
2294  P(9)(12) <= P9_12;
2295  P(9)(13) <= P9_13;
2296  P(9)(14) <= P9_14;
2297  P(9)(15) <= P9_15;
2298  P(9)(16) <= P9_16;
2299  P(9)(17) <= P9_17;
2300  P(9)(18) <= P9_18;
2301  P(9)(19) <= P9_19;
2302  P(9)(20) <= P9_20;
2303  P(9)(21) <= P9_21;
2304  P(9)(22) <= P9_22;
2305  P(9)(23) <= P9_23;
2306  P(9)(24) <= P9_24;
2307  P(10)(0) <= P10_0;
2308  P(10)(1) <= P10_1;
2309  P(10)(2) <= P10_2;
2310  P(10)(3) <= P10_3;
2311  P(10)(4) <= P10_4;
2312  P(10)(5) <= P10_5;
2313  P(10)(6) <= P10_6;
2314  P(10)(7) <= P10_7;
2315  P(10)(8) <= P10_8;
2316  P(10)(9) <= P10_9;
2317  P(10)(10) <= P10_10;
2318  P(10)(11) <= P10_11;
2319  P(10)(12) <= P10_12;
2320  P(10)(13) <= P10_13;
2321  P(10)(14) <= P10_14;
2322  P(10)(15) <= P10_15;
2323  P(10)(16) <= P10_16;
2324  P(10)(17) <= P10_17;
2325  P(10)(18) <= P10_18;
2326  P(10)(19) <= P10_19;
2327  P(10)(20) <= P10_20;
2328  P(10)(21) <= P10_21;
2329  P(10)(22) <= P10_22;
2330  P(10)(23) <= P10_23;
2331  P(10)(24) <= P10_24;
2332  P(11)(0) <= P11_0;
2333  P(11)(1) <= P11_1;
2334  P(11)(2) <= P11_2;
2335  P(11)(3) <= P11_3;
2336  P(11)(4) <= P11_4;
2337  P(11)(5) <= P11_5;
2338  P(11)(6) <= P11_6;
2339  P(11)(7) <= P11_7;
2340  P(11)(8) <= P11_8;
2341  P(11)(9) <= P11_9;
2342  P(11)(10) <= P11_10;
2343  P(11)(11) <= P11_11;
2344  P(11)(12) <= P11_12;
2345  P(11)(13) <= P11_13;
2346  P(11)(14) <= P11_14;
2347  P(11)(15) <= P11_15;
2348  P(11)(16) <= P11_16;
2349  P(11)(17) <= P11_17;
2350  P(11)(18) <= P11_18;
2351  P(11)(19) <= P11_19;
2352  P(11)(20) <= P11_20;
2353  P(11)(21) <= P11_21;
2354  P(11)(22) <= P11_22;
2355  P(11)(23) <= P11_23;
2356  P(11)(24) <= P11_24;
2357  P(12)(0) <= P12_0;
2358  P(12)(1) <= P12_1;
2359  P(12)(2) <= P12_2;
2360  P(12)(3) <= P12_3;
2361  P(12)(4) <= P12_4;
2362  P(12)(5) <= P12_5;
2363  P(12)(6) <= P12_6;
2364  P(12)(7) <= P12_7;
2365  P(12)(8) <= P12_8;
2366  P(12)(9) <= P12_9;
2367  P(12)(10) <= P12_10;
2368  P(12)(11) <= P12_11;
2369  P(12)(12) <= P12_12;
2370  P(12)(13) <= P12_13;
2371  P(12)(14) <= P12_14;
2372  P(12)(15) <= P12_15;
2373  P(12)(16) <= P12_16;
2374  P(12)(17) <= P12_17;
2375  P(12)(18) <= P12_18;
2376  P(12)(19) <= P12_19;
2377  P(12)(20) <= P12_20;
2378  P(12)(21) <= P12_21;
2379  P(12)(22) <= P12_22;
2380  P(12)(23) <= P12_23;
2381  P(12)(24) <= P12_24;
2382  P(13)(0) <= P13_0;
2383  P(13)(1) <= P13_1;
2384  P(13)(2) <= P13_2;
2385  P(13)(3) <= P13_3;
2386  P(13)(4) <= P13_4;
2387  P(13)(5) <= P13_5;
2388  P(13)(6) <= P13_6;
2389  P(13)(7) <= P13_7;
2390  P(13)(8) <= P13_8;
2391  P(13)(9) <= P13_9;
2392  P(13)(10) <= P13_10;
2393  P(13)(11) <= P13_11;
2394  P(13)(12) <= P13_12;
2395  P(13)(13) <= P13_13;
2396  P(13)(14) <= P13_14;
2397  P(13)(15) <= P13_15;
2398  P(13)(16) <= P13_16;
2399  P(13)(17) <= P13_17;
2400  P(13)(18) <= P13_18;
2401  P(13)(19) <= P13_19;
2402  P(13)(20) <= P13_20;
2403  P(13)(21) <= P13_21;
2404  P(13)(22) <= P13_22;
2405  P(13)(23) <= P13_23;
2406  P(13)(24) <= P13_24;
2407  P(14)(0) <= P14_0;
2408  P(14)(1) <= P14_1;
2409  P(14)(2) <= P14_2;
2410  P(14)(3) <= P14_3;
2411  P(14)(4) <= P14_4;
2412  P(14)(5) <= P14_5;
2413  P(14)(6) <= P14_6;
2414  P(14)(7) <= P14_7;
2415  P(14)(8) <= P14_8;
2416  P(14)(9) <= P14_9;
2417  P(14)(10) <= P14_10;
2418  P(14)(11) <= P14_11;
2419  P(14)(12) <= P14_12;
2420  P(14)(13) <= P14_13;
2421  P(14)(14) <= P14_14;
2422  P(14)(15) <= P14_15;
2423  P(14)(16) <= P14_16;
2424  P(14)(17) <= P14_17;
2425  P(14)(18) <= P14_18;
2426  P(14)(19) <= P14_19;
2427  P(14)(20) <= P14_20;
2428  P(14)(21) <= P14_21;
2429  P(14)(22) <= P14_22;
2430  P(14)(23) <= P14_23;
2431  P(14)(24) <= P14_24;
2432  P(15)(0) <= P15_0;
2433  P(15)(1) <= P15_1;
2434  P(15)(2) <= P15_2;
2435  P(15)(3) <= P15_3;
2436  P(15)(4) <= P15_4;
2437  P(15)(5) <= P15_5;
2438  P(15)(6) <= P15_6;
2439  P(15)(7) <= P15_7;
2440  P(15)(8) <= P15_8;
2441  P(15)(9) <= P15_9;
2442  P(15)(10) <= P15_10;
2443  P(15)(11) <= P15_11;
2444  P(15)(12) <= P15_12;
2445  P(15)(13) <= P15_13;
2446  P(15)(14) <= P15_14;
2447  P(15)(15) <= P15_15;
2448  P(15)(16) <= P15_16;
2449  P(15)(17) <= P15_17;
2450  P(15)(18) <= P15_18;
2451  P(15)(19) <= P15_19;
2452  P(15)(20) <= P15_20;
2453  P(15)(21) <= P15_21;
2454  P(15)(22) <= P15_22;
2455  P(15)(23) <= P15_23;
2456  P(15)(24) <= P15_24;
2457 
2458 
2459 
2460  MP1_F01_QUAD_110_TRN_0_DIR <= TXP_OUT(0) ;
2461  MP1_F01_QUAD_110_TRN_0_CMP <= TXN_OUT(0) ;
2462  MP1_F03_QUAD_110_TRN_1_DIR <= TXP_OUT(1) ;
2463  MP1_F03_QUAD_110_TRN_1_CMP <= TXN_OUT(1) ;
2464  MP1_F07_QUAD_110_TRN_2_DIR <= TXP_OUT(2) ;
2465  MP1_F07_QUAD_110_TRN_2_CMP <= TXN_OUT(2) ;
2466  MP1_F05_QUAD_110_TRN_3_DIR <= TXP_OUT(3) ;
2467  MP1_F05_QUAD_110_TRN_3_CMP <= TXN_OUT(3) ;
2468  MP1_F09_QUAD_111_TRN_0_DIR <= TXP_OUT(4) ;
2469  MP1_F09_QUAD_111_TRN_0_CMP <= TXN_OUT(4) ;
2470  MP1_F11_QUAD_111_TRN_1_DIR <= TXP_OUT(5) ;
2471  MP1_F11_QUAD_111_TRN_1_CMP <= TXN_OUT(5) ;
2472  MP1_F10_QUAD_111_TRN_2_DIR <= TXP_OUT(6) ;
2473  MP1_F10_QUAD_111_TRN_2_CMP <= TXN_OUT(6) ;
2474  MP1_F08_QUAD_111_TRN_3_DIR <= TXP_OUT(7) ;
2475  MP1_F08_QUAD_111_TRN_3_CMP <= TXN_OUT(7) ;
2476  MP1_F04_QUAD_112_TRN_0_DIR <= TXP_OUT(8) ;
2477  MP1_F04_QUAD_112_TRN_0_CMP <= TXN_OUT(8) ;
2478  MP1_F06_QUAD_112_TRN_1_DIR <= TXP_OUT(9) ;
2479  MP1_F06_QUAD_112_TRN_1_CMP <= TXN_OUT(9) ;
2480  MP1_F02_QUAD_112_TRN_2_DIR <= TXP_OUT(10) ;
2481  MP1_F02_QUAD_112_TRN_2_CMP <= TXN_OUT(10) ;
2482  MP1_F00_QUAD_112_TRN_3_DIR <= TXP_OUT(11) ;
2483  MP1_F00_QUAD_112_TRN_3_CMP <= TXN_OUT(11) ;
2484  MP2_F01_QUAD_113_TRN_0_DIR <= TXP_OUT(12) ;
2485  MP2_F01_QUAD_113_TRN_0_CMP <= TXN_OUT(12) ;
2486  MP2_F03_QUAD_113_TRN_1_DIR <= TXP_OUT(13) ;
2487  MP2_F03_QUAD_113_TRN_1_CMP <= TXN_OUT(13) ;
2488  MP2_F07_QUAD_113_TRN_2_DIR <= TXP_OUT(14) ;
2489  MP2_F07_QUAD_113_TRN_2_CMP <= TXN_OUT(14) ;
2490  MP2_F05_QUAD_113_TRN_3_DIR <= TXP_OUT(15) ;
2491  MP2_F05_QUAD_113_TRN_3_CMP <= TXN_OUT(15) ;
2492  MP2_F09_QUAD_114_TRN_0_DIR <= TXP_OUT(16) ;
2493  MP2_F09_QUAD_114_TRN_0_CMP <= TXN_OUT(16) ;
2494  MP2_F11_QUAD_114_TRN_1_DIR <= TXP_OUT(17) ;
2495  MP2_F11_QUAD_114_TRN_1_CMP <= TXN_OUT(17) ;
2496  MP2_F10_QUAD_114_TRN_2_DIR <= TXP_OUT(18) ;
2497  MP2_F10_QUAD_114_TRN_2_CMP <= TXN_OUT(18) ;
2498  MP2_F08_QUAD_114_TRN_3_DIR <= TXP_OUT(19) ;
2499  MP2_F08_QUAD_114_TRN_3_CMP <= TXN_OUT(19) ;
2500  MP2_F04_QUAD_115_TRN_0_DIR <= TXP_OUT(20) ;
2501  MP2_F04_QUAD_115_TRN_0_CMP <= TXN_OUT(20) ;
2502  MP2_F06_QUAD_115_TRN_1_DIR <= TXP_OUT(21) ;
2503  MP2_F06_QUAD_115_TRN_1_CMP <= TXN_OUT(21) ;
2504  MP2_F02_QUAD_115_TRN_2_DIR <= TXP_OUT(22) ;
2505  MP2_F02_QUAD_115_TRN_2_CMP <= TXN_OUT(22) ;
2506  MP2_F00_QUAD_115_TRN_3_DIR <= TXP_OUT(23) ;
2507  MP2_F00_QUAD_115_TRN_3_CMP <= TXN_OUT(23) ;
2508 
2509  MGTREFCLK_PAD_P_IN(0) <= CLK_320MHz64_LHC_BF_QUAD_111_DIR;
2510  MGTREFCLK_PAD_N_IN(0) <= CLK_320MHz64_LHC_BF_QUAD_111_CMP;
2511  MGTREFCLK_PAD_P_IN(1) <= CLK_320MHz64_LHC_BF_QUAD_114_DIR;
2512  MGTREFCLK_PAD_N_IN(1) <= CLK_320MHz64_LHC_BF_QUAD_114_CMP;
2513 
2514 
2515 
2516  --debug pins bus assignment
2517  BF_DEBUG_0 <= BF_DEBUG(0);
2518  BF_DEBUG_1 <= BF_DEBUG(1);
2519  BF_DEBUG_2 <= BF_DEBUG(2);
2520  BF_DEBUG_3 <= BF_DEBUG(3);
2521  BF_DEBUG_4 <= BF_DEBUG(4);
2522  BF_DEBUG_5 <= BF_DEBUG(5);
2523  BF_DEBUG_6 <= BF_DEBUG(6);
2524  BF_DEBUG_7 <= BF_DEBUG(7);
2525  BF_DEBUG_8 <= BF_DEBUG(8);
2526  BF_DEBUG_9 <= BF_DEBUG(9);
2527 
2528 
2529  ODDR_inst_buf_clk_40 : ODDR
2530  generic map(
2531  DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
2532  INIT => '0', -- Initial value for Q port ('1' or '0')
2533  SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
2534  port map (
2535  Q => BF_DEBUG(8), -- 1-bit DDR output
2536  C => buf_clk40, -- 1-bit clock input
2537  CE => '1', -- 1-bit clock enable input
2538  D1 => '1', -- 1-bit data input (positive edge)
2539  D2 => '0', -- 1-bit data input (negative edge)
2540  R => (not pll_locked), -- 1-bit reset input
2541  S => '0' -- 1-bit set input
2542  );
2543 
2544  ODDR_inst_buf_clk_40_ds2 : ODDR
2545  generic map(
2546  DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
2547  INIT => '0', -- Initial value for Q port ('1' or '0')
2548  SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
2549  port map (
2550  Q => BF_DEBUG(9), -- 1-bit DDR output
2551  C => buf_clk40_ds2, -- 1-bit clock input
2552  CE => '1', -- 1-bit clock enable input
2553  D1 => '1', -- 1-bit data input (positive edge)
2554  D2 => '0', -- 1-bit data input (negative edge)
2555  R => (not pll_locked_ds2), -- 1-bit reset input
2556  S => '0' -- 1-bit set input
2557  );
2558 
2559 
2560  --BF_DEBUG(8) <= buf_clk40;
2561  --BF_DEBUG(9) <= l1a_synced;--DATA96(5)(0);--start_playback;--BF_TO_TP_DAQ_SLINK_RETURN_DIR;--send_align(0);-- BUF_TTC_BNCH_CNT_RES; --bunch counter reset
2562 
2563  BF_DEBUG(7 downto 0)<=(others=>'0');
2564 
2565  vme_address(1) <= OCB_A01;
2566  vme_address(2) <= OCB_A02;
2567  vme_address(3) <= OCB_A03;
2568  vme_address(4) <= OCB_A04;
2569  vme_address(5) <= OCB_A05;
2570  vme_address(6) <= OCB_A06;
2571  vme_address(7) <= OCB_A07;
2572  vme_address(8) <= OCB_A08;
2573  vme_address(9) <= OCB_A09;
2574  vme_address(10) <= OCB_A10;
2575  vme_address(11) <= OCB_A11;
2576  vme_address(12) <= OCB_A12;
2577  vme_address(13) <= OCB_A13;
2578  vme_address(14) <= OCB_A14;
2579  vme_address(15) <= OCB_A15;
2580  vme_address(16) <= OCB_A16;
2581  vme_address(17) <= OCB_A17;
2582  vme_address(18) <= OCB_A18;
2583  vme_address(19) <= OCB_A19;
2584  vme_address(20) <= OCB_A20;
2585  vme_address(21) <= OCB_A21;
2586  vme_address(22) <= OCB_A22;
2587  vme_address(23) <= OCB_A23;
2588 
2589  ------------------------------------------------------------------------------
2590  -- VME interface component used in BSPT FPGA (Ian's vme_interface)
2591  ------------------------------------------------------------------------------
2592  CMX_BASE_VMEIF_BSPT : CMX_BASE_VME_BSPT
2593  port map (
2594  ----------------------------------------------------------------------------
2595  -- inputs
2596  ----------------------------------------------------------------------------
2597  clk40 => buf_clk40 ,
2598  geoadd_0 => OCB_GEO_ADRS_0 ,
2599  n_ds0_int => OCB_DS_B,
2600  n_write => OCB_WRITE_B ,
2601  -- vme_address
2602  vme_address => vme_address,
2603  ----------------------------------------------------------------------------
2604  -- outputs
2605  ----------------------------------------------------------------------------
2606  board_ds => ds, -- board_ds output from VME (Ian model)
2607  brdsel_n => ncs -- brdsel_n output from VME (Ian model)
2608  );
2609 
2610 
2611 
2612  vme_main_hub_inst: entity work.vme_main_hub
2613  port map (
2614  data_vme => OCB_D,
2615  data_vme_from_below => data_vme_up_top,
2616  bus_drive_from_below => bus_drive_up_top ,
2617  data_vme_going_below => data_vme_going_below);
2618 
2619 
2620  vme_local_switch_inst: entity work.vme_local_switch
2621  port map (
2622  data_vme_up => data_vme_up_top,
2623  data_vme_from_below => data_vme_from_below_top ,
2624  bus_drive_up => bus_drive_up_top ,
2625  bus_drive_from_below => bus_drive_from_below_top );
2626 
2627 
2628  CMX_version_inst: entity work.CMX_version
2629  port map (
2630  clk40 => buf_clk40 ,
2631  ncs => ncs,
2632  rd_nwr => OCB_WRITE_B ,
2633  ds => ds,
2634  addr_vme => vme_address(16 downto 1),
2635  data_vme_out => data_vme_from_below_top(1605),
2636  bus_drive => bus_drive_from_below_top (1605));
2637 
2638 
2639 
2640  sys_monitor_inst: entity work.sys_monitor
2641  generic map (
2642  ADDR_REG_RO_SYSMON_DATA_BLOCK => ADDR_REG_RO_SYSMON_DATA_BLOCK)
2643  port map (
2644  clk => buf_clk40 ,
2645  BF_SYSMON_01_P => BF_SYSMON_01_P,
2646  BF_SYSMON_01_N => BF_SYSMON_01_N,
2647  BF_SYSMON_03_P => BF_SYSMON_03_P,
2648  BF_SYSMON_03_N => BF_SYSMON_03_N,
2649  BF_SYSMON_04_P => BF_SYSMON_04_P,
2650  BF_SYSMON_04_N => BF_SYSMON_04_N,
2651  BF_SYSMON_07_P => BF_SYSMON_07_P,
2652  BF_SYSMON_07_N => BF_SYSMON_07_N,
2653  BF_SYSMON_08_P => BF_SYSMON_08_P,
2654  BF_SYSMON_08_N => BF_SYSMON_08_N,
2655  BF_SYSMON_09_P => BF_SYSMON_09_P,
2656  BF_SYSMON_09_N => BF_SYSMON_09_N,
2657  BF_SYSMON_10_P => BF_SYSMON_10_P,
2658  BF_SYSMON_10_N => BF_SYSMON_10_N,
2659  BF_SYSMON_11_P => BF_SYSMON_11_P,
2660  BF_SYSMON_11_N => BF_SYSMON_11_N,
2661  BF_SYSMON_12_P => BF_SYSMON_12_P,
2662  BF_SYSMON_12_N => BF_SYSMON_12_N,
2663  BF_SYSMON_13_P => BF_SYSMON_13_P,
2664  BF_SYSMON_13_N => BF_SYSMON_13_N,
2665  BF_SYSMON_14_P => BF_SYSMON_14_P,
2666  BF_SYSMON_14_N => BF_SYSMON_14_N,
2667  BF_SYSMON_15_P => BF_SYSMON_15_P,
2668  BF_SYSMON_15_N => BF_SYSMON_15_N,
2669  ncs => ncs,
2670  rd_nwr => OCB_WRITE_B ,
2671  ds => ds,
2672  addr_vme => vme_address(16 downto 1),
2673  data_vme_in => data_vme_going_below ,
2674  data_vme_out => data_vme_from_below_top (1760),
2675  bus_drive => bus_drive_from_below_top (1760));
2676 
2677 
2678  process(buf_clk40)
2679  begin
2680  if rising_edge(buf_clk40) then
2681  if (read_detect_inreg_test='1' or write_detect_inreg_test='1') and read_detect_outreg_test='0' then
2682  test_rw_counter<=test_rw_counter+1;
2683  elsif read_detect_outreg_test='1' then
2684  test_rw_counter<=test_rw_counter-1;
2685  end if;
2686  end if;
2687  end process;
2688 
2689  data_to_vme_test_r<=std_logic_vector(test_rw_counter);
2690 
2691 
2692  vme_outreg_notri_test: entity work.vme_outreg_notri
2693  generic map (
2694  ia_vme => ADDR_REG_RO_test ,
2695  width => 16)
2696  port map (
2697  clk => buf_clk40 ,
2698  ncs => ncs,
2699  rd_nwr => OCB_WRITE_B ,
2700  ds => ds,
2701  addr_vme => vme_address(16 downto 1),
2702  data_vme => data_vme_from_below_top(1600),
2703  bus_drive => bus_drive_from_below_top (1600),
2704  data_to_vme => data_to_vme_test_r ,
2705  read_detect => read_detect_outreg_test);
2706 
2707  --vme_outreg_test: vme_outreg
2708  -- generic map (
2709  -- ia_vme => ADDR_REG_RO_test,
2710  -- width => 16)
2711  -- port map (
2712  -- clk => buf_clk40,
2713  -- addr_vme => vme_address(16 downto 1),
2714  -- ncs => ncs,
2715  -- rd_nwr => OCB_WRITE_B,
2716  -- ds => ds,
2717  -- data_to_vme => data_to_vme_test_r,
2718  -- read_detect => read_detect_outreg_test,
2719  -- data_vme => OCB_D);
2720 
2721 
2722  vme_inreg_notri_test: entity work.vme_inreg_notri
2723  generic map (
2724  ia_vme => ADDR_REG_RW_test ,
2725  width => 16)
2726  port map (
2727  clk => buf_clk40 ,
2728  ncs => ncs,
2729  rd_nwr => OCB_WRITE_B ,
2730  ds => ds,
2731  addr_vme => vme_address(16 downto 1),
2732  data_vme_in => data_vme_going_below ,
2733  data_vme_out => data_vme_from_below_top (1601),
2734  bus_drive => bus_drive_from_below_top (1601),
2735  data_from_vme => data_from_vme_test_rw ,
2736  data_to_vme => data_to_vme_test_rw ,
2737  read_detect => read_detect_inreg_test,
2738  write_detect => write_detect_inreg_test );
2739 
2740  --vme_inreg_test: vme_inreg
2741  -- generic map (
2742  -- ia_vme => ADDR_REG_RW_test,
2743  -- width => 16)
2744  -- port map (
2745  -- clk => buf_clk40,
2746  -- ncs => ncs,
2747  -- rd_nwr => OCB_WRITE_B,
2748  -- ds => ds,
2749  -- data_from_vme => data_from_vme_test_rw,
2750  -- data_to_vme => data_to_vme_test_rw,
2751  -- addr_vme => vme_address(16 downto 1),
2752  -- read_detect => read_detect_inreg_test,
2753  -- write_detect => write_detect_inreg_test,
2754  -- data_vme => OCB_D);
2755  --
2756  data_to_vme_test_rw<=(data_from_vme_test_rw or data_to_vme_test_r);
2757  --
2758  --chipscope_ila_CMX_top_inputmodclk_inst: chipscope_ila_CMX_top_inputmodclk
2759  -- port map (
2760  -- CONTROL => CONTROL0,
2761  -- CLK => buf_clk40,
2762  -- DATA => DATA_chipscope_ila_CMX_top_inputmodclk,
2763  -- TRIG0 => TRIG0_chipscope_ila_CMX_top_inputmodclk);
2764  --
2765  --
2766  --TRIG0_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2767  --TRIG0_chipscope_ila_CMX_top_inputmodclk(33)<=start_playback;
2768  --TRIG0_chipscope_ila_CMX_top_inputmodclk(34)<=dout(0);
2769  --TRIG0_chipscope_ila_CMX_top_inputmodclk(35)<=data_from_RTM(0);
2770  --
2771  --
2772  --DATA_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2773  --
2774  --gen_data_chipscope_ila: for ichannel in numactchan-1 downto 0 generate
2775  --
2776  -- TRIG0_chipscope_ila_CMX_top_inputmodclk(1+ichannel*2)<=PAR_ERROR(ichannel);
2777  -- TRIG0_chipscope_ila_CMX_top_inputmodclk(2+ichannel*2)<=counter_enable_inputmod_sig(ichannel);
2778  --
2779  -- DATA_chipscope_ila_CMX_top_inputmodclk(1+ichannel*98)<=PAR_ERROR(ichannel);
2780  -- DATA_chipscope_ila_CMX_top_inputmodclk(2+ichannel*98)<=counter_enable_inputmod_sig(ichannel);
2781  -- DATA_chipscope_ila_CMX_top_inputmodclk(95+3+ichannel*98 downto 3+ichannel*98)<=DATA96(ichannel);
2782  --
2783  --end generate gen_data_chipscope_ila;
2784  --
2785  --
2786  --
2787  --DATA_chipscope_ila_CMX_top_inputmodclk(1630 downto 1569)<=dout;
2788  --DATA_chipscope_ila_CMX_top_inputmodclk(1734 downto 1631)<=data_from_RTM(103 downto 0);
2789  --DATA_chipscope_ila_CMX_top_inputmodclk(1735)<=start_playback;
2790  --DATA_chipscope_ila_CMX_top_inputmodclk(2375 downto 1736) <= (others=>'0');
2791 
2792 
2793 
2794 
2795  --chipscope_ila_IDELAY_1: chipscope_ila_IDELAY
2796  -- port map (
2797  -- CONTROL => CONTROL1,
2798  -- CLK => buf_clk40,
2799  -- DATA => DATA_chipscope_ila_IDELAY,
2800  -- TRIG0(0) => upload_delays);
2801  --
2802  --gen_chipscpe_data_idelay_ichan: for ichan in numactchan-1 downto 0 generate
2803  -- --no -1 because the clock adds one:
2804  -- gen_chipscpe_data_idelay_ibit: for ibit in numbitsinchan downto 0 generate
2805  -- DATA_chipscope_ila_IDELAY( (ichan*(numbitsinchan+1)+ibit)*5 + 4 downto (ichan*(numbitsinchan+1)+ibit)*5)<=
2806  -- del_register(ichan,ibit);
2807  -- end generate gen_chipscpe_data_idelay_ibit;
2808  --end generate gen_chipscpe_data_idelay_ichan;
2809  --DATA_chipscope_ila_IDELAY(2000)<=upload_delays;
2810 
2811  CMX_delay_generator_inst: CMX_delay_generator
2812  generic map (
2813  start_address => ADDR_REG_RW_IDELAY_BACKPLANE )
2814  port map (
2815  clk40 => buf_clk40 ,
2816  ncs => ncs,
2817  rd_nwr => OCB_WRITE_B ,
2818  ds => ds,
2819  addr_vme => vme_address(16 downto 1),
2820  data_vme_in => data_vme_going_below ,
2821  data_vme_out => data_vme_from_below_top (1602),
2822  bus_drive => bus_drive_from_below_top (1602),
2823  del_register => del_register,
2824  upload_delays => upload_delays);
2825 
2826  --upload_delays<='0';
2827  --del_register<=(others=>(others=>(others=>'0')));
2828 
2829  BCID_counter_inst: BCID_counter
2830  port map (
2831  reset => bc_reset_synced ,
2832  clk_40 => buf_clk40,
2833  BCID_out => BCID_counter_sig ,
2834  ncs => ncs,
2835  rd_nwr => OCB_WRITE_B ,
2836  ds => ds,
2837  addr_vme => vme_address(16 downto 1),
2838  data_vme_in => data_vme_going_below ,
2839  data_vme_out => data_vme_from_below_top (1639),
2840  bus_drive => bus_drive_from_below_top (1639));
2841 
2842 
2843 
2844 
2845  process(buf_clk40)
2846  begin
2847  if rising_edge(buf_clk40) then
2848  start_playback<=start_playback_r1;
2849  start_playback_r1<=BF_TO_FROM_BSPT_0;
2850  end if;
2851  end process;
2852 
2853  CMX_input_inst: CMX_input_module
2854  port map (
2855  P => P,
2856  buf_clk40 => buf_clk40,
2857  buf_clk40_m180o => buf_clk40_m180o,
2858  buf_clk200 => buf_clk200,
2859  pll_locked => pll_locked,
2860  ODATA => DATA96,
2861  ODATA_first_half => ODATA_first_half ,
2862  --ODATA_WORD0 => open,
2863  PAR_ERROR_total => par_err(0),
2864  counter_enable_out => counter_enable_inputmod_sig ,
2865  counter_values => counter_values,
2866  del_register => del_register,
2867  upload_delays => upload_delays,
2868  quiet => quiet,
2869  start_playback => start_playback,
2870  spy_write_inhibit => spy_write_inhibit ,
2871  ncs => ncs,
2872  rd_nwr => OCB_WRITE_B,
2873  ds => ds,
2874  addr_vme => vme_address(16 downto 1),
2875  data_vme_in => data_vme_going_below ,
2876  data_vme_out => data_vme_from_below_top (1603),
2877  bus_drive => bus_drive_from_below_top (1603));
2878 
2879 
2880 
2881  vme_inreg_async_REG_RW_QUIET_FORCE : vme_inreg_notri_async
2882  generic map (
2883  ia_vme => ADDR_REG_RW_QUIET_FORCE ,
2884  width => 16)
2885  port map (
2886  ncs => ncs,
2887  rd_nwr => OCB_WRITE_B,
2888  ds => ds,
2889  addr_vme => vme_address(16 downto 1),
2890  data_vme_in => data_vme_going_below,
2891  data_vme_out => data_vme_from_below_top(1630),
2892  bus_drive => bus_drive_from_below_top (1630),
2893  data_from_vme => data_from_vme_REG_RW_QUIET_FORCE,
2894  data_to_vme => data_to_vme_REG_RW_QUIET_FORCE);
2895 
2896  data_to_vme_REG_RW_QUIET_FORCE<=data_from_vme_REG_RW_QUIET_FORCE;
2897  quiet<=data_from_vme_REG_RW_QUIET_FORCE(1);
2898  force<=data_from_vme_REG_RW_QUIET_FORCE(0);
2899 
2900  CMX_Memory_spy_inhibit_inst: entity work.CMX_Memory_spy_inhibit
2901  port map (
2902  spy_write_inhibit => spy_write_inhibit ,
2903  buf_clk40 => buf_clk40,
2904  ncs => ncs,
2905  rd_nwr => OCB_WRITE_B,
2906  ds => ds,
2907  addr_vme => vme_address(16 downto 1),
2908  data_vme_in => data_vme_going_below,
2909  data_vme_out => data_vme_from_below_top(1761),
2910  bus_drive => bus_drive_from_below_top (1761));
2911 
2912 
2913  gen_REG_RW_JET_THRESHOLD_BLOCK: for i_thr in 1599 downto 0 generate
2914 
2915  vme_inreg_notri_async_REG_RW_JET_THRESHOLD_BLOCK: entity work.vme_inreg_notri_async
2916  generic map (
2917  ia_vme => ADDR_REG_RW_JET_THRESHOLD_BLOCK+2*i_thr,
2918  width => 16)
2919  port map (
2920  ncs => ncs,
2921  rd_nwr => OCB_WRITE_B,
2922  ds => ds,
2923  addr_vme => vme_address(16 downto 1),
2924  data_vme_in => data_vme_going_below,
2925  data_vme_out => data_vme_from_below_top (i_thr),
2926  bus_drive => bus_drive_from_below_top (i_thr),
2927  data_from_vme => data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr),
2928  data_to_vme => data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr));
2929 
2930 
2931  --vme_inreg_async_REG_RW_JET_THRESHOLD_BLOCK: vme_inreg_async
2932  -- generic map (
2933  -- ia_vme => ADDR_REG_RW_JET_THRESHOLD_BLOCK+2*i_thr,
2934  -- width => 16)
2935  -- port map (
2936  -- ncs => ncs,
2937  -- rd_nwr => OCB_WRITE_B,
2938  -- ds => ds,
2939  -- addr_vme => vme_address(16 downto 1),
2940  -- data_vme => OCB_D,
2941  -- data_from_vme => data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr),
2942  -- data_to_vme => data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr));
2943  data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr)<=data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr);
2944  end generate gen_REG_RW_JET_THRESHOLD_BLOCK;
2945 
2946 
2947  thresholds<=data_from_vme_REG_RW_JET_THRESHOLD_BLOCK;
2948 
2949 
2950  decoder_inst: entity work.decoder
2951  port map (
2952  clk40MHz => buf_clk40,
2953  clk40MHz_m90o => buf_clk40_m90o,
2954  clk40MHz_90o => buf_clk40_90o,
2955  clk40MHz_m180o => buf_clk40_m180o,
2956  pll_locked => pll_locked,
2957  datai => DATA96(14 downto 1),
2958  datai_first_half => ODATA_first_half(14 downto 1),
2959  Tobs_to_TOPO => Tobs_to_TOPO,
2960  overflow => overflow,
2961  BCID_in => BCID_counter_sig ,
2962  BCID_delayed => BCID_delayed_decoder ,
2963  counter_inhibit => counter_inhibit,
2964  counter_reset => counter_reset,
2965  ncs => ncs,
2966  rd_nwr => OCB_WRITE_B ,
2967  ds => ds,
2968  addr_vme => vme_address(16 downto 1),
2969  data_vme_out => data_vme_from_below_top (1638),
2970  bus_drive => bus_drive_from_below_top (1638));
2971 
2972 
2973 
2974  adder_top_inst: entity work.adder_top
2975  generic map (
2976  ADDR_REG_RW_PIPELINE_DELAY_LENGTH => ADDR_REG_RW_DELAY_INPUT_DATA_ADDER,
2977  gen_system => '1')
2978  port map (
2979  clk => buf_clk40 ,
2980  thresholds => thresholds(895 downto 0),
2981  datai => DATA96(14 downto 1),
2982  din_cbl => din_cbl,
2983  din_cbla_ro => din_cbla_ro,
2984  din_cblb_ro => din_cblb_ro,
2985  din_cblc_ro => din_cblc_ro,
2986  dout_lcl => dout_lcl,
2987  dout_lcl_ro => dout_lcl_ro,
2988  dout => dout,
2989  dout_ro => dout_ro,
2990  dout_cbla_mux0 => open,
2991  dout_cbla_mux1 => open,
2992  -- vme
2993  ncs => ncs,
2994  rd_nwr => OCB_WRITE_B ,
2995  ds => ds,
2996  addr_vme => vme_address(16 downto 1),
2997  data_vme_in => data_vme_going_below ,
2998  data_vme_out => data_vme_from_below_top (1606),
2999  bus_drive => bus_drive_from_below_top (1606),
3000  par_err => par_err,
3001  force => force,
3002  reset => counter_reset ,
3003  inhibit => counter_inhibit );
3004 
3005 
3006  din_cbl(23 downto 0) <= data_from_RTM(23 downto 0); -- cbl_a (mux0)
3007  din_cbl(47 downto 24) <= data_from_RTM(49 downto 26); -- cbl_a (mux1)
3008  din_cbl(71 downto 48) <= data_from_RTM(75 downto 52); -- cbl_b (mux0)
3009  din_cbl(95 downto 72) <= data_from_RTM(101 downto 78); -- cbl_b (mux1)
3010  din_cbl(119 downto 96) <= data_from_RTM(127 downto 104); -- cbl_c (mux0)
3011  din_cbl(143 downto 120) <= data_from_RTM(153 downto 130); -- cbl_c (mux1)
3012 
3013  din_cbl(144)<=data_from_RTM(25);
3014  din_cbl(145)<=data_from_RTM(51);
3015  din_cbl(146)<=data_from_RTM(77);
3016  din_cbl(147)<=data_from_RTM(103);
3017  din_cbl(148)<=data_from_RTM(129);
3018  din_cbl(149)<=data_from_RTM(155);
3019 
3020  din_cbla_ro <= data_from_RTM(50); -- remote overflow cbla
3021  din_cblb_ro <= data_from_RTM(102); -- remote overflow cblb
3022  din_cblc_ro <= data_from_RTM(154); -- remote overflow cblc
3023 
3024  gen_dummy_loc_vme_bus: for i_dummy in 1640 to 1759 generate
3025  data_vme_from_below_top(i_dummy)<=(others=>'0');
3026  bus_drive_from_below_top(i_dummy)<='0';
3027  end generate gen_dummy_loc_vme_bus;
3028 
3029  CMX_CTP_output_module_inst: entity work.CMX_CTP_output_module
3030  port map (
3031  data => dout,
3032  sdr_data_out => sdr_data_CTP,
3033  buf_clk40 => buf_clk40,
3034  buf_clk40_center => buf_clk40_90o,
3035  buf_clk200 => buf_clk200,
3036  pll_locked => pll_locked,
3037  start_playback => start_playback,
3038  spy_write_inhibit => spy_write_inhibit ,
3039  ncs => ncs,
3040  rd_nwr => OCB_WRITE_B,
3041  ds => ds,
3042  addr_vme => vme_address(16 downto 1),
3043  data_vme_in => data_vme_going_below ,
3044  data_vme_out => data_vme_from_below_top(1631),
3045  bus_drive => bus_drive_from_below_top (1631));
3046 
3047 
3048  CMX_system_cable_input_module_inst: entity work.CMX_system_cable_input_module
3049  port map (
3050  data => data_from_RTM,
3051  parity_error_total => par_err(1),
3052  ddr_data_in => sig_arr_RTM,
3053  buf_clk40 => buf_clk40,
3054  buf_clk40_ds2 => buf_clk40_ds2 ,
3055  pll_locked => pll_locked,
3056  pll_locked_ds2 => pll_locked_ds2,
3057  quiet => quiet,
3058  start_playback => start_playback,
3059  spy_write_inhibit => spy_write_inhibit ,
3060  ncs => ncs,
3061  rd_nwr => OCB_WRITE_B,
3062  ds => ds,
3063  addr_vme => vme_address(16 downto 1),
3064  data_vme_in => data_vme_going_below,
3065  data_vme_out => data_vme_from_below_top (1636),
3066  bus_drive => bus_drive_from_below_top(1636)
3067  );
3068 
3069  --chipscope_ila_LVDS_TX_CTP_RTM_inst: chipscope_ila_LVDS_TX_CTP_RTM
3070  -- port map (
3071  -- CONTROL => CONTROL1,
3072  -- CLK => buf_clk40,
3073  -- DATA(31 downto 0) => sdr_data_out,
3074  -- DATA(63 downto 32) => (others=>'0'),
3075  -- DATA(115 downto 64) => data_RTM,
3076  -- DATA(116) => '0',
3077  -- DATA(117) => '0',
3078  -- TRIG0(0) => '0',
3079  -- TRIG0(1) => '0'
3080  -- );
3081 
3082 
3083 
3084 
3085  CMX_clock_manager_inst: CMX_clock_manager
3086  port map (
3087  I_DS1 => CLK_40MHz08_DSKW_1_BF_LOGIC_DIR,
3088  IB_DS1 => CLK_40MHz08_DSKW_1_BF_LOGIC_CMP,
3089  buf_clk40 => buf_clk40,
3090  buf_clk40_90o => buf_clk40_90o,
3091  buf_clk40_m180o => buf_clk40_m180o,
3092  buf_clk40_m90o => buf_clk40_m90o,
3093  buf_clk320 => buf_clk320,
3094  buf_clk160 => buf_clk160,
3095  buf_clk200 => buf_clk200,
3096  pll_locked => pll_locked,
3097  I_DS2 => CLK_40MHz08_DSKW_2_BF_LOGIC_DIR,
3098  IB_DS2 => CLK_40MHz08_DSKW_2_BF_LOGIC_CMP,
3099  buf_clk40_ds2 => buf_clk40_ds2,
3100  pll_locked_ds2 => pll_locked_ds2,
3101  ncs => ncs,
3102  rd_nwr => OCB_WRITE_B ,
3103  ds => ds,
3104  addr_vme => vme_address(16 downto 1),
3105  data_vme_in => data_vme_going_below ,
3106  data_vme_out => data_vme_from_below_top (1762),
3107  bus_drive => bus_drive_from_below_top (1762));
3108 
3109 
3110  CMX_CP_Topo_Encoder_inst: entity work.CMX_CP_Topo_Encoder
3111  port map (
3112  Tobs_to_TOPO => Tobs_to_TOPO,
3113  overflow => overflow,
3114  send_align_out => send_align,
3115  Data_out => indata_Topo_TX );
3116 
3117 
3118  Topo_Data_TX_inst: entity work.Topo_Data_TX
3119  port map (
3120  MGTREFCLK_PAD_N_IN => MGTREFCLK_PAD_N_IN,
3121  MGTREFCLK_PAD_P_IN => MGTREFCLK_PAD_P_IN,
3122  GTXTXRESET_IN => GTXTXRESET_IN,
3123  GTXRXRESET_IN => GTXRXRESET_IN,
3124  GTX_TX_READY_OUT => GTX_TX_READY_OUT ,
3125  GTX_RX_READY_OUT => GTX_RX_READY_OUT ,
3126  RXN_IN => RXN_IN,
3127  RXP_IN => RXP_IN,
3128  TXN_OUT => TXN_OUT,
3129  TXP_OUT => TXP_OUT,
3130  clk40 => buf_clk40_m90o,
3131  clk320 => buf_clk320,
3132  pll_locked => pll_locked,
3133  send_align => send_align,
3134  BCID => BCID_delayed_decoder,
3135  indata => indata_Topo_TX,
3136  ext_trigger => '0',
3137  ncs => ncs,
3138  rd_nwr => OCB_WRITE_B,
3139  ds => ds,
3140  addr_vme => vme_address(16 downto 1),
3141  data_vme_in => data_vme_going_below,
3142  data_vme_out => data_vme_from_below_top(1604),
3143  bus_drive => bus_drive_from_below_top (1604));
3144 
3145 
3146 
3147  --Topo_Data_TX_inst: Topo_Data_TX
3148  -- port map (
3149  -- MGTREFCLK_PAD_N_IN => MGTREFCLK_PAD_N_IN,
3150  -- MGTREFCLK_PAD_P_IN => MGTREFCLK_PAD_P_IN,
3151  -- GTXTXRESET_IN => GTXTXRESET_IN,
3152  -- GTXRXRESET_IN => GTXRXRESET_IN,
3153  -- GTX_TX_READY_OUT => GTX_TX_READY_OUT,
3154  -- GTX_RX_READY_OUT => GTX_RX_READY_OUT,
3155  -- RXN_IN => RXN_IN,
3156  -- RXP_IN => RXP_IN,
3157  -- TXN_OUT => TXN_OUT,
3158  -- TXP_OUT => TXP_OUT,
3159  -- clk40 => buf_clk40,
3160  -- clk320 => buf_clk320,
3161  -- pll_locked => pll_locked,
3162  -- send_align => send_align,
3163  -- BCID => BCID_counter_sig,
3164  -- indata => indata_Topo_TX,
3165  -- ext_trigger => BF_TO_TP_DAQ_SLINK_RETURN_DIR,
3166  -- ncs => ncs,
3167  -- rd_nwr => OCB_WRITE_B,
3168  -- ds => ds,
3169  -- addr_vme => vme_address(16 downto 1),
3170  -- data_vme => OCB_D);
3171 
3172 
3173 
3174 -- --for the test make a fake data to send topo
3175 -- gen_indata_counter_fiber: for i_fiber in 0 to 23 generate
3176 -- process(buf_clk40)
3177 -- begin
3178 -- if rising_edge(buf_clk40) then
3179 -- if counter_fake_data_Topo_TX(i_fiber)(11 downto 0)=to_unsigned(0,12) then
3180 -- send_align(i_fiber)<='1';
3181 -- else
3182 -- send_align(i_fiber)<='0';
3183 -- end if;
3184 -- counter_fake_data_Topo_TX(i_fiber)<=counter_fake_data_Topo_TX(i_fiber)+1;
3185 -- end if;
3186 -- end process;
3187 --
3188 --
3189 -- PRNG_LFSR_BIG_inst: PRNG_LFSR_BIG
3190 -- port map (
3191 -- clk => buf_clk40,
3192 -- rst => (not pll_locked),
3193 -- DATA_PRN => DATA_PRN(i_fiber) );
3194 --
3195 -- --counter repeated twice for the msb words
3196 -- gen_data_counter_word: for i_word in 6 to 7 generate
3197 -- indata_Topo_TX(128*(i_fiber)+16*(i_word)+15 downto 128*(i_fiber)+16*(i_word))<=std_logic_vector(counter_fake_data_Topo_TX(i_fiber));
3198 -- end generate gen_data_counter_word;
3199 --
3200 -- --then the 8 msb of the counter
3201 -- indata_Topo_TX(128*(i_fiber)+95 downto 128*(i_fiber)+88) <= std_logic_vector(counter_fake_data_Topo_TX(i_fiber)(15 downto 8));
3202 --
3203 -- --then the mgt number
3204 -- indata_Topo_TX(128*(i_fiber)+87 downto 128*(i_fiber)+80) <= std_logic_vector(to_unsigned(i_fiber,8));
3205 --
3206 -- --then the pseudo random number
3207 -- indata_Topo_TX(128*(i_fiber)+79 downto 128*(i_fiber)+16) <= DATA_PRN(i_fiber);
3208 --
3209 --
3210 -- --last 12 bits must be 0, four msb bits of the last word have the counter again
3211 -- indata_Topo_TX(128*(i_fiber)+15 downto 128*(i_fiber)+12) <= std_logic_vector(counter_fake_data_Topo_TX(i_fiber)(15 downto 12));
3212 -- indata_Topo_TX(128*(i_fiber)+11 downto 128*(i_fiber))<=(others=>'0');
3213 --
3214 -- end generate gen_indata_counter_fiber;
3215 
3216 
3217  vme_inreg_REG_RW_TOPOTR_GTX_RESET: vme_inreg_notri_async
3218  generic map (
3219  ia_vme => ADDR_REG_RW_TOPOTR_GTX_RESET ,
3220  width => 16)
3221  port map (
3222  ncs => ncs,
3223  rd_nwr => OCB_WRITE_B ,
3224  ds => ds,
3225  addr_vme => vme_address (16 downto 1),
3226  data_vme_in => data_vme_going_below,
3227  data_vme_out => data_vme_from_below_top(1634),
3228  bus_drive => bus_drive_from_below_top (1634),
3229  data_from_vme => data_from_vme_REG_RW_TOPOTR_GTX_RESET,
3230  data_to_vme => data_to_vme_REG_RW_TOPOTR_GTX_RESET
3231  );
3232 
3233  GTXTXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(1);
3234  GTXRXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(0);
3235 
3236  data_to_vme_REG_RW_TOPOTR_GTX_RESET<=data_from_vme_REG_RW_TOPOTR_GTX_RESET;
3237 
3238 
3239  vme_outreg_async_REG_RO_TOPOTR_GTX_STATUS : vme_outreg_notri_async
3240  generic map (
3241  ia_vme => ADDR_REG_RO_TOPOTR_GTX_STATUS ,
3242  width => 16)
3243  port map (
3244  ncs => ncs,
3245  rd_nwr => OCB_WRITE_B,
3246  ds => ds,
3247  addr_vme => vme_address(16 downto 1),
3248  data_vme => data_vme_from_below_top(1635),
3249  bus_drive => bus_drive_from_below_top (1635),
3250  data_to_vme => data_to_vme_REG_RO_TOPOTR_GTX_STATUS );
3251 
3252  data_to_vme_REG_RO_TOPOTR_GTX_STATUS(1)<=GTX_TX_READY_OUT;
3253  data_to_vme_REG_RO_TOPOTR_GTX_STATUS(0)<=GTX_RX_READY_OUT;
3254 
3255  data_to_vme_REG_RO_TOPOTR_GTX_STATUS(15 downto 2)<=(others=>'0');
3256 
3257  -- sfp
3258 
3259 
3260  SFP_Data_TXRX_TX_SFP_DAQ: SFP_Data_TXRX
3261  generic map(
3262  direction => '1',
3263  clock_source => '1')
3264  port map (
3265  MGTREFCLK => MGTREFCLK_Q118 ,
3266  gtx_reset => gtx_reset_SFP_DAQ ,
3267  local_pll_lock_out => local_pll_lock_out_SFP_DAQ ,
3268  GTX_TX_READY_OUT => GTX_TX_READY_OUT_TX_SFP_DAQ ,
3269  GTX_RX_READY_OUT => GTX_RX_READY_OUT_TX_SFP_DAQ ,
3270  PLLLKDET_diag => PLLLKDET_diag_TX_SFP_DAQ ,
3271  local_gtx_reset_diag => local_gtx_reset_diag_TX_SFP_DAQ ,
3272  local_mmcm_reset_diag => local_mmcm_reset_diag_TX_SFP_DAQ ,
3273  GTXTEST_diag => GTXTEST_diag_TX_SFP_DAQ ,
3274  RXN_IN => RXN_IN_TX_SFP_DAQ ,
3275  RXP_IN => RXP_IN_TX_SFP_DAQ ,
3276  TXN_OUT => TXN_OUT_TX_SFP_DAQ,
3277  TXP_OUT => TXP_OUT_TX_SFP_DAQ,
3278  clk40_out => clk40_out_TX_SFP_DAQ,
3279  clk120_out => clk120_out_TX_SFP_DAQ,
3280  clk40_in => clk40_in_TX_SFP_DAQ,
3281  clk120_in => clk120_in_TX_SFP_DAQ,
3282  indata => indata_TX_SFP_DAQ ,
3283  odata => odata_TX_SFP_DAQ ,
3284  TXPREEMPHASIS_IN => TXPREEMPHASIS_IN_TX_SFP_DAQ ,
3285  TXPOSTEMPHASIS_IN => TXPOSTEMPHASIS_IN_TX_SFP_DAQ ,
3286  TXDIFFCTRL_IN => TXDIFFCTRL_IN_TX_SFP_DAQ ,
3287  RXEQMIX_IN => RXEQMIX_IN_TX_SFP_DAQ,
3288  DFECLKDLYADJ => DFECLKDLYADJ_TX_SFP_DAQ ,
3289  DFECLKDLYADJMON => DFECLKDLYADJMON_TX_SFP_DAQ ,
3290  DFEDLYOVRD => DFEDLYOVRD_TX_SFP_DAQ,
3291  DFEEYEDACMON => DFEEYEDACMON_TX_SFP_DAQ ,
3292  DFESENSCAL => DFESENSCAL_TX_SFP_DAQ,
3293  DFETAP1 => DFETAP1_TX_SFP_DAQ,
3294  DFETAP1MONITOR => DFETAP1MONITOR_TX_SFP_DAQ ,
3295  DFETAP2 => DFETAP2_TX_SFP_DAQ,
3296  DFETAP2MONITOR => DFETAP2MONITOR_TX_SFP_DAQ ,
3297  DFETAP3 => DFETAP3_TX_SFP_DAQ,
3298  DFETAP3MONITOR => DFETAP3MONITOR_TX_SFP_DAQ ,
3299  DFETAP4 => DFETAP4_TX_SFP_DAQ,
3300  DFETAP4MONITOR => DFETAP4MONITOR_TX_SFP_DAQ ,
3301  DFETAPOVRD => DFETAPOVRD_TX_SFP_DAQ);
3302 
3303 
3304  SFP_Data_TXRX_TX_SFP_ROI: SFP_Data_TXRX
3305  generic map(
3306  direction => '1',
3307  clock_source => '0')
3308  port map (
3309  MGTREFCLK => MGTREFCLK_Q118 ,
3310  gtx_reset => gtx_reset_SFP_ROI ,
3311  local_pll_lock_out => local_pll_lock_out_SFP_ROI ,
3312  GTX_TX_READY_OUT => GTX_TX_READY_OUT_TX_SFP_ROI ,
3313  GTX_RX_READY_OUT => GTX_RX_READY_OUT_TX_SFP_ROI ,
3314  PLLLKDET_diag => PLLLKDET_diag_TX_SFP_ROI ,
3315  local_gtx_reset_diag => local_gtx_reset_diag_TX_SFP_ROI ,
3316  local_mmcm_reset_diag => local_mmcm_reset_diag_TX_SFP_ROI ,
3317  GTXTEST_diag => GTXTEST_diag_TX_SFP_ROI ,
3318  RXN_IN => RXN_IN_TX_SFP_ROI ,
3319  RXP_IN => RXP_IN_TX_SFP_ROI ,
3320  TXN_OUT => TXN_OUT_TX_SFP_ROI,
3321  TXP_OUT => TXP_OUT_TX_SFP_ROI,
3322  clk40_out => clk40_out_TX_SFP_ROI,
3323  clk120_out => clk120_out_TX_SFP_ROI,
3324  clk40_in => clk40_in_TX_SFP_ROI,
3325  clk120_in => clk120_in_TX_SFP_ROI,
3326  indata => indata_TX_SFP_ROI ,
3327  odata => odata_TX_SFP_ROI ,
3328  TXPREEMPHASIS_IN => TXPREEMPHASIS_IN_TX_SFP_ROI ,
3329  TXPOSTEMPHASIS_IN => TXPOSTEMPHASIS_IN_TX_SFP_ROI ,
3330  TXDIFFCTRL_IN => TXDIFFCTRL_IN_TX_SFP_ROI ,
3331  RXEQMIX_IN => RXEQMIX_IN_TX_SFP_ROI,
3332  DFECLKDLYADJ => DFECLKDLYADJ_TX_SFP_ROI ,
3333  DFECLKDLYADJMON => DFECLKDLYADJMON_TX_SFP_ROI ,
3334  DFEDLYOVRD => DFEDLYOVRD_TX_SFP_ROI,
3335  DFEEYEDACMON => DFEEYEDACMON_TX_SFP_ROI ,
3336  DFESENSCAL => DFESENSCAL_TX_SFP_ROI,
3337  DFETAP1 => DFETAP1_TX_SFP_ROI,
3338  DFETAP1MONITOR => DFETAP1MONITOR_TX_SFP_ROI ,
3339  DFETAP2 => DFETAP2_TX_SFP_ROI,
3340  DFETAP2MONITOR => DFETAP2MONITOR_TX_SFP_ROI ,
3341  DFETAP3 => DFETAP3_TX_SFP_ROI,
3342  DFETAP3MONITOR => DFETAP3MONITOR_TX_SFP_ROI ,
3343  DFETAP4 => DFETAP4_TX_SFP_ROI,
3344  DFETAP4MONITOR => DFETAP4MONITOR_TX_SFP_ROI ,
3345  DFETAPOVRD => DFETAPOVRD_TX_SFP_ROI);
3346 
3347 -- glink interface
3348 
3349 
3350  glink: glink_interface
3351  port map (
3352  CLK_40MHz => clk40_in_TX_SFP_ROI, -- clk40MHz
3353  CLK_120MHz => clk120_in_TX_SFP_ROI , -- clk120MHz
3354  RST => reset_daq , --not pll_locked, --reset(0), -- reset
3355  DAQ_IN => daq_in, -- Input data (DAQ)
3356  ROI_IN => roi_in, -- Input data (ROI)
3357  DAQ_DAV => daq_dav, -- Control (DAQ)
3358  ROI_DAV => roi_dav, -- Control (ROI)
3359  DAQ_BYTE => roi_byte, -- Output Byte (DAQ)
3360  ROI_BYTE => daq_byte, -- Output Byte (ROI)
3361  DAQ_ENCODED_DIAG => daq_encoded_diag,
3362  daq_byte_out => daq_byte_out,
3363  byte_pos_out => byte_pos_out,
3364  word_sel_out => word_sel_out,
3365  readout_rst_out => readout_rst_out
3366 
3367 
3368 
3369  ); -- daq_encoded_DIAG
3370 
3371  MGT_118_clk0_ibufds_i : IBUFDS_GTXE1
3372  port map
3373  (
3374  O => MGTREFCLK_Q118,
3375  ODIV2 => open,
3376  CEB => '0',
3377  I => CLK_120MHz000_XTAL_1_BF_TRNCV_DIR,
3378  IB => CLK_120MHz000_XTAL_1_BF_TRNCV_CMP
3379  );
3380 
3381  BF_DAQ_DATA_OUT_DIR<=TXP_OUT_TX_SFP_DAQ;
3382  BF_DAQ_DATA_OUT_CMP<=TXN_OUT_TX_SFP_DAQ;
3383 
3384  BF_ROI_DATA_OUT_DIR<=TXP_OUT_TX_SFP_ROI;
3385  BF_ROI_DATA_OUT_CMP<=TXN_OUT_TX_SFP_ROI;
3386 
3387  clk40_in_TX_SFP_ROI<=clk40_out_TX_SFP_DAQ;
3388  clk120_in_TX_SFP_ROI<=clk120_out_TX_SFP_DAQ;
3389 
3390  indata_TX_SFP_DAQ<=daq_byte; -- from GLINK emulator
3391  indata_TX_SFP_ROI<=roi_byte; -- from GLINK emulator;
3392 
3393 -- Reset control
3394 
3395  --vio_data_i : diagn_module_vio
3396  -- port map(
3397  -- CONTROL => control1,
3398  -- ASYNC_OUT => reset);
3399 
3400  vme_inreg_async_REG_RW_DAQ_ROI_RESET : vme_inreg_notri_async
3401  generic map (
3402  ia_vme => ADDR_REG_RW_DAQ_ROI_RESET ,
3403  width => 16)
3404  port map (
3405  ncs => ncs,
3406  rd_nwr => OCB_WRITE_B,
3407  ds => ds,
3408  addr_vme => vme_address(16 downto 1),
3409  data_vme_in => data_vme_going_below,
3410  data_vme_out => data_vme_from_below_top(1629),
3411  bus_drive => bus_drive_from_below_top (1629),
3412  data_from_vme => data_from_vme_REG_RW_DAQ_ROI_RESET,
3413  data_to_vme => data_to_vme_REG_RW_DAQ_ROI_RESET);
3414 
3415  reset_daq<=data_from_vme_REG_RW_DAQ_ROI_RESET(0);
3416  data_to_vme_REG_RW_DAQ_ROI_RESET<=data_from_vme_REG_RW_DAQ_ROI_RESET;
3417 
3418  vme_inreg_async_REG_RW_DAQ_ROI_GTX_RESET : vme_inreg_notri_async
3419  generic map (
3420  ia_vme => ADDR_REG_RW_DAQ_ROI_GTX_RESET ,
3421  width => 16)
3422  port map (
3423  ncs => ncs,
3424  rd_nwr => OCB_WRITE_B,
3425  ds => ds,
3426  addr_vme => vme_address(16 downto 1),
3427  data_vme_in => data_vme_going_below,
3428  data_vme_out => data_vme_from_below_top(1633),
3429  bus_drive => bus_drive_from_below_top (1633),
3430  data_from_vme => data_from_vme_REG_RW_DAQ_ROI_GTX_RESET,
3431  data_to_vme => data_to_vme_REG_RW_DAQ_ROI_GTX_RESET);
3432 
3433  gtx_reset_SFP_DAQ<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(0);
3434  gtx_reset_SFP_ROI<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(1);
3435  data_to_vme_REG_RW_DAQ_ROI_GTX_RESET<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET;
3436 
3437 
3438  vme_outreg_async_REG_RO_DAQ_ROI_STATUS : vme_outreg_notri_async
3439  generic map (
3440  ia_vme => ADDR_REG_RO_DAQ_ROI_STATUS ,
3441  width => 16)
3442  port map (
3443  ncs => ncs,
3444  rd_nwr => OCB_WRITE_B,
3445  ds => ds,
3446  addr_vme => vme_address(16 downto 1),
3447  data_vme => data_vme_from_below_top(1632),
3448  bus_drive => bus_drive_from_below_top (1632),
3449  data_to_vme => data_to_vme_REG_RO_DAQ_ROI_STATUS );
3450 
3451  data_to_vme_REG_RO_DAQ_ROI_STATUS(0)<=local_pll_lock_out_SFP_DAQ;
3452  data_to_vme_REG_RO_DAQ_ROI_STATUS(1)<=GTX_TX_READY_OUT_TX_SFP_DAQ;
3453  data_to_vme_REG_RO_DAQ_ROI_STATUS(2)<=GTX_RX_READY_OUT_TX_SFP_DAQ;
3454  data_to_vme_REG_RO_DAQ_ROI_STATUS(3)<=PLLLKDET_diag_TX_SFP_DAQ;
3455  data_to_vme_REG_RO_DAQ_ROI_STATUS(4)<=local_pll_lock_out_SFP_ROI;
3456  data_to_vme_REG_RO_DAQ_ROI_STATUS(5)<=GTX_TX_READY_OUT_TX_SFP_ROI;
3457  data_to_vme_REG_RO_DAQ_ROI_STATUS(6)<=GTX_RX_READY_OUT_TX_SFP_ROI;
3458  data_to_vme_REG_RO_DAQ_ROI_STATUS(7)<=PLLLKDET_diag_TX_SFP_ROI;
3459  data_to_vme_REG_RO_DAQ_ROI_STATUS(8)<=readout_rst_out;
3460 
3461  data_to_vme_REG_RO_DAQ_ROI_STATUS(15 downto 9) <= (others=>'0');
3462 
3463 
3464 -- -- Chipscope analyzer
3465 -- chipscope_icon_u2_c3_inst: chipscope_icon_u2_c3
3466 -- port map (
3467 -- CONTROL0 => CONTROL0,
3468 -- CONTROL1 => CONTROL1,
3469 -- CONTROL2 => CONTROL2
3470 -- );
3471 --
3472 -- ila_daq_glink : glink_chipscope_analyzer
3473 -- port map (
3474 -- CONTROL => control0,
3475 -- CLK => clk40_in_TX_SFP_ROI,
3476 -- DATA => data_ila_daq,
3477 -- TRIG0 => trig_ila_daq);
3478 --
3479 -- ila_glink_encoder : glink_chipscope_analyzer_encoder
3480 -- port map (
3481 -- CONTROL => control1,
3482 -- CLK => clk120_in_TX_SFP_ROI,
3483 -- DATA => data_ila_encoder,
3484 -- TRIG0 => trig_ila_encoder);
3485 --
3486 -- ila_gtx_start: entity work.glink_chipscope_analyzer_gtx_start
3487 -- port map (
3488 -- CONTROL => CONTROL2,
3489 -- CLK => MGTREFCLK_Q118,
3490 -- DATA => data_ila_gtx_start,
3491 -- TRIG0 => trig_ila_gtx_start);
3492 --
3493 -- data_ila_daq <= daq_in &
3494 -- daq_encoded_diag &
3495 -- pll_locked &
3496 -- local_pll_lock_out_SFP_DAQ &
3497 -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3498 -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3499 -- local_pll_lock_out_SFP_ROI &
3500 -- GTX_TX_READY_OUT_TX_SFP_ROI &
3501 -- GTX_RX_READY_OUT_TX_SFP_ROI &
3502 -- reset_daq &
3503 -- l1a_synced &
3504 -- daq_dav ;
3505 --
3506 --
3507 -- trig_ila_daq <= daq_encoded_diag &
3508 -- pll_locked &
3509 -- local_pll_lock_out_SFP_DAQ &
3510 -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3511 -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3512 -- local_pll_lock_out_SFP_ROI &
3513 -- GTX_TX_READY_OUT_TX_SFP_ROI &
3514 -- GTX_RX_READY_OUT_TX_SFP_ROI &
3515 -- reset_daq &
3516 -- l1a_synced &
3517 -- daq_dav ;
3518 --
3519 --
3520 --
3521 -- trig_ila_encoder <= GTX_TX_READY_OUT_TX_SFP_DAQ &
3522 -- reset_daq &
3523 -- l1a_synced &
3524 -- daq_byte &
3525 -- pll_locked;
3526 --
3527 -- data_ila_encoder <= byte_pos_out &
3528 -- word_sel_out &
3529 -- readout_rst_out &
3530 -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3531 -- reset_daq &
3532 -- l1a_synced &
3533 -- daq_byte&
3534 -- pll_locked;
3535 --
3536 -- trig_ila_gtx_start(0)<=pll_locked;
3537 -- trig_ila_gtx_start(1)<=gtx_reset_SFP_DAQ;
3538 -- trig_ila_gtx_start(2)<=gtx_reset_SFP_ROI;
3539 --
3540 --
3541 --
3542 -- data_ila_gtx_start(0)<= pll_locked;
3543 -- data_ila_gtx_start(1)<= gtx_reset_SFP_DAQ;
3544 -- data_ila_gtx_start(2)<= gtx_reset_SFP_ROI;
3545 -- data_ila_gtx_start(3)<= GTX_TX_READY_OUT_TX_SFP_DAQ;
3546 -- data_ila_gtx_start(4)<= PLLLKDET_diag_TX_SFP_DAQ;
3547 -- data_ila_gtx_start(5)<= local_gtx_reset_diag_TX_SFP_DAQ;
3548 -- data_ila_gtx_start(6)<= local_mmcm_reset_diag_TX_SFP_DAQ;
3549 -- data_ila_gtx_start(7)<= GTXTEST_diag_TX_SFP_DAQ;
3550 -- data_ila_gtx_start(8)<= GTX_TX_READY_OUT_TX_SFP_ROI;
3551 -- data_ila_gtx_start(9)<= PLLLKDET_diag_TX_SFP_ROI;
3552 -- data_ila_gtx_start(10)<= local_gtx_reset_diag_TX_SFP_ROI;
3553 -- data_ila_gtx_start(11)<= local_mmcm_reset_diag_TX_SFP_ROI;
3554 -- data_ila_gtx_start(12)<= GTXTEST_diag_TX_SFP_ROI;
3555 
3556 
3557 
3558  process(buf_clk40)
3559  begin
3560  if rising_edge(buf_clk40) then
3561  l1a_synced<=BUF_TTC_L1_ACCEPT_r;
3562  BUF_TTC_L1_ACCEPT_r<=BUF_TTC_L1_ACCEPT;
3563 
3564  bc_reset_synced<=BUF_TTC_BNCH_CNT_RES_r;
3565  BUF_TTC_BNCH_CNT_RES_r<=BUF_TTC_BNCH_CNT_RES;
3566  end if;
3567  end process;
3568 
3569 
3570  daq_i: entity work.daq_glink
3571  port map (
3572  data_in => data_in_daq ,
3573  bc_counter => unsigned(BCID_delayed_daq),
3574  l1a => l1a_synced ,
3575  data_out => daq_in,
3576  dav => daq_dav ,
3577  clk4000 => clk40_out_TX_SFP_DAQ ,
3578  clk4008 => buf_clk40,
3579  reset => reset_daq ,--not pll_locked,
3580  RAM_global_offset => RAM_global_offset ,
3581  RAM_rel_offsets => RAM_rel_offsets,
3582  nslices => nslices
3583  );
3584 
3585  --in this flavor roi and daq have the same behavior
3586  roi_dav<=daq_dav;
3587  roi_in<=daq_in;
3588 
3589  --readout control registers
3590  vme_inreg_async_REG_RW_DAQ_SLICE: entity work.vme_inreg_notri_async
3591  generic map (
3592  ia_vme => ADDR_REG_RW_DAQ_SLICE,
3593  width => 16)
3594  port map (
3595  ncs => ncs,
3596  rd_nwr => OCB_WRITE_B ,
3597  ds => ds,
3598  addr_vme => vme_address(16 downto 1),
3599  data_vme_in => data_vme_going_below ,
3600  data_vme_out => data_vme_from_below_top(1607),
3601  bus_drive => bus_drive_from_below_top (1607),
3602  data_from_vme => data_from_vme_REG_RW_DAQ_SLICE,
3603  data_to_vme => data_to_vme_REG_RW_DAQ_SLICE );
3604 
3605  nslices(1 downto 0) <= unsigned(data_to_vme_REG_RW_DAQ_SLICE(1 downto 0));
3606  nslices(7 downto 2) <= (others=>'0');
3607 
3608  data_to_vme_REG_RW_DAQ_SLICE<=data_from_vme_REG_RW_DAQ_SLICE;
3609 
3610 
3611  vme_inreg_async_REG_DAQ_RAM_OFFSET: entity work.vme_inreg_notri_async
3612  generic map (
3613  ia_vme => ADDR_REG_RW_DAQ_RAM_OFFSET ,
3614  width => 16)
3615  port map (
3616  ncs => ncs,
3617  rd_nwr => OCB_WRITE_B ,
3618  ds => ds,
3619  addr_vme => vme_address(16 downto 1),
3620  data_vme_in => data_vme_going_below ,
3621  data_vme_out => data_vme_from_below_top(1608),
3622  bus_drive => bus_drive_from_below_top (1608),
3623  data_from_vme => data_from_vme_REG_RW_DAQ_RAM_OFFSET,
3624  data_to_vme => data_to_vme_REG_RW_DAQ_RAM_OFFSET);
3625 
3626  data_to_vme_REG_RW_DAQ_RAM_OFFSET<=data_from_vme_REG_RW_DAQ_RAM_OFFSET;
3627  RAM_global_offset <= unsigned(data_from_vme_REG_RW_DAQ_RAM_OFFSET(7 downto 0));
3628 
3629 
3630  rel_offset_gen: for i_row in 1 to 19 generate
3631  vme_inreg_async_REG_DAQ_RAM_OFFSET: entity work.vme_inreg_notri_async
3632  generic map (
3633  ia_vme => (ADDR_REG_RW_DAQ_RAM_RELATIVE_OFFSET+2*(i_row-1)),
3634  width => 16)
3635  port map (
3636  ncs => ncs,
3637  rd_nwr => OCB_WRITE_B ,
3638  ds => ds,
3639  data_vme_in => data_vme_going_below ,
3640  addr_vme => vme_address(16 downto 1),
3641  data_vme_out => data_vme_from_below_top(1609+i_row),
3642  bus_drive => bus_drive_from_below_top (1609+i_row),
3643  data_from_vme => data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1),
3644  data_to_vme => data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1));
3645 
3646  data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)<=data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1);
3647  RAM_rel_offsets(i_row-1)<=unsigned(data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)(7 downto 0));
3648  end generate rel_offset_gen;
3649 
3650 
3651 
3652  daq_collector_i: entity work.daq_collector
3653  port map (
3654  clk => buf_clk40 ,
3655  datai => DATA96(14 downto 1),
3656  din_cbl => din_cbl,
3657  din_cbla_ro => din_cbla_ro,
3658  din_cblb_ro => din_cblb_ro,
3659  din_cblc_ro => din_cblc_ro,
3660  din_lcl => dout_lcl,
3661  din_lcl_ro => dout_lcl_ro,
3662  dout => dout,
3663  dout_ro => dout_ro,
3664  data_in_daq => data_in_daq,
3665  BCID_in => BCID_counter_sig ,
3666  BCID_delayed => BCID_delayed_daq );
3667 
3668 
3669  CMX_rate_counter_inhibit_inst: entity work.CMX_rate_counter_inhibit
3670  port map (
3671  counter_inhibit => counter_inhibit,
3672  counter_reset => counter_reset,
3673  buf_clk40 => buf_clk40,
3674  ncs => ncs,
3675  rd_nwr => OCB_WRITE_B ,
3676  ds => ds,
3677  addr_vme => vme_address(16 downto 1),
3678  data_vme_in => data_vme_going_below,
3679  data_vme_out => data_vme_from_below_top(1637),
3680  bus_drive => bus_drive_from_below_top (1637));
3681 
3682 
3683 
3684 
3685 end Behavioral;
3686 
CMX_top_Base.P6_5
in P6_5std_logic
Definition: CMX_top_Base.vhd:246
CMX_top_Base.BF_DOUT_CTP_41
out BF_DOUT_CTP_41std_logic
Definition: CMX_top_Base.vhd:581
CMX_top_Base.P3_21
in P3_21std_logic
Definition: CMX_top_Base.vhd:187
CMX_top_Base.P9_17
in P9_17std_logic
Definition: CMX_top_Base.vhd:333
CMX_top_Base.BF_SYSMON_13_N
in BF_SYSMON_13_NSTD_LOGIC
Definition: CMX_top_Base.vhd:84
CMX_top_Base.P1_7
in P1_7std_logic
Definition: CMX_top_Base.vhd:123
Topo_Data_TX.TXN_OUT
out TXN_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:36
CMX_top_Base.BF_SYSMON_14_P
in BF_SYSMON_14_PSTD_LOGIC
Definition: CMX_top_Base.vhd:85
CMX_top_Base.P12_4
in P12_4std_logic
Definition: CMX_top_Base.vhd:395
CMX_top_Base.P3_6
in P3_6std_logic
Definition: CMX_top_Base.vhd:172
CMX_top_Base.Behavioral.ncs
std_logic ncs
Definition: CMX_top_Base.vhd:793
CMX_top_Base.P11_20
in P11_20std_logic
Definition: CMX_top_Base.vhd:386
CMX_top_Base.D_CBL_48_B
out D_CBL_48_Bstd_logic
Definition: CMX_top_Base.vhd:656
CMX_top_Base.P6_24
in P6_24std_logic
Definition: CMX_top_Base.vhd:265
CMX_top_Base.BF_DOUT_CTP_01
out BF_DOUT_CTP_01std_logic
Definition: CMX_top_Base.vhd:539
CMX_top_Base.P13_17
in P13_17std_logic
Definition: CMX_top_Base.vhd:433
CMX_top_Base.P10_16
in P10_16std_logic
Definition: CMX_top_Base.vhd:357
CMX_top_Base.P14_21
in P14_21std_logic
Definition: CMX_top_Base.vhd:462
CMX_top_Base.P11_18
in P11_18std_logic
Definition: CMX_top_Base.vhd:384
CMX_top_Base.BF_TO_FROM_BSPT_2
out BF_TO_FROM_BSPT_2std_logic
Definition: CMX_top_Base.vhd:530
vme_inreg.read_detect
out read_detectstd_logic
Definition: vme_inreg_rtl.vhd:38
CMX_top_Base.BF_DAQ_DATA_OUT_CMP
out BF_DAQ_DATA_OUT_CMPstd_logic
Definition: CMX_top_Base.vhd:705
CMX_top_Base.OCB_A10
in OCB_A10std_logic
Definition: CMX_top_Base.vhd:41
CMX_top_Base.CLK_120MHz000_XTAL_1_BF_TRNCV_DIR
in CLK_120MHz000_XTAL_1_BF_TRNCV_DIRstd_logic
Definition: CMX_top_Base.vhd:702
CMX_top_Base.P11_7
in P11_7std_logic
Definition: CMX_top_Base.vhd:373
CMX_top_Base.P14_13
in P14_13std_logic
Definition: CMX_top_Base.vhd:454
CMX_top_Base.D_CBL_74_B
out D_CBL_74_Bstd_logic
Definition: CMX_top_Base.vhd:684
CMX_top_Base.P1_21
in P1_21std_logic
Definition: CMX_top_Base.vhd:137
sys_monitor.BF_SYSMON_09_P
in BF_SYSMON_09_PSTD_LOGIC
Definition: sys_monitor.vhd:38
CMX_top_Base.P7_20
in P7_20std_logic
Definition: CMX_top_Base.vhd:286
CMX_top_Base.D_CBL_32_B
out D_CBL_32_Bstd_logic
Definition: CMX_top_Base.vhd:640
CMX_delay_generator.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_delay_generator.vhd:39
CMX_top_Base.BF_TO_TP_ROI_SLINK_RETURN_CMP
in BF_TO_TP_ROI_SLINK_RETURN_CMPstd_logic
Definition: CMX_top_Base.vhd:696
vme_outreg_notri.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl_notri.vhd:16
CMX_top_Base.BF_TO_FROM_BSPT_3
out BF_TO_FROM_BSPT_3std_logic
Definition: CMX_top_Base.vhd:531
CMX_top_Base.MP1_F11_QUAD_111_TRN_1_CMP
out MP1_F11_QUAD_111_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:720
CMX_top_Base.P5_10
in P5_10std_logic
Definition: CMX_top_Base.vhd:226
daq_collector.din_cbla_ro
in din_cbla_roT_SL
Definition: daq_collector.vhd:28
CMX_top_Base.P7_10
in P7_10std_logic
Definition: CMX_top_Base.vhd:276
CMX_top_Base.P2_14
in P2_14std_logic
Definition: CMX_top_Base.vhd:155
CMX_top_Base.P1_2
in P1_2std_logic
Definition: CMX_top_Base.vhd:118
CMX_top_Base.P9_3
in P9_3std_logic
Definition: CMX_top_Base.vhd:319
daq_collector.dout
in doutT_SLV62
Definition: daq_collector.vhd:30
CMX_input_module.ODATA
out ODATAarr_4Xword (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:33
CMX_top_Base.P1_10
in P1_10std_logic
Definition: CMX_top_Base.vhd:126
CMX_top_Base.D_CBL_42_B
out D_CBL_42_Bstd_logic
Definition: CMX_top_Base.vhd:650
CMX_top_Base.P1_19
in P1_19std_logic
Definition: CMX_top_Base.vhd:135
CMX_top_Base.P4_12
in P4_12std_logic
Definition: CMX_top_Base.vhd:203
CMX_top_Base.P7_5
in P7_5std_logic
Definition: CMX_top_Base.vhd:271
vme_inreg.write_detect
out write_detectstd_logic
Definition: vme_inreg_rtl.vhd:39
CMX_top_Base.P12_6
in P12_6std_logic
Definition: CMX_top_Base.vhd:397
CMX_input_module.ds
in dsstd_logic
Definition: CMX_input_module.vhd:59
CMX_top_Base.Behavioral.read_detect_inreg_test
std_logic read_detect_inreg_test
Definition: CMX_top_Base.vhd:936
vme_outreg.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl.vhd:24
CMX_top_Base.BF_LED_REQ_4
out BF_LED_REQ_4std_logic
Definition: CMX_top_Base.vhd:527
CMX_top_Base.P8_24
in P8_24std_logic
Definition: CMX_top_Base.vhd:315
CMX_top_Base.OCB_A19
in OCB_A19std_logic
Definition: CMX_top_Base.vhd:50
vme_outreg.clk
in clkstd_logic
Definition: vme_outreg_rtl.vhd:21
CMX_BASE_VME_BSPT.n_write
in n_writestd_logic
Definition: cmx_base_vme_bspt.vhd:29
CMX_top_Base.BF_TO_FROM_BSPT_0
in BF_TO_FROM_BSPT_0std_logic
Definition: CMX_top_Base.vhd:528
CMX_clock_manager
Definition: CMX_clock_manager.vhd:27
CMX_top_Base.D_CBL_17_B
out D_CBL_17_Bstd_logic
Definition: CMX_top_Base.vhd:623
CMX_top_Base.P7_18
in P7_18std_logic
Definition: CMX_top_Base.vhd:284
vme_inreg_notri.read_detect
out read_detectstd_logic
Definition: vme_inreg_rtl_notri.vhd:39
CMX_top_Base.P6_15
in P6_15std_logic
Definition: CMX_top_Base.vhd:256
CMX_top_Base.BF_DOUT_CTP_61
out BF_DOUT_CTP_61std_logic
Definition: CMX_top_Base.vhd:601
vme_outreg_notri_async.ncs
in ncsstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:22
CMX_top_Base.P3_14
in P3_14std_logic
Definition: CMX_top_Base.vhd:180
CMX_input_module.PAR_ERROR_total
out PAR_ERROR_totalstd_logic
Definition: CMX_input_module.vhd:39
CMX_Memory_spy_inhibit
Definition: CMX_Memory_spy_inhibit.vhd:37
CMX_top_Base.P4_21
in P4_21std_logic
Definition: CMX_top_Base.vhd:212
daq_collector.data_in_daq
out data_in_daqarr_96 (19 downto 0)
Definition: daq_collector.vhd:32
CMX_top_Base.OCB_A21
in OCB_A21std_logic
Definition: CMX_top_Base.vhd:52
adder_top
Definition: adder_top_vs.vhd:28
CMX_top_Base.P1_11
in P1_11std_logic
Definition: CMX_top_Base.vhd:127
CMX_top_Base.D_CBL_64_B
out D_CBL_64_Bstd_logic
Definition: CMX_top_Base.vhd:674
CMX_top_Base.P5_13
in P5_13std_logic
Definition: CMX_top_Base.vhd:229
CMX_top_Base.P6_19
in P6_19std_logic
Definition: CMX_top_Base.vhd:260
vme_inreg_notri_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:29
sys_monitor.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: sys_monitor.vhd:58
CMX_top_Base.BF_DOUT_CTP_34
out BF_DOUT_CTP_34std_logic
Definition: CMX_top_Base.vhd:574
Topo_Data_TX.MGTREFCLK_PAD_N_IN
in MGTREFCLK_PAD_N_INstd_logic_vector (num_GTX_groups - 1 downto 0)
Definition: Topo_Data_TX.vhd:27
CMX_top_Base.P15_5
in P15_5std_logic
Definition: CMX_top_Base.vhd:471
CMX_top_Base.P5_6
in P5_6std_logic
Definition: CMX_top_Base.vhd:222
CMX_top_Base.P9_10
in P9_10std_logic
Definition: CMX_top_Base.vhd:326
CMX_top_Base.MP1_F04_QUAD_112_TRN_0_DIR
out MP1_F04_QUAD_112_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:725
vme_inreg.data_vme
inout data_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl.vhd:32
CMX_system_cable_input_module.start_playback
in start_playbackstd_logic
Definition: CMX_system_cable_input_module.vhd:40
CMX_top_Base.BF_DOUT_CTP_32
out BF_DOUT_CTP_32std_logic
Definition: CMX_top_Base.vhd:572
CMX_CTP_output_module.buf_clk200
in buf_clk200std_logic
Definition: CMX_CTP_output_module.vhd:38
CMX_system_cable_input_module.parity_error_total
out parity_error_totalstd_logic
Definition: CMX_system_cable_input_module.vhd:33
daq_glink.data_in
in data_inarr_96 (19 downto 0)
Definition: daq_glink.vhd:24
adder_top.din_cbl
in din_cblT_SLV65
Definition: adder_top_vs.vhd:38
CMX_top_Base.D_CBL_81_B
out D_CBL_81_Bstd_logic
Definition: CMX_top_Base.vhd:633
CMX_top_Base.P11_3
in P11_3std_logic
Definition: CMX_top_Base.vhd:369
CMX_version.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_version.vhd:26
CMX_top_Base.P6_4
in P6_4std_logic
Definition: CMX_top_Base.vhd:245
decoder.Tobs_to_TOPO
out Tobs_to_TOPOcopy_arr_TOB
Definition: jet_decoder.vhd:49
CMX_top_Base.P9_7
in P9_7std_logic
Definition: CMX_top_Base.vhd:323
adder_top.ds
in dsstd_logic
Definition: adder_top_vs.vhd:51
CMX_top_Base.P9_12
in P9_12std_logic
Definition: CMX_top_Base.vhd:328
CMX_top_Base.P13_18
in P13_18std_logic
Definition: CMX_top_Base.vhd:434
decoder.datai_first_half
in datai_first_halfarr_2Xword (max_jems - 1 downto 0)
Definition: jet_decoder.vhd:48
CMX_top_Base.D_CBL_67_B
out D_CBL_67_Bstd_logic
Definition: CMX_top_Base.vhd:677
CMX_top_Base.P7_9
in P7_9std_logic
Definition: CMX_top_Base.vhd:275
CMX_top_Base.MP1_F07_QUAD_110_TRN_2_DIR
out MP1_F07_QUAD_110_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:713
CMX_top_Base.P0_6
in P0_6std_logic
Definition: CMX_top_Base.vhd:97
CMX_top_Base.P6_1
in P6_1std_logic
Definition: CMX_top_Base.vhd:242
CMX_top_Base.P10_5
in P10_5std_logic
Definition: CMX_top_Base.vhd:346
CMX_top_Base.P1_4
in P1_4std_logic
Definition: CMX_top_Base.vhd:120
sys_monitor.rd_nwr
in rd_nwrstd_logic
Definition: sys_monitor.vhd:54
vme_outreg_notri_async.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:27
CMX_top_Base.P13_20
in P13_20std_logic
Definition: CMX_top_Base.vhd:436
CMX_top_Base.D_CBL_24_B
in D_CBL_24_Bstd_logic
Definition: CMX_top_Base.vhd:630
CMX_top_Base.D_CBL_28_B
out D_CBL_28_Bstd_logic
Definition: CMX_top_Base.vhd:636
decoder.clk40MHz_90o
in clk40MHz_90ostd_logic
Definition: jet_decoder.vhd:44
CMX_top_Base.BF_TO_FROM_BSPT_6
out BF_TO_FROM_BSPT_6std_logic
Definition: CMX_top_Base.vhd:534
vme_inreg_notri.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:33
SFP_Data_TXRX.local_gtx_reset_diag
out local_gtx_reset_diagstd_logic
Definition: SFP_TXRX.vhd:39
CMX_top_Base.P8_19
in P8_19std_logic
Definition: CMX_top_Base.vhd:310
SFP_Data_TXRX.DFETAP2MONITOR
out DFETAP2MONITORstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:64
CMX_top_Base.P6_16
in P6_16std_logic
Definition: CMX_top_Base.vhd:257
decoder.counter_inhibit
in counter_inhibitstd_logic
Definition: jet_decoder.vhd:61
CMX_top_Base.BF_LED_REQ_1
out BF_LED_REQ_1std_logic
Definition: CMX_top_Base.vhd:524
CMX_top_Base.MP2_F01_QUAD_113_TRN_0_CMP
out MP2_F01_QUAD_113_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:734
vme_outreg.ds
in dsstd_logic
Definition: vme_outreg_rtl.vhd:25
CMX_top_Base.P11_0
in P11_0std_logic
Definition: CMX_top_Base.vhd:366
CMX_top_Base.P5_21
in P5_21std_logic
Definition: CMX_top_Base.vhd:237
CMX_Memory_spy_inhibit.bus_drive
out bus_drivestd_logic
Definition: CMX_Memory_spy_inhibit.vhd:48
Topo_Data_TX.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:56
CMX_top_Base.BF_DEBUG_2
out BF_DEBUG_2std_logic
Definition: CMX_top_Base.vhd:508
CMX_top_Base.P5_8
in P5_8std_logic
Definition: CMX_top_Base.vhd:224
CMX_cable_clocked_80Mbps_input_module.data
out datastd_logic_vector ((numbits_in_cable_connector * 2) - 1 downto 0)
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:26
CMX_top_Base.BF_DOUT_CTP_21
out BF_DOUT_CTP_21std_logic
Definition: CMX_top_Base.vhd:559
CMX_top_Base.P7_21
in P7_21std_logic
Definition: CMX_top_Base.vhd:287
CMX_clock_manager.buf_clk160
out buf_clk160std_logic
Definition: CMX_clock_manager.vhd:37
SFP_Data_TXRX
Definition: SFP_TXRX.vhd:21
CMX_system_cable_input_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_system_cable_input_module.vhd:47
CMX_top_Base.MP1_F10_QUAD_111_TRN_2_DIR
out MP1_F10_QUAD_111_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:721
CMX_top_Base.D_CBL_79_B
out D_CBL_79_Bstd_logic
Definition: CMX_top_Base.vhd:689
CMX_top_Base.P1_8
in P1_8std_logic
Definition: CMX_top_Base.vhd:124
vme_outreg.read_detect
out read_detectstd_logic
Definition: vme_outreg_rtl.vhd:31
CMX_top_Base.D_CBL_59_B
out D_CBL_59_Bstd_logic
Definition: CMX_top_Base.vhd:669
CMX_top_Base.P6_0
in P6_0std_logic
Definition: CMX_top_Base.vhd:241
CMX_top_Base.Behavioral.data_to_vme_test_rw
std_logic_vector (15 downto 0) data_to_vme_test_rw
Definition: CMX_top_Base.vhd:935
CMX_top_Base.BF_DOUT_CTP_46
out BF_DOUT_CTP_46std_logic
Definition: CMX_top_Base.vhd:586
daq_collector.clk
in clkT_SL
Definition: daq_collector.vhd:24
CMX_Memory_spy_inhibit.rd_nwr
in rd_nwrstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:43
CMX_top_Base.P2_18
in P2_18std_logic
Definition: CMX_top_Base.vhd:159
CMX_top_Base.P10_23
in P10_23std_logic
Definition: CMX_top_Base.vhd:364
CMX_top_Base.D_CBL_38_B
out D_CBL_38_Bstd_logic
Definition: CMX_top_Base.vhd:646
CMX_CTP_output_module.start_playback
in start_playbackstd_logic
Definition: CMX_CTP_output_module.vhd:40
CMX_delay_generator.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_delay_generator.vhd:37
SFP_Data_TXRX.DFETAP4
in DFETAP4std_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:67
CMX_CTP_output_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_CTP_output_module.vhd:44
CMX_CTP_output_module
Definition: CMX_CTP_output_module.vhd:27
sys_monitor.BF_SYSMON_03_N
in BF_SYSMON_03_NSTD_LOGIC
Definition: sys_monitor.vhd:31
CMX_top_Base.P11_8
in P11_8std_logic
Definition: CMX_top_Base.vhd:374
CMX_top_Base.BF_DOUT_CTP_04
out BF_DOUT_CTP_04std_logic
Definition: CMX_top_Base.vhd:542
CMX_top_Base.P2_15
in P2_15std_logic
Definition: CMX_top_Base.vhd:156
CMX_top_Base.OCB_A09
in OCB_A09std_logic
Definition: CMX_top_Base.vhd:40
SFP_Data_TXRX.TXN_OUT
out TXN_OUTstd_logic
Definition: SFP_TXRX.vhd:44
CMX_input_module.counter_enable_out
out counter_enable_outstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:41
CMX_top_Base.P8_9
in P8_9std_logic
Definition: CMX_top_Base.vhd:300
sys_monitor.BF_SYSMON_10_P
in BF_SYSMON_10_PSTD_LOGIC
Definition: sys_monitor.vhd:40
CMX_top_Base.BF_DOUT_CTP_65
out BF_DOUT_CTP_65std_logic
Definition: CMX_top_Base.vhd:604
CMX_top_Base.P3_11
in P3_11std_logic
Definition: CMX_top_Base.vhd:177
CMX_top_Base.P11_1
in P11_1std_logic
Definition: CMX_top_Base.vhd:367
CMX_top_Base.BF_DOUT_CTP_55
out BF_DOUT_CTP_55std_logic
Definition: CMX_top_Base.vhd:595
sys_monitor.BF_SYSMON_13_N
in BF_SYSMON_13_NSTD_LOGIC
Definition: sys_monitor.vhd:47
CMX_top_Base.P11_23
in P11_23std_logic
Definition: CMX_top_Base.vhd:389
CMX_input_module.upload_delays
in upload_delaysstd_logic
Definition: CMX_input_module.vhd:45
CMX_top_Base.Behavioral.data_vme_up_top
std_logic_vector (15 downto 0) data_vme_up_top
Definition: CMX_top_Base.vhd:866
CMX_top_Base.P0_8
in P0_8std_logic
Definition: CMX_top_Base.vhd:99
CMX_top_Base.P9_6
in P9_6std_logic
Definition: CMX_top_Base.vhd:322
CMX_top_Base.P4_20
in P4_20std_logic
Definition: CMX_top_Base.vhd:211
vme_inreg_notri.ncs
in ncsstd_logic
Definition: vme_inreg_rtl_notri.vhd:27
CMX_cable_clocked_80Mbps_input_module
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:22
CMX_top_Base.P12_12
in P12_12std_logic
Definition: CMX_top_Base.vhd:403
CMX_top_Base.BF_SYSMON_13_P
in BF_SYSMON_13_PSTD_LOGIC
Definition: CMX_top_Base.vhd:83
CMX_top_Base.BF_DOUT_CTP_19
out BF_DOUT_CTP_19std_logic
Definition: CMX_top_Base.vhd:557
CMX_system_cable_input_module.quiet
in quietstd_logic
Definition: CMX_system_cable_input_module.vhd:39
sys_monitor.BF_SYSMON_12_P
in BF_SYSMON_12_PSTD_LOGIC
Definition: sys_monitor.vhd:44
CMX_top_Base.P1_16
in P1_16std_logic
Definition: CMX_top_Base.vhd:132
SFP_Data_TXRX.TXDIFFCTRL_IN
in TXDIFFCTRL_INstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:54
CMX_top_Base.OCB_A14
in OCB_A14std_logic
Definition: CMX_top_Base.vhd:45
CMX_top_Base.P3_23
in P3_23std_logic
Definition: CMX_top_Base.vhd:189
CMX_top_Base.OCB_DS_B
in OCB_DS_Bstd_logic
Definition: CMX_top_Base.vhd:56
CMX_top_Base.OCB_A11
in OCB_A11std_logic
Definition: CMX_top_Base.vhd:42
CMX_top_Base.P6_21
in P6_21std_logic
Definition: CMX_top_Base.vhd:262
adder_top.dout_cbla_mux0
out dout_cbla_mux0std_logic_vector (33 downto 0)
Definition: adder_top_vs.vhd:44
CMX_input_module.buf_clk40_m180o
in buf_clk40_m180ostd_logic
Definition: CMX_input_module.vhd:29
CMX_top_Base.BF_DOUT_CTP_14
out BF_DOUT_CTP_14std_logic
Definition: CMX_top_Base.vhd:552
CMX_top_Base.BF_DOUT_CTP_47
out BF_DOUT_CTP_47std_logic
Definition: CMX_top_Base.vhd:587
CMX_top_Base.D_CBL_39_B
in D_CBL_39_Bstd_logic
Definition: CMX_top_Base.vhd:647
CMX_rate_counter_inhibit.buf_clk40
in buf_clk40std_logic
Definition: CMX_rate_counter_inhibit.vhd:33
CMX_input_module
Definition: CMX_input_module.vhd:25
CMX_top_Base.P4_18
in P4_18std_logic
Definition: CMX_top_Base.vhd:209
adder_top.dout_lcl
out dout_lclstd_logic_vector (59 downto 0)
Definition: adder_top_vs.vhd:40
CMX_top_Base.P9_2
in P9_2std_logic
Definition: CMX_top_Base.vhd:318
CMX_top_Base.BF_SYSMON_01_N
in BF_SYSMON_01_NSTD_LOGIC
Definition: CMX_top_Base.vhd:66
vme_outreg_notri_async.width
widthinteger :=16
Definition: vme_outreg_rtl_notri_async.vhd:19
vme_main_hub.data_vme
inout data_vmestd_logic_vector (15 downto 0)
the tri-stated port
Definition: vme_main_hub.vhd:23
CMX_top_Base.P4_14
in P4_14std_logic
Definition: CMX_top_Base.vhd:205
CMX_top_Base.D_CBL_27_B
out D_CBL_27_Bstd_logic
Definition: CMX_top_Base.vhd:635
CMX_top_Base.P10_18
in P10_18std_logic
Definition: CMX_top_Base.vhd:359
CMX_input_module.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:61
CMX_top_Base.P9_21
in P9_21std_logic
Definition: CMX_top_Base.vhd:337
CMX_top_Base.BF_SYSMON_10_N
in BF_SYSMON_10_NSTD_LOGIC
Definition: CMX_top_Base.vhd:78
CMX_top_Base.P15_18
in P15_18std_logic
Definition: CMX_top_Base.vhd:484
CMX_top_Base.OCB_A15
in OCB_A15std_logic
Definition: CMX_top_Base.vhd:46
vme_inreg_async.ds
in dsstd_logic
Definition: vme_inreg_async_rtl.vhd:27
CMX_system_cable_input_module.bus_drive
out bus_drivestd_logic
Definition: CMX_system_cable_input_module.vhd:50
CMX_top_Base.P8_21
in P8_21std_logic
Definition: CMX_top_Base.vhd:312
CMX_CTP_output_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_CTP_output_module.vhd:46
CMX_top_Base.P2_1
in P2_1std_logic
Definition: CMX_top_Base.vhd:142
CMX_top_Base.D_CBL_06_B
out D_CBL_06_Bstd_logic
Definition: CMX_top_Base.vhd:612
CMX_top_Base.P14_17
in P14_17std_logic
Definition: CMX_top_Base.vhd:458
CMX_top_Base.work
_library_ workwork
Definition: CMX_top_Base.vhd:15
CMX_top_Base.BF_LED_REQ_2
out BF_LED_REQ_2std_logic
Definition: CMX_top_Base.vhd:525
glink_interface.RST
in RSTstd_logic
Definition: glink_interface.vhd:21
CMX_top_Base.P7_6
in P7_6std_logic
Definition: CMX_top_Base.vhd:272
CMX_top_Base.P9_13
in P9_13std_logic
Definition: CMX_top_Base.vhd:329
CMX_top_Base.BF_TO_TP_DAQ_SLINK_RETURN_DIR
in BF_TO_TP_DAQ_SLINK_RETURN_DIRstd_logic
Definition: CMX_top_Base.vhd:693
CMX_top_Base.P9_18
in P9_18std_logic
Definition: CMX_top_Base.vhd:334
vme_inreg_notri.width
widthinteger :=16
Definition: vme_inreg_rtl_notri.vhd:22
CMX_top_Base.D_CBL_76_B
out D_CBL_76_Bstd_logic
Definition: CMX_top_Base.vhd:686
CMX_top_Base.P10_11
in P10_11std_logic
Definition: CMX_top_Base.vhd:352
CMX_CTP_output_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_CTP_output_module.vhd:41
vme_outreg.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl.vhd:17
CMX_top_Base.MP2_F11_QUAD_114_TRN_1_DIR
out MP2_F11_QUAD_114_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:743
CMX_top_Base.D_CBL_01_B
out D_CBL_01_Bstd_logic
Definition: CMX_top_Base.vhd:607
Topo_Data_TX.rd_nwr
in rd_nwrstd_logic
Definition: Topo_Data_TX.vhd:53
vme_inreg_notri_async.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:34
CMX_top_Base.P14_9
in P14_9std_logic
Definition: CMX_top_Base.vhd:450
vme_inreg.width
widthinteger :=16
Definition: vme_inreg_rtl.vhd:22
daq_glink.RAM_rel_offsets
in RAM_rel_offsetsarr_ctr_8bit (18 downto 0)
Definition: daq_glink.vhd:35
CMX_top_Base.P3_16
in P3_16std_logic
Definition: CMX_top_Base.vhd:182
CMX_top_Base.P4_13
in P4_13std_logic
Definition: CMX_top_Base.vhd:204
CMX_top_Base.BF_LED_REQ_0
out BF_LED_REQ_0std_logic
Definition: CMX_top_Base.vhd:523
CMX_top_Base.P2_6
in P2_6std_logic
Definition: CMX_top_Base.vhd:147
CMX_input_module.P
in Pmat_var (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:27
CMX_top_Base.P13_6
in P13_6std_logic
Definition: CMX_top_Base.vhd:422
CMX_system_cable_input_module.buf_clk40_ds2
in buf_clk40_ds2std_logic
Definition: CMX_system_cable_input_module.vhd:36
CMX_top_Base.BF_DOUT_CTP_00
out BF_DOUT_CTP_00std_logic
Definition: CMX_top_Base.vhd:538
CMX_top_Base.P15_19
in P15_19std_logic
Definition: CMX_top_Base.vhd:485
CMX_version
Definition: CMX_version.vhd:19
BCID_counter.BCID_out
out BCID_outstd_logic_vector (11 downto 0)
Definition: BCID_counter.vhd:32
SFP_Data_TXRX.TXPREEMPHASIS_IN
in TXPREEMPHASIS_INstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:52
vme_inreg_notri_async.width
widthinteger :=16
Definition: vme_inreg_rtl_notri_async.vhd:21
vme_inreg.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl.vhd:35
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_114_DIR
in CLK_320MHz64_LHC_BF_QUAD_114_DIRstd_logic
Definition: CMX_top_Base.vhd:759
CMX_top_Base.Behavioral.vme_local_switch
vme_local_switch
Definition: CMX_top_Base.vhd:847
sys_monitor.BF_SYSMON_03_P
in BF_SYSMON_03_PSTD_LOGIC
Definition: sys_monitor.vhd:30
CMX_top_Base.P6_11
in P6_11std_logic
Definition: CMX_top_Base.vhd:252
CMX_top_Base.P1_20
in P1_20std_logic
Definition: CMX_top_Base.vhd:136
CMX_CP_Topo_Encoder.Data_out
out Data_outstd_logic_vector (TX_indata_length - 1 downto 0)
Definition: CMX_CP_Topo_Encoder.vhd:36
CMX_top_Base.P15_15
in P15_15std_logic
Definition: CMX_top_Base.vhd:481
CMX_top_Base.D_CBL_20_B
in D_CBL_20_Bstd_logic
Definition: CMX_top_Base.vhd:626
CMX_top_Base.P14_6
in P14_6std_logic
Definition: CMX_top_Base.vhd:447
CMX_top_Base.P3_15
in P3_15std_logic
Definition: CMX_top_Base.vhd:181
CMX_top_Base.P5_4
in P5_4std_logic
Definition: CMX_top_Base.vhd:220
CMX_top_Base.P4_17
in P4_17std_logic
Definition: CMX_top_Base.vhd:208
CMX_top_Base.P1_18
in P1_18std_logic
Definition: CMX_top_Base.vhd:134
CMX_top_Base.Behavioral.data_to_vme_outreg_test
std_logic_vector (15 downto 0) data_to_vme_outreg_test
Definition: CMX_top_Base.vhd:813
CMX_top_Base.MP2_F07_QUAD_113_TRN_2_DIR
out MP2_F07_QUAD_113_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:737
CMX_top_Base.RXP_IN
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: CMX_top_Base.vhd:763
CMX_clock_manager.I_DS1
in I_DS1std_logic
Definition: CMX_clock_manager.vhd:30
CMX_delay_generator.del_register
out del_registerdel_register_type
Definition: CMX_delay_generator.vhd:41
CMX_top_Base.P5_2
in P5_2std_logic
Definition: CMX_top_Base.vhd:218
CMX_top_Base.D_CBL_58_B
out D_CBL_58_Bstd_logic
Definition: CMX_top_Base.vhd:668
Topo_Data_TX
Definition: Topo_Data_TX.vhd:23
CMX_top_Base.BF_DOUT_CTP_49
out BF_DOUT_CTP_49std_logic
Definition: CMX_top_Base.vhd:589
CMX_top_Base.P14_10
in P14_10std_logic
Definition: CMX_top_Base.vhd:451
sys_monitor.BF_SYSMON_09_N
in BF_SYSMON_09_NSTD_LOGIC
Definition: sys_monitor.vhd:39
CMX_top_Base.P7_7
in P7_7std_logic
Definition: CMX_top_Base.vhd:273
CMX_top_Base.P12_23
in P12_23std_logic
Definition: CMX_top_Base.vhd:414
CMX_top_Base.P10_15
in P10_15std_logic
Definition: CMX_top_Base.vhd:356
sys_monitor.BF_SYSMON_13_P
in BF_SYSMON_13_PSTD_LOGIC
Definition: sys_monitor.vhd:46
CMX_clock_manager.pll_locked
out pll_lockedstd_logic
Definition: CMX_clock_manager.vhd:39
CMX_top_Base.BF_DEBUG_7
out BF_DEBUG_7std_logic
Definition: CMX_top_Base.vhd:513
CMX_cable_clocked_80Mbps_input_module.numbits_in_cable_connector
numbits_in_cable_connectorinteger
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:24
SFP_Data_TXRX.TXP_OUT
out TXP_OUTstd_logic
Definition: SFP_TXRX.vhd:45
CMX_top_Base.P9_11
in P9_11std_logic
Definition: CMX_top_Base.vhd:327
CMX_top_Base.P0_11
in P0_11std_logic
Definition: CMX_top_Base.vhd:102
CMX_clock_manager.buf_clk320
out buf_clk320std_logic
Definition: CMX_clock_manager.vhd:36
CMX_delay_generator
Definition: CMX_delay_generator.vhd:28
CMX_top_Base.BF_DOUT_CTP_64
out BF_DOUT_CTP_64std_logic
Definition: CMX_top_Base.vhd:570
BCID_counter.ds
in dsstd_logic
Definition: BCID_counter.vhd:36
CMX_top_Base.P7_3
in P7_3std_logic
Definition: CMX_top_Base.vhd:269
CMX_top_Base.MP1_F04_QUAD_112_TRN_0_CMP
out MP1_F04_QUAD_112_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:726
CMX_top_Base.P1_1
in P1_1std_logic
Definition: CMX_top_Base.vhd:117
CMX_system_cable_input_module
Definition: CMX_system_cable_input_module.vhd:28
CMX_top_Base.P5_14
in P5_14std_logic
Definition: CMX_top_Base.vhd:230
CMX_top_Base.P14_7
in P14_7std_logic
Definition: CMX_top_Base.vhd:448
SFP_Data_TXRX.DFECLKDLYADJMON
out DFECLKDLYADJMONstd_logic_vector (5 downto 0)
Definition: SFP_TXRX.vhd:57
CMX_top_Base.P2_19
in P2_19std_logic
Definition: CMX_top_Base.vhd:160
daq_collector.BCID_delayed
out BCID_delayedstd_logic_vector (11 downto 0)
Definition: daq_collector.vhd:34
CMX_top_Base.P8_16
in P8_16std_logic
Definition: CMX_top_Base.vhd:307
CMX_top_Base.BF_SYSMON_15_P
in BF_SYSMON_15_PSTD_LOGIC
Definition: CMX_top_Base.vhd:87
vme_inreg_async
Definition: vme_inreg_async_rtl.vhd:18
CMX_input_module.del_register
in del_registerdel_register_type
Definition: CMX_input_module.vhd:44
CMX_top_Base.D_CBL_21_B
out D_CBL_21_Bstd_logic
Definition: CMX_top_Base.vhd:627
CMX_Memory_spy_inhibit.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_Memory_spy_inhibit.vhd:47
CMX_top_Base.D_CBL_04_B
out D_CBL_04_Bstd_logic
Definition: CMX_top_Base.vhd:610
CMX_top_Base.BF_SYSMON_03_N
in BF_SYSMON_03_NSTD_LOGIC
Definition: CMX_top_Base.vhd:68
vme_inreg_async.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_async_rtl.vhd:33
CMX_top_Base.P12_24
in P12_24std_logic
Definition: CMX_top_Base.vhd:415
CMX_top_Base.BF_ROI_DATA_OUT_DIR
out BF_ROI_DATA_OUT_DIRstd_logic
Definition: CMX_top_Base.vhd:706
CMX_top_Base.P0_18
in P0_18std_logic
Definition: CMX_top_Base.vhd:109
CMX_top_Base.P15_0
in P15_0std_logic
Definition: CMX_top_Base.vhd:466
CMX_top_Base.P2_3
in P2_3std_logic
Definition: CMX_top_Base.vhd:144
CMX_top_Base.P5_24
in P5_24std_logic
Definition: CMX_top_Base.vhd:240
vme_inreg_notri.clk
in clkstd_logic
Definition: vme_inreg_rtl_notri.vhd:25
vme_inreg_async.width
widthinteger :=16
Definition: vme_inreg_async_rtl.vhd:21
CMX_top_Base.P15_2
in P15_2std_logic
Definition: CMX_top_Base.vhd:468
CMX_top_Base.P12_19
in P12_19std_logic
Definition: CMX_top_Base.vhd:410
CMX_top_Base.P8_8
in P8_8std_logic
Definition: CMX_top_Base.vhd:299
decoder.rd_nwr
in rd_nwrstd_logic
Definition: jet_decoder.vhd:65
CMX_top_Base.P6_7
in P6_7std_logic
Definition: CMX_top_Base.vhd:248
CMX_top_Base.P12_0
in P12_0std_logic
Definition: CMX_top_Base.vhd:391
vme_inreg.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl.vhd:21
daq_collector
Definition: daq_collector.vhd:22
SFP_Data_TXRX.clk120_in
in clk120_instd_logic
Definition: SFP_TXRX.vhd:49
daq_collector.din_lcl_ro
in din_lcl_roT_SL
Definition: daq_collector.vhd:29
CMX_top_Base.P12_17
in P12_17std_logic
Definition: CMX_top_Base.vhd:408
sys_monitor.BF_SYSMON_11_N
in BF_SYSMON_11_NSTD_LOGIC
Definition: sys_monitor.vhd:43
CMX_top_Base.P13_9
in P13_9std_logic
Definition: CMX_top_Base.vhd:425
vme_local_switch.data_vme_from_below
in data_vme_from_belowarr_16
--! inputs from local registers and from
Definition: vme_local_switch.vhd:35
glink_interface.CLK_40MHz
in CLK_40MHzstd_logic
Definition: glink_interface.vhd:19
vme_inreg_notri.data_from_vme
out data_from_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri.vhd:36
glink_interface
Definition: glink_interface.vhd:17
daq_collector.din_cbl
in din_cblT_SLV65
Definition: daq_collector.vhd:26
CMX_top_Base.D_CBL_80_B
out D_CBL_80_Bstd_logic
Definition: CMX_top_Base.vhd:690
vme_inreg.ncs
in ncsstd_logic
Definition: vme_inreg_rtl.vhd:27
Topo_Data_TX.ds
in dsstd_logic
Definition: Topo_Data_TX.vhd:54
SFP_Data_TXRX.GTXTEST_diag
out GTXTEST_diagstd_logic
Definition: SFP_TXRX.vhd:41
vme_main_hub.bus_drive_from_below
in bus_drive_from_belowstd_logic
--! a request to drive the outside
Definition: vme_main_hub.vhd:32
CMX_top_Base.P14_12
in P14_12std_logic
Definition: CMX_top_Base.vhd:453
CMX_top_Base
Definition: CMX_top_Base.vhd:23
CMX_version.ncs
in ncsstd_logic
Definition: CMX_version.vhd:22
CMX_version.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_version.vhd:25
CMX_cable_clocked_80Mbps_output_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:29
CMX_top_Base.P12_2
in P12_2std_logic
Definition: CMX_top_Base.vhd:393
CMX_top_Base.D_CBL_29_B
out D_CBL_29_Bstd_logic
Definition: CMX_top_Base.vhd:637
CMX_top_Base.D_CBL_57_B
out D_CBL_57_Bstd_logic
Definition: CMX_top_Base.vhd:667
CMX_top_Base.MP1_F01_QUAD_110_TRN_0_DIR
out MP1_F01_QUAD_110_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:709
sys_monitor.BF_SYSMON_07_N
in BF_SYSMON_07_NSTD_LOGIC
Definition: sys_monitor.vhd:35
CMX_cable_clocked_80Mbps_input_module.forwarded_clock
out forwarded_clockstd_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:28
CMX_top_Base.BF_DOUT_CTP_05
out BF_DOUT_CTP_05std_logic
Definition: CMX_top_Base.vhd:543
CMX_delay_generator.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_delay_generator.vhd:38
CMX_top_Base.BF_DEBUG_4
out BF_DEBUG_4std_logic
Definition: CMX_top_Base.vhd:510
CMX_top_Base.D_CBL_14_B
out D_CBL_14_Bstd_logic
Definition: CMX_top_Base.vhd:620
CMX_clock_manager.ds
in dsstd_logic
Definition: CMX_clock_manager.vhd:46
CMX_top_Base.P10_6
in P10_6std_logic
Definition: CMX_top_Base.vhd:347
CMX_delay_generator.rd_nwr
in rd_nwrstd_logic
Definition: CMX_delay_generator.vhd:35
CMX_cable_clocked_80Mbps_input_module.upload_delays
in upload_delaysstd_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:34
CMX_top_Base.BF_DOUT_CTP_50
out BF_DOUT_CTP_50std_logic
Definition: CMX_top_Base.vhd:590
CMX_top_Base.P1_0
in P1_0std_logic
Definition: CMX_top_Base.vhd:116
CMX_top_Base.P12_9
in P12_9std_logic
Definition: CMX_top_Base.vhd:400
daq_collector.BCID_in
in BCID_instd_logic_vector (11 downto 0)
Definition: daq_collector.vhd:33
CMX_top_Base.P8_20
in P8_20std_logic
Definition: CMX_top_Base.vhd:311
CMX_top_Base.P13_2
in P13_2std_logic
Definition: CMX_top_Base.vhd:418
CMX_top_Base.P13_4
in P13_4std_logic
Definition: CMX_top_Base.vhd:420
CMX_top_Base.P11_6
in P11_6std_logic
Definition: CMX_top_Base.vhd:372
CMX_top_Base.BF_SYSMON_14_N
in BF_SYSMON_14_NSTD_LOGIC
Definition: CMX_top_Base.vhd:86
CMX_CP_Topo_Encoder.Tobs_to_TOPO
in Tobs_to_TOPOcopy_arr_TOB
Definition: CMX_CP_Topo_Encoder.vhd:29
sys_monitor.BF_SYSMON_01_N
in BF_SYSMON_01_NSTD_LOGIC
Definition: sys_monitor.vhd:29
CMX_top_Base.MP2_F04_QUAD_115_TRN_0_CMP
out MP2_F04_QUAD_115_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:750
CMX_CTP_output_module.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_CTP_output_module.vhd:48
vme_outreg_notri.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri.vhd:27
adder_top.dout_lcl_ro
out dout_lcl_roT_SL
Definition: adder_top_vs.vhd:41
CMX_top_Base.P8_1
in P8_1std_logic
Definition: CMX_top_Base.vhd:292
CMX_top_Base.CLK_40MHz08_DSKW_2_BF_LOGIC_CMP
in CLK_40MHz08_DSKW_2_BF_LOGIC_CMPstd_logic
Definition: CMX_top_Base.vhd:500
CMX_top_Base.BF_SYSMON_04_N
in BF_SYSMON_04_NSTD_LOGIC
Definition: CMX_top_Base.vhd:70
CMX_top_Base.P0_15
in P0_15std_logic
Definition: CMX_top_Base.vhd:106
vme_inreg_notri_async.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:30
adder_top.ncs
in ncsstd_logic
Definition: adder_top_vs.vhd:49
CMX_clock_manager.buf_clk40_m180o
out buf_clk40_m180ostd_logic
Definition: CMX_clock_manager.vhd:34
CMX_input_module.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:62
CMX_top_Base.P12_11
in P12_11std_logic
Definition: CMX_top_Base.vhd:402
CMX_top_Base.BF_SYSMON_12_P
in BF_SYSMON_12_PSTD_LOGIC
Definition: CMX_top_Base.vhd:81
CMX_top_Base.MP2_F04_QUAD_115_TRN_0_DIR
out MP2_F04_QUAD_115_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:749
vme_inreg.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl.vhd:31
CMX_top_Base.P3_22
in P3_22std_logic
Definition: CMX_top_Base.vhd:188
sys_monitor.ncs
in ncsstd_logic
Definition: sys_monitor.vhd:53
CMX_top_Base.Behavioral.vme_address
std_logic_vector (23 downto 1) vme_address
Definition: CMX_top_Base.vhd:795
CMX_top_Base.P3_2
in P3_2std_logic
Definition: CMX_top_Base.vhd:168
CMX_top_Base.BF_DOUT_CTP_57
out BF_DOUT_CTP_57std_logic
Definition: CMX_top_Base.vhd:597
CMX_top_Base.P14_1
in P14_1std_logic
Definition: CMX_top_Base.vhd:442
CMX_top_Base.D_CBL_25_B
out D_CBL_25_Bstd_logic
Definition: CMX_top_Base.vhd:631
CMX_top_Base.P10_19
in P10_19std_logic
Definition: CMX_top_Base.vhd:360
CMX_top_Base.Behavioral.sys_monitor
sys_monitor
Definition: CMX_top_Base.vhd:961
CMX_top_Base.BF_DOUT_CTP_42
out BF_DOUT_CTP_42std_logic
Definition: CMX_top_Base.vhd:582
CMX_top_Base.P3_13
in P3_13std_logic
Definition: CMX_top_Base.vhd:179
adder_top.din_cblb_ro
in din_cblb_roT_SL
Definition: adder_top_vs_cp.vhd:39
CMX_top_Base.P15_24
in P15_24std_logic
Definition: CMX_top_Base.vhd:490
CMX_top_Base.P9_22
in P9_22std_logic
Definition: CMX_top_Base.vhd:338
CMX_top_Base.OCB_A12
in OCB_A12std_logic
Definition: CMX_top_Base.vhd:43
CMX_top_Base.P3_4
in P3_4std_logic
Definition: CMX_top_Base.vhd:170
CMX_top_Base.P6_18
in P6_18std_logic
Definition: CMX_top_Base.vhd:259
sys_monitor.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: sys_monitor.vhd:56
CMX_system_cable_input_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_system_cable_input_module.vhd:45
CMX_top_Base.P3_0
in P3_0std_logic
Definition: CMX_top_Base.vhd:166
CMX_clock_manager.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_clock_manager.vhd:48
Topo_Data_TX.send_align
in send_alignstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:41
BCID_counter.rd_nwr
in rd_nwrstd_logic
Definition: BCID_counter.vhd:35
CMX_top_Base.P2_17
in P2_17std_logic
Definition: CMX_top_Base.vhd:158
CMX_top_Base.P2_13
in P2_13std_logic
Definition: CMX_top_Base.vhd:154
adder_top.dout
out doutT_SLV62
Definition: adder_top_vs.vhd:42
CMX_top_Base.OCB_A07
in OCB_A07std_logic
Definition: CMX_top_Base.vhd:38
CMX_top_Base.P10_9
in P10_9std_logic
Definition: CMX_top_Base.vhd:350
CMX_top_Base.BF_DOUT_CTP_51
out BF_DOUT_CTP_51std_logic
Definition: CMX_top_Base.vhd:591
CMX_cable_clocked_80Mbps_output_module
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:22
vme_outreg.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl.vhd:30
CMX_top_Base.D_CBL_33_B
out D_CBL_33_Bstd_logic
Definition: CMX_top_Base.vhd:641
CMX_top_Base.BF_DOUT_CTP_54
out BF_DOUT_CTP_54std_logic
Definition: CMX_top_Base.vhd:594
CMX_top_Base.OCB_A03
in OCB_A03std_logic
Definition: CMX_top_Base.vhd:34
CMX_top_Base.MP1_F02_QUAD_112_TRN_2_DIR
out MP1_F02_QUAD_112_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:729
CMX_top_Base.BF_TO_FROM_BSPT_1
in BF_TO_FROM_BSPT_1std_logic
Definition: CMX_top_Base.vhd:529
CMX_top_Base.OCB_A22
in OCB_A22std_logic
Definition: CMX_top_Base.vhd:53
CMX_top_Base.BF_DOUT_CTP_45
out BF_DOUT_CTP_45std_logic
Definition: CMX_top_Base.vhd:585
sys_monitor.BF_SYSMON_07_P
in BF_SYSMON_07_PSTD_LOGIC
Definition: sys_monitor.vhd:34
CMX_top_Base.P4_22
in P4_22std_logic
Definition: CMX_top_Base.vhd:213
vme_main_hub
Definition: vme_main_hub.vhd:21
Topo_Data_TX.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:57
decoder.BCID_delayed
out BCID_delayedstd_logic_vector (11 downto 0)
Definition: jet_decoder.vhd:57
vme_inreg_notri.write_detect
out write_detectstd_logic
Definition: vme_inreg_rtl_notri.vhd:40
CMX_top_Base.P10_10
in P10_10std_logic
Definition: CMX_top_Base.vhd:351
CMX_top_Base.P12_20
in P12_20std_logic
Definition: CMX_top_Base.vhd:411
CMX_top_Base.P14_8
in P14_8std_logic
Definition: CMX_top_Base.vhd:449
CMX_top_Base.MP2_F08_QUAD_114_TRN_3_DIR
out MP2_F08_QUAD_114_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:747
CMX_top_Base.P0_10
in P0_10std_logic
Definition: CMX_top_Base.vhd:101
CMX_top_Base.P6_14
in P6_14std_logic
Definition: CMX_top_Base.vhd:255
CMX_top_Base.Behavioral.data_vme_from_below_top
arr_16 (1762 downto 0) data_vme_from_below_top
Definition: CMX_top_Base.vhd:863
CMX_top_Base.P5_16
in P5_16std_logic
Definition: CMX_top_Base.vhd:232
CMX_top_Base.P3_8
in P3_8std_logic
Definition: CMX_top_Base.vhd:174
CMX_BASE_VME_BSPT.n_ds0_int
in n_ds0_intstd_logic
Definition: cmx_base_vme_bspt.vhd:28
CMX_top_Base.P13_19
in P13_19std_logic
Definition: CMX_top_Base.vhd:435
CMX_top_Base.BF_DOUT_CTP_60
out BF_DOUT_CTP_60std_logic
Definition: CMX_top_Base.vhd:600
CMX_top_Base.Behavioral.bus_drive_up_top
std_logic bus_drive_up_top
Definition: CMX_top_Base.vhd:865
CMX_top_Base.P4_19
in P4_19std_logic
Definition: CMX_top_Base.vhd:210
vme_inreg_notri_async.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl_notri_async.vhd:20
adder_top.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: adder_top_vs.vhd:54
CMX_top_Base.P4_23
in P4_23std_logic
Definition: CMX_top_Base.vhd:214
SFP_Data_TXRX.gtx_reset
in gtx_resetstd_logic
Definition: SFP_TXRX.vhd:34
CMX_top_Base.BF_DOUT_CTP_07
out BF_DOUT_CTP_07std_logic
Definition: CMX_top_Base.vhd:545
CMX_top_Base.BF_TO_FROM_BSPT_5
out BF_TO_FROM_BSPT_5std_logic
Definition: CMX_top_Base.vhd:533
CMX_top_Base.MP2_F01_QUAD_113_TRN_0_DIR
out MP2_F01_QUAD_113_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:733
CMX_top_Base.P11_2
in P11_2std_logic
Definition: CMX_top_Base.vhd:368
CMX_top_Base.P2_0
in P2_0std_logic
Definition: CMX_top_Base.vhd:141
CMX_top_Base.D_CBL_07_B
out D_CBL_07_Bstd_logic
Definition: CMX_top_Base.vhd:613
vme_outreg
Definition: vme_outreg_rtl.vhd:15
CMX_top_Base.P15_10
in P15_10std_logic
Definition: CMX_top_Base.vhd:476
SFP_Data_TXRX.local_mmcm_reset_diag
out local_mmcm_reset_diagstd_logic
Definition: SFP_TXRX.vhd:40
CMX_Memory_spy_inhibit.ncs
in ncsstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:42
vme_inreg.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl.vhd:36
CMX_top_Base.D_CBL_62_B
out D_CBL_62_Bstd_logic
Definition: CMX_top_Base.vhd:672
CMX_input_module.quiet
in quietstd_logic
Definition: CMX_input_module.vhd:48
CMX_top_Base.P12_3
in P12_3std_logic
Definition: CMX_top_Base.vhd:394
SFP_Data_TXRX.DFETAP3
in DFETAP3std_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:65
CMX_top_Base.P13_24
in P13_24std_logic
Definition: CMX_top_Base.vhd:440
CMX_system_cable_input_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_system_cable_input_module.vhd:35
CMX_top_Base.OCB_A16
in OCB_A16std_logic
Definition: CMX_top_Base.vhd:47
CMX_top_Base.P7_2
in P7_2std_logic
Definition: CMX_top_Base.vhd:268
vme_inreg_notri
Definition: vme_inreg_rtl_notri.vhd:19
CMX_top_Base.P1_5
in P1_5std_logic
Definition: CMX_top_Base.vhd:121
CMX_top_Base.P4_24
in P4_24std_logic
Definition: CMX_top_Base.vhd:215
CMX_top_Base.MP1_F07_QUAD_110_TRN_2_CMP
out MP1_F07_QUAD_110_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:714
CMX_top_Base.Behavioral.start_playback
std_logic start_playback
Definition: CMX_top_Base.vhd:941
vme_inreg_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_async_rtl.vhd:29
CMX_top_Base.P12_8
in P12_8std_logic
Definition: CMX_top_Base.vhd:399
CMX_top_Base.P2_24
in P2_24std_logic
Definition: CMX_top_Base.vhd:165
CMX_top_Base.BF_SYSMON_09_P
in BF_SYSMON_09_PSTD_LOGIC
Definition: CMX_top_Base.vhd:75
vme_inreg_async.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_async_rtl.vhd:20
CMX_top_Base.P4_9
in P4_9std_logic
Definition: CMX_top_Base.vhd:200
SFP_Data_TXRX.DFEEYEDACMON
out DFEEYEDACMONstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:59
CMX_top_Base.Behavioral.ds
std_logic ds
Definition: CMX_top_Base.vhd:792
CMX_top_Base.BF_DOUT_CTP_17
out BF_DOUT_CTP_17std_logic
Definition: CMX_top_Base.vhd:555
vme_outreg_notri.ncs
in ncsstd_logic
Definition: vme_outreg_rtl_notri.vhd:22
CMX_top_Base.D_CBL_09_B
out D_CBL_09_Bstd_logic
Definition: CMX_top_Base.vhd:615
CMX_top_Base.P7_17
in P7_17std_logic
Definition: CMX_top_Base.vhd:283
CMX_top_Base.BF_SYSMON_01_P
in BF_SYSMON_01_PSTD_LOGIC
Definition: CMX_top_Base.vhd:65
CMX_BASE_VME_BSPT.geoadd_0
in geoadd_0std_logic
Definition: cmx_base_vme_bspt.vhd:27
CMX_input_module.start_playback
in start_playbackstd_logic
Definition: CMX_input_module.vhd:51
CMX_top_Base.BF_DOUT_CTP_31
out BF_DOUT_CTP_31std_logic
Definition: CMX_top_Base.vhd:569
CMX_top_Base.BF_DOUT_CTP_38
out BF_DOUT_CTP_38std_logic
Definition: CMX_top_Base.vhd:578
CMX_top_Base.D_CBL_22_B
out D_CBL_22_Bstd_logic
Definition: CMX_top_Base.vhd:628
CMX_top_Base.P1_24
in P1_24std_logic
Definition: CMX_top_Base.vhd:140
CMX_top_Base.BF_DOUT_CTP_37
out BF_DOUT_CTP_37std_logic
Definition: CMX_top_Base.vhd:577
CMX_top_Base.P10_14
in P10_14std_logic
Definition: CMX_top_Base.vhd:355
CMX_top_Base.P1_23
in P1_23std_logic
Definition: CMX_top_Base.vhd:139
CMX_clock_manager.bus_drive
out bus_drivestd_logic
Definition: CMX_clock_manager.vhd:50
CMX_top_Base.MP2_F08_QUAD_114_TRN_3_CMP
out MP2_F08_QUAD_114_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:748
CMX_top_Base.P11_10
in P11_10std_logic
Definition: CMX_top_Base.vhd:376
CMX_CP_Topo_Encoder
Definition: CMX_CP_Topo_Encoder.vhd:27
CMX_top_Base.D_CBL_83_B
out D_CBL_83_Bstd_logic
Definition: CMX_top_Base.vhd:691
CMX_top_Base.P6_3
in P6_3std_logic
Definition: CMX_top_Base.vhd:244
CMX_Memory_spy_inhibit.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_Memory_spy_inhibit.vhd:45
CMX_top_Base.BF_DEBUG_8
out BF_DEBUG_8std_logic
Definition: CMX_top_Base.vhd:514
CMX_cable_clocked_80Mbps_output_module.del_array
in del_arraycable_del_array_type (numbits_in_cable_connector downto 0)
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:34
decoder.ds
in dsstd_logic
Definition: jet_decoder.vhd:66
CMX_top_Base.BF_DOUT_CTP_29
out BF_DOUT_CTP_29std_logic
Definition: CMX_top_Base.vhd:567
SFP_Data_TXRX.DFEDLYOVRD
in DFEDLYOVRDstd_logic
Definition: SFP_TXRX.vhd:58
sys_monitor.ds
in dsstd_logic
Definition: sys_monitor.vhd:55
CMX_top_Base.BF_REQ_CABLE_3_INPUT
out BF_REQ_CABLE_3_INPUTstd_logic
Definition: CMX_top_Base.vhd:522
CMX_top_Base.D_CBL_82_B
out D_CBL_82_Bstd_logic
Definition: CMX_top_Base.vhd:662
CMX_top_Base.BF_DOUT_CTP_35
out BF_DOUT_CTP_35std_logic
Definition: CMX_top_Base.vhd:575
CMX_top_Base.D_CBL_69_B
out D_CBL_69_Bstd_logic
Definition: CMX_top_Base.vhd:679
CMX_top_Base.P3_1
in P3_1std_logic
Definition: CMX_top_Base.vhd:167
daq_glink.nslices
in nslicesunsigned (7 downto 0)
Definition: daq_glink.vhd:36
CMX_top_Base.BF_DOUT_CTP_26
out BF_DOUT_CTP_26std_logic
Definition: CMX_top_Base.vhd:564
CMX_top_Base.P14_4
in P14_4std_logic
Definition: CMX_top_Base.vhd:445
CMX_top_Base.BF_DOUT_CTP_39
out BF_DOUT_CTP_39std_logic
Definition: CMX_top_Base.vhd:579
CMX_top_Base.P4_15
in P4_15std_logic
Definition: CMX_top_Base.vhd:206
Topo_Data_TX.GTX_RX_READY_OUT
out GTX_RX_READY_OUTstd_logic
Definition: Topo_Data_TX.vhd:32
CMX_top_Base.P1_22
in P1_22std_logic
Definition: CMX_top_Base.vhd:138
CMX_top_Base.BF_DOUT_CTP_23
out BF_DOUT_CTP_23std_logic
Definition: CMX_top_Base.vhd:561
CMX_top_Base.P15_23
in P15_23std_logic
Definition: CMX_top_Base.vhd:489
SFP_Data_TXRX.DFECLKDLYADJ
in DFECLKDLYADJstd_logic_vector (5 downto 0)
Definition: SFP_TXRX.vhd:56
CMX_top_Base.P6_8
in P6_8std_logic
Definition: CMX_top_Base.vhd:249
CMX_top_Base.P5_0
in P5_0std_logic
Definition: CMX_top_Base.vhd:216
CMX_top_Base.P1_15
in P1_15std_logic
Definition: CMX_top_Base.vhd:131
CMX_top_Base.MP2_F09_QUAD_114_TRN_0_DIR
out MP2_F09_QUAD_114_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:741
CMX_top_Base.BF_DOUT_CTP_16
out BF_DOUT_CTP_16std_logic
Definition: CMX_top_Base.vhd:554
CMX_input_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_input_module.vhd:31
CMX_clock_manager.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_clock_manager.vhd:49
CMX_top_Base.P4_8
in P4_8std_logic
Definition: CMX_top_Base.vhd:199
CMX_top_Base.P4_4
in P4_4std_logic
Definition: CMX_top_Base.vhd:195
vme_inreg_notri_async.ncs
in ncsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:25
CMX_top_Base.P3_7
in P3_7std_logic
Definition: CMX_top_Base.vhd:173
SFP_Data_TXRX.local_pll_lock_out
out local_pll_lock_outstd_logic
Definition: SFP_TXRX.vhd:35
CMX_rate_counter_inhibit.bus_drive
out bus_drivestd_logic
Definition: CMX_rate_counter_inhibit.vhd:41
CMX_top_Base.P5_11
in P5_11std_logic
Definition: CMX_top_Base.vhd:227
CMX_top_Base.P10_12
in P10_12std_logic
Definition: CMX_top_Base.vhd:353
CMX_top_Base.P5_18
in P5_18std_logic
Definition: CMX_top_Base.vhd:234
CMX_top_Base.D_CBL_03_B
out D_CBL_03_Bstd_logic
Definition: CMX_top_Base.vhd:609
CMX_top_Base.P10_13
in P10_13std_logic
Definition: CMX_top_Base.vhd:354
CMX_top_Base.P0_13
in P0_13std_logic
Definition: CMX_top_Base.vhd:104
CMX_rate_counter_inhibit.ncs
in ncsstd_logic
Definition: CMX_rate_counter_inhibit.vhd:35
CMX_top_Base.P8_3
in P8_3std_logic
Definition: CMX_top_Base.vhd:294
CMX_top_Base.Behavioral.counter_values
std_logic_vector (numactchan - 1 downto 0) counter_values
Definition: CMX_top_Base.vhd:1027
CMX_system_cable_input_module.ddr_data_in
in ddr_data_inarr_RTM (num_RTM_cables - 1 downto 0)
Definition: CMX_system_cable_input_module.vhd:34
adder_top.din_cblc_ro
in din_cblc_roT_SL
Definition: adder_top_vs_cp.vhd:40
adder_top.dout_cbla_mux1
out dout_cbla_mux1std_logic_vector (33 downto 0)
Definition: adder_top_vs.vhd:45
sys_monitor.BF_SYSMON_10_N
in BF_SYSMON_10_NSTD_LOGIC
Definition: sys_monitor.vhd:41
CMX_delay_generator.upload_delays
out upload_delaysstd_logic
Definition: CMX_delay_generator.vhd:42
SFP_Data_TXRX.RXN_IN
in RXN_INstd_logic
Definition: SFP_TXRX.vhd:42
CMX_top_Base.P0_19
in P0_19std_logic
Definition: CMX_top_Base.vhd:110
CMX_top_Base.D_CBL_54_B
out D_CBL_54_Bstd_logic
Definition: CMX_top_Base.vhd:664
CMX_top_Base.P7_0
in P7_0std_logic
Definition: CMX_top_Base.vhd:266
decoder.clk40MHz_m90o
in clk40MHz_m90ostd_logic
Definition: jet_decoder.vhd:43
CMX_top_Base.D_CBL_30_B
out D_CBL_30_Bstd_logic
Definition: CMX_top_Base.vhd:638
CMX_top_Base.P3_10
in P3_10std_logic
Definition: CMX_top_Base.vhd:176
CMX_CTP_output_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_CTP_output_module.vhd:36
CMX_top_Base.P12_7
in P12_7std_logic
Definition: CMX_top_Base.vhd:398
CMX_input_module.counter_values
out counter_valuesstd_logic_vector (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:42
CMX_clock_manager.ncs
in ncsstd_logic
Definition: CMX_clock_manager.vhd:44
CMX_top_Base.P7_15
in P7_15std_logic
Definition: CMX_top_Base.vhd:281
vme_outreg_notri.ds
in dsstd_logic
Definition: vme_outreg_rtl_notri.vhd:24
CMX_top_Base.P3_24
in P3_24std_logic
Definition: CMX_top_Base.vhd:190
CMX_top_Base.P13_22
in P13_22std_logic
Definition: CMX_top_Base.vhd:438
vme_main_hub.data_vme_going_below
out data_vme_going_belowstd_logic_vector (15 downto 0)
Definition: vme_main_hub.vhd:34
CMX_top_Base.P14_5
in P14_5std_logic
Definition: CMX_top_Base.vhd:446
SFP_Data_TXRX.TXPOSTEMPHASIS_IN
in TXPOSTEMPHASIS_INstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:53
CMX_BASE_VME_BSPT.vme_address
in vme_addressstd_logic_vector (23 downto 1)
Definition: cmx_base_vme_bspt.vhd:30
CMX_top_Base.D_CBL_23_B
out D_CBL_23_Bstd_logic
Definition: CMX_top_Base.vhd:629
CMX_top_Base.Behavioral.start_playback_r1
std_logic start_playback_r1
Definition: CMX_top_Base.vhd:941
CMX_top_Base.D_CBL_73_B
out D_CBL_73_Bstd_logic
Definition: CMX_top_Base.vhd:683
BCID_counter.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: BCID_counter.vhd:39
CMX_top_Base.Behavioral.data_vme_going_below
std_logic_vector (15 downto 0) data_vme_going_below
Definition: CMX_top_Base.vhd:867
CMX_top_Base.P0_17
in P0_17std_logic
Definition: CMX_top_Base.vhd:108
vme_outreg_notri.width
widthinteger :=16
Definition: vme_outreg_rtl_notri.vhd:17
CMX_CTP_output_module.ncs
in ncsstd_logic
Definition: CMX_CTP_output_module.vhd:43
CMX_top_Base.P15_20
in P15_20std_logic
Definition: CMX_top_Base.vhd:486
CMX_top_Base.IEEE
_library_ IEEEIEEE
Definition: CMX_top_Base.vhd:8
CMX_top_Base.P4_10
in P4_10std_logic
Definition: CMX_top_Base.vhd:201
vme_inreg_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_async_rtl.vhd:34
vme_outreg_notri.bus_drive
out bus_drivestd_logic
Definition: vme_outreg_rtl_notri.vhd:28
CMX_top_Base.P11_14
in P11_14std_logic
Definition: CMX_top_Base.vhd:380
CMX_delay_generator.bus_drive
out bus_drivestd_logic
Definition: CMX_delay_generator.vhd:40
CMX_top_Base.P2_11
in P2_11std_logic
Definition: CMX_top_Base.vhd:152
CMX_top_Base.MP1_F00_QUAD_112_TRN_3_CMP
out MP1_F00_QUAD_112_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:732
CMX_top_Base.Behavioral.IOB
string IOB
Definition: CMX_top_Base.vhd:774
CMX_cable_clocked_80Mbps_output_module.buf_clk40_center
in buf_clk40_centerstd_logic
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:30
SFP_Data_TXRX.direction
directionstd_logic
Definition: SFP_TXRX.vhd:24
CMX_top_Base.P9_4
in P9_4std_logic
Definition: CMX_top_Base.vhd:320
CMX_top_Base.P5_7
in P5_7std_logic
Definition: CMX_top_Base.vhd:223
CMX_top_Base.Behavioral.quiet
std_logic quiet
Definition: CMX_top_Base.vhd:1033
CMX_top_Base.BF_DOUT_CTP_28
out BF_DOUT_CTP_28std_logic
Definition: CMX_top_Base.vhd:566
vme_inreg_notri_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:35
vme_outreg.width
widthinteger :=16
Definition: vme_outreg_rtl.vhd:18
CMX_top_Base.P7_16
in P7_16std_logic
Definition: CMX_top_Base.vhd:282
Topo_Data_TX.GTXRXRESET_IN
in GTXRXRESET_INstd_logic
Definition: Topo_Data_TX.vhd:30
Topo_Data_TX.MGTREFCLK_PAD_P_IN
in MGTREFCLK_PAD_P_INstd_logic_vector (num_GTX_groups - 1 downto 0)
Definition: Topo_Data_TX.vhd:28
sys_monitor.BF_SYSMON_04_N
in BF_SYSMON_04_NSTD_LOGIC
Definition: sys_monitor.vhd:33
CMX_top_Base.P11_19
in P11_19std_logic
Definition: CMX_top_Base.vhd:385
CMX_top_Base.P0_1
in P0_1std_logic
Definition: CMX_top_Base.vhd:92
CMX_top_Base.P15_12
in P15_12std_logic
Definition: CMX_top_Base.vhd:478
glink_interface.DAQ_DAV
in DAQ_DAVstd_logic
Definition: glink_interface.vhd:24
CMX_version.bus_drive
out bus_drivestd_logic
Definition: CMX_version.vhd:27
vme_outreg_notri_async.bus_drive
out bus_drivestd_logic
Definition: vme_outreg_rtl_notri_async.vhd:28
CMX_top_Base.P2_23
in P2_23std_logic
Definition: CMX_top_Base.vhd:164
CMX_top_Base.D_CBL_08_B
in D_CBL_08_Bstd_logic
Definition: CMX_top_Base.vhd:614
CMX_top_Base.OCB_A05
in OCB_A05std_logic
Definition: CMX_top_Base.vhd:36
CMX_top_Base.P2_22
in P2_22std_logic
Definition: CMX_top_Base.vhd:163
CMX_delay_generator.ds
in dsstd_logic
Definition: CMX_delay_generator.vhd:36
CMX_top_Base.Behavioral.vme_outreg_notri
vme_outreg_notri
Definition: CMX_top_Base.vhd:918
sys_monitor.BF_SYSMON_14_P
in BF_SYSMON_14_PSTD_LOGIC
Definition: sys_monitor.vhd:48
CMX_top_Base.Behavioral.data_from_vme_test_rw
std_logic_vector (15 downto 0) data_from_vme_test_rw
Definition: CMX_top_Base.vhd:934
CMX_top_Base.P2_21
in P2_21std_logic
Definition: CMX_top_Base.vhd:162
CMX_top_Base.P8_15
in P8_15std_logic
Definition: CMX_top_Base.vhd:306
vme_local_switch.data_vme_up
out data_vme_upstd_logic_vector (15 downto 0)
--! connect this to
Definition: vme_local_switch.vhd:24
CMX_CP_Topo_Encoder.send_align_out
out send_align_outstd_logic_vector (num_GTX_groups * num_GTX_per_group - 1 downto 0)
Definition: CMX_CP_Topo_Encoder.vhd:34
CMX_cable_clocked_80Mbps_input_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:30
Topo_Data_TX.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: Topo_Data_TX.vhd:55
CMX_top_Base.P1_17
in P1_17std_logic
Definition: CMX_top_Base.vhd:133
CMX_top_Base.P12_18
in P12_18std_logic
Definition: CMX_top_Base.vhd:409
CMX_top_Base.P8_6
in P8_6std_logic
Definition: CMX_top_Base.vhd:297
CMX_cable_clocked_80Mbps_input_module.del_array
in del_arraycable_del_array_type (numbits_in_cable_connector downto 0)
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:33
CMX_system_cable_input_module.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_system_cable_input_module.vhd:49
CMX_rate_counter_inhibit.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_rate_counter_inhibit.vhd:38
CMX_top_Base.BF_DOUT_CTP_24
out BF_DOUT_CTP_24std_logic
Definition: CMX_top_Base.vhd:562
daq_glink.bc_counter
in bc_counterunsigned (11 downto 0)
Definition: daq_glink.vhd:27
CMX_top_Base.BF_TO_TP_DAQ_SLINK_RETURN_CMP
in BF_TO_TP_DAQ_SLINK_RETURN_CMPstd_logic
Definition: CMX_top_Base.vhd:694
CMX_top_Base.P3_5
in P3_5std_logic
Definition: CMX_top_Base.vhd:171
Topo_Data_TX.GTX_TX_READY_OUT
out GTX_TX_READY_OUTstd_logic
Definition: Topo_Data_TX.vhd:31
CMX_top_Base.P4_6
in P4_6std_logic
Definition: CMX_top_Base.vhd:197
CMX_top_Base.BF_SYSMON_09_N
in BF_SYSMON_09_NSTD_LOGIC
Definition: CMX_top_Base.vhd:76
CMX_top_Base.P14_14
in P14_14std_logic
Definition: CMX_top_Base.vhd:455
CMX_top_Base.D_CBL_78_B
out D_CBL_78_Bstd_logic
Definition: CMX_top_Base.vhd:688
CMX_top_Base.P13_23
in P13_23std_logic
Definition: CMX_top_Base.vhd:439
CMX_top_Base.OCB_A18
in OCB_A18std_logic
Definition: CMX_top_Base.vhd:49
vme_inreg_notri_async.bus_drive
out bus_drivestd_logic
Definition: vme_inreg_rtl_notri_async.vhd:32
CMX_top_Base.BF_DOUT_CTP_53
out BF_DOUT_CTP_53std_logic
Definition: CMX_top_Base.vhd:593
CMX_top_Base.MP2_F02_QUAD_115_TRN_2_DIR
out MP2_F02_QUAD_115_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:753
CMX_top_Base.P15_16
in P15_16std_logic
Definition: CMX_top_Base.vhd:482
adder_top.clk
in clkT_SL
Definition: adder_top_vs.vhd:35
CMX_CTP_output_module.data
in datastd_logic_vector ((numbits_in_CTP_connector * 2) - 1 downto 0)
Definition: CMX_CTP_output_module.vhd:31
CMX_clock_manager.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_clock_manager.vhd:47
CMX_top_Base.P15_14
in P15_14std_logic
Definition: CMX_top_Base.vhd:480
CMX_top_Base.P13_0
in P13_0std_logic
Definition: CMX_top_Base.vhd:416
CMX_top_Base.P7_14
in P7_14std_logic
Definition: CMX_top_Base.vhd:280
BCID_counter.clk_40
in clk_40std_logic
Definition: BCID_counter.vhd:31
CMX_top_Base.BF_REQ_CABLE_1_INPUT
out BF_REQ_CABLE_1_INPUTstd_logic
Definition: CMX_top_Base.vhd:520
CMX_top_Base.P11_16
in P11_16std_logic
Definition: CMX_top_Base.vhd:382
CMX_top_Base.Behavioral.read_detect_outreg_test
std_logic read_detect_outreg_test
Definition: CMX_top_Base.vhd:812
CMX_top_Base.OCB_A17
in OCB_A17std_logic
Definition: CMX_top_Base.vhd:48
CMX_top_Base.Behavioral.del_register
del_register_type del_register
Definition: CMX_top_Base.vhd:1028
CMX_top_Base.OCB_A23
in OCB_A23std_logic
Definition: CMX_top_Base.vhd:54
CMX_top_Base.OCB_A01
in OCB_A01std_logic
Definition: CMX_top_Base.vhd:32
vme_outreg_notri_async.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:26
CMX_top_Base.MP2_F09_QUAD_114_TRN_0_CMP
out MP2_F09_QUAD_114_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:742
CMX_top_Base.P9_20
in P9_20std_logic
Definition: CMX_top_Base.vhd:336
CMX_top_Base.P0_7
in P0_7std_logic
Definition: CMX_top_Base.vhd:98
daq_glink.clk4000
in clk4000std_logic
Definition: daq_glink.vhd:31
sys_monitor.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: sys_monitor.vhd:57
CMX_top_Base.D_CBL_15_B
out D_CBL_15_Bstd_logic
Definition: CMX_top_Base.vhd:621
CMX_top_Base.P0_22
in P0_22std_logic
Definition: CMX_top_Base.vhd:113
SFP_Data_TXRX.clk120_out
out clk120_outstd_logic
Definition: SFP_TXRX.vhd:47
CMX_top_Base.P14_20
in P14_20std_logic
Definition: CMX_top_Base.vhd:461
CMX_top_Base.CLK_120MHz000_XTAL_1_BF_TRNCV_CMP
in CLK_120MHz000_XTAL_1_BF_TRNCV_CMPstd_logic
Definition: CMX_top_Base.vhd:703
CMX_top_Base.P8_13
in P8_13std_logic
Definition: CMX_top_Base.vhd:304
CMX_system_cable_input_module.ncs
in ncsstd_logic
Definition: CMX_system_cable_input_module.vhd:44
CMX_top_Base.BF_DOUT_CTP_18
out BF_DOUT_CTP_18std_logic
Definition: CMX_top_Base.vhd:556
CMX_top_Base.BF_DOUT_CTP_06
out BF_DOUT_CTP_06std_logic
Definition: CMX_top_Base.vhd:544
vme_inreg.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl.vhd:28
CMX_cable_clocked_80Mbps_output_module.ddr_data_out
out ddr_data_outstd_logic_vector (numbits_in_cable_connector downto 0)
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:27
CMX_delay_generator.clk40
in clk40std_logic
Definition: CMX_delay_generator.vhd:33
CMX_top_Base.BF_DOUT_CTP_27
out BF_DOUT_CTP_27std_logic
Definition: CMX_top_Base.vhd:565
CMX_top_Base.BF_DOUT_CTP_43
out BF_DOUT_CTP_43std_logic
Definition: CMX_top_Base.vhd:583
CMX_clock_manager.buf_clk200
out buf_clk200std_logic
Definition: CMX_clock_manager.vhd:38
CMX_top_Base.MP2_F03_QUAD_113_TRN_1_DIR
out MP2_F03_QUAD_113_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:735
CMX_top_Base.D_CBL_49_B
out D_CBL_49_Bstd_logic
Definition: CMX_top_Base.vhd:657
decoder.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: jet_decoder.vhd:68
Topo_Data_TX.ext_trigger
in ext_triggerstd_logic
Definition: Topo_Data_TX.vhd:50
CMX_top_Base.BF_SYSMON_11_N
in BF_SYSMON_11_NSTD_LOGIC
Definition: CMX_top_Base.vhd:80
CMX_top_Base.RXN_IN
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: CMX_top_Base.vhd:762
CMX_top_Base.P3_19
in P3_19std_logic
Definition: CMX_top_Base.vhd:185
CMX_top_Base.Behavioral.data_to_vme_test_r
std_logic_vector (15 downto 0) data_to_vme_test_r
Definition: CMX_top_Base.vhd:939
CMX_top_Base.MP2_F11_QUAD_114_TRN_1_CMP
out MP2_F11_QUAD_114_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:744
CMX_top_Base.P2_16
in P2_16std_logic
Definition: CMX_top_Base.vhd:157
decoder.datai
in dataiarr_4Xword (max_jems - 1 downto 0)
Definition: jet_decoder.vhd:47
CMX_top_Base.P9_14
in P9_14std_logic
Definition: CMX_top_Base.vhd:330
SFP_Data_TXRX.DFETAP3MONITOR
out DFETAP3MONITORstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:66
vme_local_switch
Definition: vme_local_switch.vhd:22
CMX_top_Base.D_CBL_11_B
out D_CBL_11_Bstd_logic
Definition: CMX_top_Base.vhd:617
CMX_top_Base.P2_7
in P2_7std_logic
Definition: CMX_top_Base.vhd:148
CMX_top_Base.P12_10
in P12_10std_logic
Definition: CMX_top_Base.vhd:401
BCID_counter.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: BCID_counter.vhd:38
CMX_top_Base.P10_24
in P10_24std_logic
Definition: CMX_top_Base.vhd:365
Topo_Data_TX.TXP_OUT
out TXP_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:37
CMX_top_Base.P0_0
in P0_0std_logic
Definition: CMX_top_Base.vhd:91
daq_collector.dout_ro
in dout_roT_SL
Definition: daq_collector.vhd:31
daq_glink.l1a
in l1astd_logic
Definition: daq_glink.vhd:28
vme_outreg_notri_async
Definition: vme_outreg_rtl_notri_async.vhd:16
CMX_top_Base.P9_1
in P9_1std_logic
Definition: CMX_top_Base.vhd:317
CMX_top_Base.MP1_F00_QUAD_112_TRN_3_DIR
out MP1_F00_QUAD_112_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:731
BCID_counter.reset
in resetstd_logic
Definition: BCID_counter.vhd:30
CMX_top_Base.P11_5
in P11_5std_logic
Definition: CMX_top_Base.vhd:371
CMX_top_Base.MP1_F06_QUAD_112_TRN_1_CMP
out MP1_F06_QUAD_112_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:728
CMX_top_Base.P14_16
in P14_16std_logic
Definition: CMX_top_Base.vhd:457
CMX_top_Base.BF_SYSMON_11_P
in BF_SYSMON_11_PSTD_LOGIC
Definition: CMX_top_Base.vhd:79
decoder.ncs
in ncsstd_logic
Definition: jet_decoder.vhd:64
SFP_Data_TXRX.GTX_RX_READY_OUT
out GTX_RX_READY_OUTstd_logic
Definition: SFP_TXRX.vhd:37
sys_monitor.BF_SYSMON_01_P
in BF_SYSMON_01_PSTD_LOGIC
Definition: sys_monitor.vhd:28
CMX_delay_generator.ncs
in ncsstd_logic
Definition: CMX_delay_generator.vhd:34
CMX_top_Base.D_CBL_34_B
out D_CBL_34_Bstd_logic
Definition: CMX_top_Base.vhd:642
CMX_top_Base.BF_DOUT_CTP_58
out BF_DOUT_CTP_58std_logic
Definition: CMX_top_Base.vhd:598
CMX_top_Base.P8_2
in P8_2std_logic
Definition: CMX_top_Base.vhd:293
CMX_top_Base.BF_DOUT_CTP_10
out BF_DOUT_CTP_10std_logic
Definition: CMX_top_Base.vhd:548
vme_outreg_notri.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl_notri.vhd:30
CMX_top_Base.OCB_SYS_RESET_B
in OCB_SYS_RESET_Bstd_logic
Definition: CMX_top_Base.vhd:60
CMX_top_Base.P10_1
in P10_1std_logic
Definition: CMX_top_Base.vhd:342
CMX_cable_clocked_80Mbps_output_module.numbits_in_cable_connector
numbits_in_cable_connectorinteger
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:24
CMX_top_Base.P7_22
in P7_22std_logic
Definition: CMX_top_Base.vhd:288
decoder.BCID_in
in BCID_instd_logic_vector (11 downto 0)
Definition: jet_decoder.vhd:56
SFP_Data_TXRX.DFETAP1
in DFETAP1std_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:61
CMX_BASE_VME_BSPT
Definition: cmx_base_vme_bspt.vhd:24
CMX_top_Base.P15_4
in P15_4std_logic
Definition: CMX_top_Base.vhd:470
CMX_top_Base.D_CBL_70_B
out D_CBL_70_Bstd_logic
Definition: CMX_top_Base.vhd:680
CMX_top_Base.P3_3
in P3_3std_logic
Definition: CMX_top_Base.vhd:169
BCID_counter.ncs
in ncsstd_logic
Definition: BCID_counter.vhd:34
vme_outreg.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl.vhd:27
vme_local_switch.bus_drive_up
out bus_drive_upstd_logic
or of all bus drive requests from below
Definition: vme_local_switch.vhd:38
CMX_top_Base.BF_DOUT_CTP_03
out BF_DOUT_CTP_03std_logic
Definition: CMX_top_Base.vhd:541
CMX_top_Base.D_CBL_65_B
out D_CBL_65_Bstd_logic
Definition: CMX_top_Base.vhd:675
CMX_clock_manager.buf_clk40
out buf_clk40std_logic
Definition: CMX_clock_manager.vhd:32
CMX_top_Base.P14_22
in P14_22std_logic
Definition: CMX_top_Base.vhd:463
CMX_top_Base.BUF_TTC_BNCH_CNT_RES
in BUF_TTC_BNCH_CNT_RESstd_logic
Definition: CMX_top_Base.vhd:699
CMX_top_Base.BF_DEBUG_9
out BF_DEBUG_9std_logic
Definition: CMX_top_Base.vhd:515
CMX_top_Base.P12_22
in P12_22std_logic
Definition: CMX_top_Base.vhd:413
CMX_system_cable_input_module.ds
in dsstd_logic
Definition: CMX_system_cable_input_module.vhd:46
CMX_top_Base.D_CBL_51_B
out D_CBL_51_Bstd_logic
Definition: CMX_top_Base.vhd:659
CMX_top_Base.P6_22
in P6_22std_logic
Definition: CMX_top_Base.vhd:263
CMX_top_Base.P11_22
in P11_22std_logic
Definition: CMX_top_Base.vhd:388
CMX_top_Base.P13_15
in P13_15std_logic
Definition: CMX_top_Base.vhd:431
CMX_Memory_spy_inhibit.buf_clk40
in buf_clk40std_logic
Definition: CMX_Memory_spy_inhibit.vhd:40
CMX_top_Base.P10_8
in P10_8std_logic
Definition: CMX_top_Base.vhd:349
CMX_top_Base.D_CBL_72_B
out D_CBL_72_Bstd_logic
Definition: CMX_top_Base.vhd:682
CMX_top_Base.D_CBL_00_B
out D_CBL_00_Bstd_logic
Definition: CMX_top_Base.vhd:606
CMX_top_Base.BF_DEBUG_5
out BF_DEBUG_5std_logic
Definition: CMX_top_Base.vhd:511
CMX_top_Base.MP2_F10_QUAD_114_TRN_2_CMP
out MP2_F10_QUAD_114_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:746
CMX_system_cable_input_module.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_system_cable_input_module.vhd:48
adder_top.gen_system
gen_systemstd_logic :='1'
Definition: adder_top_vs.vhd:32
daq_glink.RAM_global_offset
in RAM_global_offsetunsigned (7 downto 0)
Definition: daq_glink.vhd:34
CMX_top_Base.P11_21
in P11_21std_logic
Definition: CMX_top_Base.vhd:387
CMX_top_Base.P12_16
in P12_16std_logic
Definition: CMX_top_Base.vhd:407
CMX_system_cable_input_module.data
out datastd_logic_vector (numbits_in_RTM_connector * 2 * num_RTM_cables - 1 downto 0)
Definition: CMX_system_cable_input_module.vhd:32
CMX_top_Base.MP1_F10_QUAD_111_TRN_2_CMP
out MP1_F10_QUAD_111_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:722
CMX_top_Base.P9_16
in P9_16std_logic
Definition: CMX_top_Base.vhd:332
CMX_top_Base.P0_21
in P0_21std_logic
Definition: CMX_top_Base.vhd:112
CMX_top_Base.BF_SYSMON_07_P
in BF_SYSMON_07_PSTD_LOGIC
Definition: CMX_top_Base.vhd:71
CMX_input_module.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: CMX_input_module.vhd:60
CMX_top_Base.D_CBL_77_B
out D_CBL_77_Bstd_logic
Definition: CMX_top_Base.vhd:687
CMX_top_Base.D_CBL_41_B
out D_CBL_41_Bstd_logic
Definition: CMX_top_Base.vhd:649
CMX_top_Base.P1_6
in P1_6std_logic
Definition: CMX_top_Base.vhd:122
CMX_top_Base.P13_8
in P13_8std_logic
Definition: CMX_top_Base.vhd:424
CMX_top_Base.D_CBL_53_B
out D_CBL_53_Bstd_logic
Definition: CMX_top_Base.vhd:661
CMX_input_module.ncs
in ncsstd_logic
Definition: CMX_input_module.vhd:57
CMX_top_Base.P15_13
in P15_13std_logic
Definition: CMX_top_Base.vhd:479
CMX_rate_counter_inhibit.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_rate_counter_inhibit.vhd:39
CMX_top_Base.P8_5
in P8_5std_logic
Definition: CMX_top_Base.vhd:296
CMX_top_Base.BF_DEBUG_0
out BF_DEBUG_0std_logic
Definition: CMX_top_Base.vhd:506
sys_monitor.BF_SYSMON_08_N
in BF_SYSMON_08_NSTD_LOGIC
Definition: sys_monitor.vhd:37
CMX_cable_clocked_80Mbps_input_module.buf_clk200
in buf_clk200std_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:31
CMX_rate_counter_inhibit.counter_inhibit
out counter_inhibitstd_logic
Definition: CMX_rate_counter_inhibit.vhd:31
CMX_top_Base.P3_20
in P3_20std_logic
Definition: CMX_top_Base.vhd:186
CMX_top_Base.P10_21
in P10_21std_logic
Definition: CMX_top_Base.vhd:362
CMX_top_Base.P11_12
in P11_12std_logic
Definition: CMX_top_Base.vhd:378
adder_top.par_err
in par_errT_SLV2
Definition: adder_top_vs.vhd:57
CMX_top_Base.MP1_F09_QUAD_111_TRN_0_DIR
out MP1_F09_QUAD_111_TRN_0_DIRstd_logic
Definition: CMX_top_Base.vhd:717
CMX_top_Base.OCB_A08
in OCB_A08std_logic
Definition: CMX_top_Base.vhd:39
CMX_top_Base.BF_REQ_CTP_1_INPUT
out BF_REQ_CTP_1_INPUTstd_logic
Definition: CMX_top_Base.vhd:518
CMX_top_Base.BF_LED_REQ_3
out BF_LED_REQ_3std_logic
Definition: CMX_top_Base.vhd:526
CMX_top_Base.Behavioral.upload_delays
std_logic upload_delays
Definition: CMX_top_Base.vhd:1029
CMX_rate_counter_inhibit.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: CMX_rate_counter_inhibit.vhd:40
CMX_top_Base.BF_TO_FROM_BSPT_7
out BF_TO_FROM_BSPT_7std_logic
Definition: CMX_top_Base.vhd:535
CMX_top_Base.P4_11
in P4_11std_logic
Definition: CMX_top_Base.vhd:202
CMX_top_Base.BF_DOUT_CTP_25
out BF_DOUT_CTP_25std_logic
Definition: CMX_top_Base.vhd:563
CMX_top_Base.D_CBL_63_B
out D_CBL_63_Bstd_logic
Definition: CMX_top_Base.vhd:673
CMX_input_module.ODATA_first_half
out ODATA_first_halfarr_2Xword (numactchan - 1 downto 0)
Definition: CMX_input_module.vhd:35
CMX_rate_counter_inhibit.ds
in dsstd_logic
Definition: CMX_rate_counter_inhibit.vhd:37
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_114_CMP
in CLK_320MHz64_LHC_BF_QUAD_114_CMPstd_logic
Definition: CMX_top_Base.vhd:760
sys_monitor.BF_SYSMON_14_N
in BF_SYSMON_14_NSTD_LOGIC
Definition: sys_monitor.vhd:49
CMX_Memory_spy_inhibit.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_Memory_spy_inhibit.vhd:46
CMX_rate_counter_inhibit
Definition: CMX_rate_counter_inhibit.vhd:29
CMX_top_Base.BF_SYSMON_07_N
in BF_SYSMON_07_NSTD_LOGIC
Definition: CMX_top_Base.vhd:72
CMX_top_Base.P14_24
in P14_24std_logic
Definition: CMX_top_Base.vhd:465
glink_interface.ROI_BYTE
out ROI_BYTEstd_logic_vector (7 downto 0)
Definition: glink_interface.vhd:27
vme_inreg.ds
in dsstd_logic
Definition: vme_inreg_rtl.vhd:29
SFP_Data_TXRX.clk40_in
in clk40_instd_logic
Definition: SFP_TXRX.vhd:48
CMX_top_Base.P14_18
in P14_18std_logic
Definition: CMX_top_Base.vhd:459
CMX_top_Base.P7_23
in P7_23std_logic
Definition: CMX_top_Base.vhd:289
sys_monitor.BF_SYSMON_08_P
in BF_SYSMON_08_PSTD_LOGIC
Definition: sys_monitor.vhd:36
CMX_flavor_package
Definition: CMX_flavor_package.vhd:19
CMX_cable_clocked_80Mbps_output_module.upload_delays
in upload_delaysstd_logic
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:35
CMX_top_Base.P5_12
in P5_12std_logic
Definition: CMX_top_Base.vhd:228
CMX_top_Base.P13_11
in P13_11std_logic
Definition: CMX_top_Base.vhd:427
daq_glink.reset
in resetstd_logic
Definition: daq_glink.vhd:33
SFP_Data_TXRX.DFETAP4MONITOR
out DFETAP4MONITORstd_logic_vector (3 downto 0)
Definition: SFP_TXRX.vhd:68
vme_inreg_notri.ia_vme
ia_vmeinteger :=0
Definition: vme_inreg_rtl_notri.vhd:21
CMX_top_Base.MP1_F05_QUAD_110_TRN_3_DIR
out MP1_F05_QUAD_110_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:715
CMX_top_Base.P2_10
in P2_10std_logic
Definition: CMX_top_Base.vhd:151
CMX_top_Base.P3_18
in P3_18std_logic
Definition: CMX_top_Base.vhd:184
CMX_top_Base.P3_12
in P3_12std_logic
Definition: CMX_top_Base.vhd:178
CMX_top_Base.P8_17
in P8_17std_logic
Definition: CMX_top_Base.vhd:308
CMX_top_Base.BF_DOUT_CTP_20
out BF_DOUT_CTP_20std_logic
Definition: CMX_top_Base.vhd:558
CMX_top_Base.BF_SYSMON_15_N
in BF_SYSMON_15_NSTD_LOGIC
Definition: CMX_top_Base.vhd:88
CMX_top_Base.P13_5
in P13_5std_logic
Definition: CMX_top_Base.vhd:421
CMX_top_Base.P13_14
in P13_14std_logic
Definition: CMX_top_Base.vhd:430
vme_main_hub.data_vme_from_below
in data_vme_from_belowstd_logic_vector (15 downto 0)
--! input: ORed
Definition: vme_main_hub.vhd:25
CMX_top_Base.P11_11
in P11_11std_logic
Definition: CMX_top_Base.vhd:377
CMX_clock_manager.buf_clk40_m90o
out buf_clk40_m90ostd_logic
Definition: CMX_clock_manager.vhd:35
CMX_top_Base.OCB_A06
in OCB_A06std_logic
Definition: CMX_top_Base.vhd:37
CMX_top_Base.D_CBL_05_B
out D_CBL_05_Bstd_logic
Definition: CMX_top_Base.vhd:611
CMX_top_Base.P1_9
in P1_9std_logic
Definition: CMX_top_Base.vhd:125
glink_interface.ROI_IN
in ROI_INstd_logic_vector (19 downto 0)
Definition: glink_interface.vhd:23
CMX_top_Base.P9_9
in P9_9std_logic
Definition: CMX_top_Base.vhd:325
CMX_top_Base.P15_6
in P15_6std_logic
Definition: CMX_top_Base.vhd:472
CMX_top_Base.P0_16
in P0_16std_logic
Definition: CMX_top_Base.vhd:107
CMX_top_Base.P11_4
in P11_4std_logic
Definition: CMX_top_Base.vhd:370
CMX_top_Base.MP1_F06_QUAD_112_TRN_1_DIR
out MP1_F06_QUAD_112_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:727
CMX_top_Base.P14_3
in P14_3std_logic
Definition: CMX_top_Base.vhd:444
CMX_BASE_VME_BSPT.board_ds
out board_dsstd_logic
Definition: cmx_base_vme_bspt.vhd:31
CMX_top_Base.BF_DOUT_CTP_30
out BF_DOUT_CTP_30std_logic
Definition: CMX_top_Base.vhd:568
CMX_top_Base.P13_13
in P13_13std_logic
Definition: CMX_top_Base.vhd:429
sys_monitor.BF_SYSMON_11_P
in BF_SYSMON_11_PSTD_LOGIC
Definition: sys_monitor.vhd:42
CMX_top_Base.MP2_F05_QUAD_113_TRN_3_DIR
out MP2_F05_QUAD_113_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:739
CMX_top_Base.P4_1
in P4_1std_logic
Definition: CMX_top_Base.vhd:192
sys_monitor.clk
in clkstd_logic
Definition: sys_monitor.vhd:27
CMX_top_Base.P0_5
in P0_5std_logic
Definition: CMX_top_Base.vhd:96
CMX_rate_counter_inhibit.rd_nwr
in rd_nwrstd_logic
Definition: CMX_rate_counter_inhibit.vhd:36
CMX_input_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_input_module.vhd:54
BCID_counter.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: BCID_counter.vhd:37
CMX_top_Base.P6_6
in P6_6std_logic
Definition: CMX_top_Base.vhd:247
CMX_top_Base.P5_15
in P5_15std_logic
Definition: CMX_top_Base.vhd:231
CMX_top_Base.MP1_F09_QUAD_111_TRN_0_CMP
out MP1_F09_QUAD_111_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:718
CMX_top_Base.P5_1
in P5_1std_logic
Definition: CMX_top_Base.vhd:217
CMX_top_Base.MP1_F05_QUAD_110_TRN_3_CMP
out MP1_F05_QUAD_110_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:716
CMX_top_Base.BUF_TTC_L1_ACCEPT
in BUF_TTC_L1_ACCEPTstd_logic
Definition: CMX_top_Base.vhd:698
CMX_top_Base.P6_10
in P6_10std_logic
Definition: CMX_top_Base.vhd:251
vme_inreg_notri.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:31
CMX_top_Base.BF_DEBUG_3
out BF_DEBUG_3std_logic
Definition: CMX_top_Base.vhd:509
Topo_Data_TX.ncs
in ncsstd_logic
Definition: Topo_Data_TX.vhd:52
CMX_top_Base.BF_SYSMON_08_N
in BF_SYSMON_08_NSTD_LOGIC
Definition: CMX_top_Base.vhd:74
adder_top.din_cbla_ro
in din_cbla_roT_SL
Definition: adder_top_vs_cp.vhd:38
CMX_top_Base.P2_4
in P2_4std_logic
Definition: CMX_top_Base.vhd:145
CMX_top_Base.P12_14
in P12_14std_logic
Definition: CMX_top_Base.vhd:405
CMX_top_Base.P8_7
in P8_7std_logic
Definition: CMX_top_Base.vhd:298
CMX_top_Base.BF_SYSMON_10_P
in BF_SYSMON_10_PSTD_LOGIC
Definition: CMX_top_Base.vhd:77
CMX_top_Base.P12_1
in P12_1std_logic
Definition: CMX_top_Base.vhd:392
CMX_top_Base.P7_12
in P7_12std_logic
Definition: CMX_top_Base.vhd:278
SFP_Data_TXRX.RXEQMIX_IN
in RXEQMIX_INstd_logic_vector (2 downto 0)
Definition: SFP_TXRX.vhd:55
CMX_top_Base.P14_11
in P14_11std_logic
Definition: CMX_top_Base.vhd:452
CMX_top_Base.P0_14
in P0_14std_logic
Definition: CMX_top_Base.vhd:105
CMX_top_Base.D_CBL_37_B
out D_CBL_37_Bstd_logic
Definition: CMX_top_Base.vhd:645
CMX_top_Base.P8_10
in P8_10std_logic
Definition: CMX_top_Base.vhd:301
Topo_Data_TX.clk320
in clk320std_logic
Definition: Topo_Data_TX.vhd:39
CMX_top_Base.BF_DAQ_DATA_OUT_DIR
out BF_DAQ_DATA_OUT_DIRstd_logic
Definition: CMX_top_Base.vhd:704
CMX_top_Base.BF_DOUT_CTP_22
out BF_DOUT_CTP_22std_logic
Definition: CMX_top_Base.vhd:560
SFP_Data_TXRX.indata
in indatastd_logic_vector (7 downto 0)
Definition: SFP_TXRX.vhd:50
CMX_top_Base.P5_17
in P5_17std_logic
Definition: CMX_top_Base.vhd:233
CMX_top_Base.BF_DOUT_CTP_08
out BF_DOUT_CTP_08std_logic
Definition: CMX_top_Base.vhd:546
CMX_top_Base.P7_19
in P7_19std_logic
Definition: CMX_top_Base.vhd:285
CMX_top_Base.D_CBL_44_B
out D_CBL_44_Bstd_logic
Definition: CMX_top_Base.vhd:652
vme_inreg.clk
in clkstd_logic
Definition: vme_inreg_rtl.vhd:25
CMX_top_Base.P15_8
in P15_8std_logic
Definition: CMX_top_Base.vhd:474
glink_interface.daq_byte_out
out daq_byte_outstd_logic_vector (1 downto 0)
Definition: glink_interface.vhd:29
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_111_CMP
in CLK_320MHz64_LHC_BF_QUAD_111_CMPstd_logic
Definition: CMX_top_Base.vhd:758
CMX_top_Base.P14_2
in P14_2std_logic
Definition: CMX_top_Base.vhd:443
sys_monitor.ADDR_REG_RO_SYSMON_DATA_BLOCK
ADDR_REG_RO_SYSMON_DATA_BLOCKinteger :=16#1364#
Definition: sys_monitor.vhd:22
CMX_rate_counter_inhibit.counter_reset
out counter_resetstd_logic
Definition: CMX_rate_counter_inhibit.vhd:32
vme_inreg_notri.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_inreg_rtl_notri.vhd:37
CMX_top_Base.P8_0
in P8_0std_logic
Definition: CMX_top_Base.vhd:291
CMX_top_Base.BF_TO_FROM_BSPT_4
out BF_TO_FROM_BSPT_4std_logic
Definition: CMX_top_Base.vhd:532
CMX_top_Base.BF_DEBUG_6
out BF_DEBUG_6std_logic
Definition: CMX_top_Base.vhd:512
vme_outreg.data_vme
out data_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl.vhd:28
CMX_top_Base.P15_22
in P15_22std_logic
Definition: CMX_top_Base.vhd:488
CMX_top_Base.BF_DOUT_CTP_09
out BF_DOUT_CTP_09std_logic
Definition: CMX_top_Base.vhd:547
CMX_top_Base.P8_14
in P8_14std_logic
Definition: CMX_top_Base.vhd:305
SFP_Data_TXRX.odata
out odatastd_logic_vector (7 downto 0)
Definition: SFP_TXRX.vhd:51
vme_outreg_notri_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:23
decoder.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: jet_decoder.vhd:67
CMX_top_Base.MP1_F08_QUAD_111_TRN_3_CMP
out MP1_F08_QUAD_111_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:724
vme_outreg_notri.rd_nwr
in rd_nwrstd_logic
Definition: vme_outreg_rtl_notri.vhd:23
CMX_CTP_output_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_CTP_output_module.vhd:39
CMX_top_Base.P15_3
in P15_3std_logic
Definition: CMX_top_Base.vhd:469
CMX_top_Base.P11_24
in P11_24std_logic
Definition: CMX_top_Base.vhd:390
CMX_top_Base.P9_15
in P9_15std_logic
Definition: CMX_top_Base.vhd:331
CMX_top_Base.P4_16
in P4_16std_logic
Definition: CMX_top_Base.vhd:207
SFP_Data_TXRX.GTX_TX_READY_OUT
out GTX_TX_READY_OUTstd_logic
Definition: SFP_TXRX.vhd:36
CMX_top_Base.P15_21
in P15_21std_logic
Definition: CMX_top_Base.vhd:487
BCID_counter.bus_drive
out bus_drivestd_logic
Definition: BCID_counter.vhd:40
sys_monitor.BF_SYSMON_15_P
in BF_SYSMON_15_PSTD_LOGIC
Definition: sys_monitor.vhd:50
CMX_top_Base.CLK_320MHz64_LHC_BF_QUAD_111_DIR
in CLK_320MHz64_LHC_BF_QUAD_111_DIRstd_logic
Definition: CMX_top_Base.vhd:757
CMX_top_Base.P12_21
in P12_21std_logic
Definition: CMX_top_Base.vhd:412
CMX_top_Base.P7_13
in P7_13std_logic
Definition: CMX_top_Base.vhd:279
CMX_top_Base.P13_21
in P13_21std_logic
Definition: CMX_top_Base.vhd:437
CMX_top_Base.P0_12
in P0_12std_logic
Definition: CMX_top_Base.vhd:103
CMX_top_Base.OCB_A13
in OCB_A13std_logic
Definition: CMX_top_Base.vhd:44
vme_inreg_notri_async.ds
in dsstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:27
CMX_top_Base.D_CBL_16_B
in D_CBL_16_Bstd_logic
Definition: CMX_top_Base.vhd:622
CMX_top_Base.MP1_F11_QUAD_111_TRN_1_DIR
out MP1_F11_QUAD_111_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:719
CMX_top_Base.P7_4
in P7_4std_logic
Definition: CMX_top_Base.vhd:270
vme_inreg_notri_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl_notri_async.vhd:26
CMX_top_Base.MP1_F03_QUAD_110_TRN_1_CMP
out MP1_F03_QUAD_110_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:712
CMX_top_Base.P7_24
in P7_24std_logic
Definition: CMX_top_Base.vhd:290
CMX_top_Base.OCB_A04
in OCB_A04std_logic
Definition: CMX_top_Base.vhd:35
CMX_top_Base.BF_REQ_CABLE_2_INPUT
out BF_REQ_CABLE_2_INPUTstd_logic
Definition: CMX_top_Base.vhd:521
CMX_CTP_output_module.bus_drive
out bus_drivestd_logic
Definition: CMX_CTP_output_module.vhd:49
CMX_top_Base.MP2_F03_QUAD_113_TRN_1_CMP
out MP2_F03_QUAD_113_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:736
CMX_top_Base.P8_23
in P8_23std_logic
Definition: CMX_top_Base.vhd:314
glink_interface.readout_rst_out
out readout_rst_outstd_logic
Definition: glink_interface.vhd:32
CMX_top_Base.P9_8
in P9_8std_logic
Definition: CMX_top_Base.vhd:324
vme_inreg_notri_async.data_vme_out
out data_vme_outstd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri_async.vhd:31
CMX_clock_manager.pll_locked_ds2
out pll_locked_ds2std_logic
Definition: CMX_clock_manager.vhd:43
CMX_top_Base.OCB_WRITE_B
in OCB_WRITE_Bstd_logic
Definition: CMX_top_Base.vhd:58
CMX_top_Base.P4_2
in P4_2std_logic
Definition: CMX_top_Base.vhd:193
CMX_top_Base.OCB_GEO_ADRS_0
in OCB_GEO_ADRS_0std_logic
Definition: CMX_top_Base.vhd:30
CMX_top_Base.P13_3
in P13_3std_logic
Definition: CMX_top_Base.vhd:419
CMX_version.rd_nwr
in rd_nwrstd_logic
Definition: CMX_version.vhd:23
CMX_Memory_spy_inhibit.spy_write_inhibit
out spy_write_inhibitstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:39
CMX_top_Base.P5_9
in P5_9std_logic
Definition: CMX_top_Base.vhd:225
CMX_cable_clocked_80Mbps_input_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:32
CMX_top_Base.P10_4
in P10_4std_logic
Definition: CMX_top_Base.vhd:345
CMX_clock_manager.IB_DS2
in IB_DS2std_logic
Definition: CMX_clock_manager.vhd:41
CMX_top_Base.P2_9
in P2_9std_logic
Definition: CMX_top_Base.vhd:150
glink_interface.CLK_120MHz
in CLK_120MHzstd_logic
Definition: glink_interface.vhd:20
CMX_top_Base.P0_20
in P0_20std_logic
Definition: CMX_top_Base.vhd:111
SFP_Data_TXRX.DFETAP1MONITOR
out DFETAP1MONITORstd_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:62
CMX_top_Base.MP2_F10_QUAD_114_TRN_2_DIR
out MP2_F10_QUAD_114_TRN_2_DIRstd_logic
Definition: CMX_top_Base.vhd:745
CMX_CTP_output_module.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: CMX_CTP_output_module.vhd:47
CMX_top_Base.P1_14
in P1_14std_logic
Definition: CMX_top_Base.vhd:130
SFP_Data_TXRX.DFETAP2
in DFETAP2std_logic_vector (4 downto 0)
Definition: SFP_TXRX.vhd:63
CMX_top_Base.P12_13
in P12_13std_logic
Definition: CMX_top_Base.vhd:404
Topo_Data_TX.indata
in indatastd_logic_vector (TX_indata_length - 1 downto 0)
Definition: Topo_Data_TX.vhd:48
CMX_top_Base.BF_DOUT_CTP_63
out BF_DOUT_CTP_63std_logic
Definition: CMX_top_Base.vhd:603
CMX_top_Base.Behavioral.vme_outreg_notri_async
vme_outreg_notri_async
Definition: CMX_top_Base.vhd:885
CMX_top_Base.D_CBL_75_B
out D_CBL_75_Bstd_logic
Definition: CMX_top_Base.vhd:685
CMX_top_Base.P6_20
in P6_20std_logic
Definition: CMX_top_Base.vhd:261
CMX_top_Base.BF_SYSMON_03_P
in BF_SYSMON_03_PSTD_LOGIC
Definition: CMX_top_Base.vhd:67
vme_outreg_notri.clk
in clkstd_logic
Definition: vme_outreg_rtl_notri.vhd:20
CMX_top_Base.P1_13
in P1_13std_logic
Definition: CMX_top_Base.vhd:129
adder_top.bus_drive
out bus_drivestd_logic
Definition: adder_top_vs.vhd:55
CMX_clock_manager.rd_nwr
in rd_nwrstd_logic
Definition: CMX_clock_manager.vhd:45
CMX_top_Base.P2_12
in P2_12std_logic
Definition: CMX_top_Base.vhd:153
CMX_top_Base.P5_19
in P5_19std_logic
Definition: CMX_top_Base.vhd:235
CMX_top_Base.P6_23
in P6_23std_logic
Definition: CMX_top_Base.vhd:264
CMX_top_Base.P11_13
in P11_13std_logic
Definition: CMX_top_Base.vhd:379
daq_glink
Definition: daq_glink.vhd:21
sys_monitor.BF_SYSMON_04_P
in BF_SYSMON_04_PSTD_LOGIC
Definition: sys_monitor.vhd:32
CMX_top_Base.Behavioral.vme_inreg_async
vme_inreg_async
Definition: CMX_top_Base.vhd:833
adder_top.dout_ro
out dout_roT_SL
Definition: adder_top_vs.vhd:43
Topo_Data_TX.BCID
in BCIDstd_logic_vector (11 downto 0)
Definition: Topo_Data_TX.vhd:42
CMX_top_Base.BF_DOUT_CTP_40
out BF_DOUT_CTP_40std_logic
Definition: CMX_top_Base.vhd:580
CMX_input_module.buf_clk40
in buf_clk40std_logic
Definition: CMX_input_module.vhd:28
daq_collector.din_cblc_ro
in din_cblc_roT_SL
Definition: daq_collector.vhd:30
daq_collector.datai
in dataiarr_4Xword (max_jems - 1 downto 0)
Definition: daq_collector.vhd:25
SFP_Data_TXRX.PLLLKDET_diag
out PLLLKDET_diagstd_logic
Definition: SFP_TXRX.vhd:38
CMX_top_Base.P5_20
in P5_20std_logic
Definition: CMX_top_Base.vhd:236
CMX_top_Base.P5_22
in P5_22std_logic
Definition: CMX_top_Base.vhd:238
CMX_top_Base.BF_SYSMON_04_P
in BF_SYSMON_04_PSTD_LOGIC
Definition: CMX_top_Base.vhd:69
CMX_top_Base.D_CBL_60_B
out D_CBL_60_Bstd_logic
Definition: CMX_top_Base.vhd:670
daq_collector.din_cblb_ro
in din_cblb_roT_SL
Definition: daq_collector.vhd:29
CMX_top_Base.BF_ROI_DATA_OUT_CMP
out BF_ROI_DATA_OUT_CMPstd_logic
Definition: CMX_top_Base.vhd:707
CMX_top_Base.BF_DOUT_CTP_15
out BF_DOUT_CTP_15std_logic
Definition: CMX_top_Base.vhd:553
CMX_top_Base.P6_9
in P6_9std_logic
Definition: CMX_top_Base.vhd:250
CMX_top_Base.D_CBL_43_B
in D_CBL_43_Bstd_logic
Definition: CMX_top_Base.vhd:651
CMX_top_Base.P2_5
in P2_5std_logic
Definition: CMX_top_Base.vhd:146
CMX_top_Base.BF_DOUT_CTP_62
out BF_DOUT_CTP_62std_logic
Definition: CMX_top_Base.vhd:602
CMX_top_Base.P10_2
in P10_2std_logic
Definition: CMX_top_Base.vhd:343
daq_glink.dav
out davstd_logic
Definition: daq_glink.vhd:30
glink_interface.byte_pos_out
out byte_pos_outstd_logic_vector (5 downto 0)
Definition: glink_interface.vhd:30
CMX_top_Base.P14_19
in P14_19std_logic
Definition: CMX_top_Base.vhd:460
decoder.overflow
out overflowstd_logic_vector (num_copies - 1 downto 0)
Definition: jet_decoder.vhd:51
CMX_BASE_VME_BSPT.brdsel_n
out brdsel_nstd_logic
Definition: cmx_base_vme_bspt.vhd:32
CMX_top_Base.Behavioral.vme_main_hub
vme_main_hub
Definition: CMX_top_Base.vhd:855
SFP_Data_TXRX.clock_source
clock_sourcestd_logic
Definition: SFP_TXRX.vhd:27
CMX_top_Base.BF_DOUT_CTP_33
out BF_DOUT_CTP_33std_logic
Definition: CMX_top_Base.vhd:573
CMX_top_Base.P0_23
in P0_23std_logic
Definition: CMX_top_Base.vhd:114
CMX_top_Base.D_CBL_26_B
out D_CBL_26_Bstd_logic
Definition: CMX_top_Base.vhd:632
vme_inreg_notri.bus_drive
out bus_drivestd_logic
Definition: vme_inreg_rtl_notri.vhd:34
CMX_top_Base.P12_5
in P12_5std_logic
Definition: CMX_top_Base.vhd:396
CMX_top_Base.P8_18
in P8_18std_logic
Definition: CMX_top_Base.vhd:309
CMX_top_Base.P0_24
in P0_24std_logic
Definition: CMX_top_Base.vhd:115
Topo_Data_TX.bus_drive
out bus_drivestd_logic
Definition: Topo_Data_TX.vhd:58
vme_outreg_notri.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: vme_outreg_rtl_notri.vhd:26
CMX_cable_clocked_80Mbps_input_module.ddr_data_in
in ddr_data_instd_logic_vector (numbits_in_cable_connector downto 0)
Definition: CMX_cable_clocked_80Mbps_input_module.vhd:29
sys_monitor.BF_SYSMON_15_N
in BF_SYSMON_15_NSTD_LOGIC
Definition: sys_monitor.vhd:51
CMX_top_Base.MP2_F00_QUAD_115_TRN_3_DIR
out MP2_F00_QUAD_115_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:755
decoder.clk40MHz
in clk40MHzstd_logic
Definition: jet_decoder.vhd:42
Topo_Data_TX.RXN_IN
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:34
BCID_counter
Definition: BCID_counter.vhd:28
CMX_top_Base.D_CBL_47_B
out D_CBL_47_Bstd_logic
Definition: CMX_top_Base.vhd:655
CMX_top_Base.P8_11
in P8_11std_logic
Definition: CMX_top_Base.vhd:302
CMX_input_module.bus_drive
out bus_drivestd_logic
Definition: CMX_input_module.vhd:63
glink_interface.word_sel_out
out word_sel_outstd_logic_vector (1 downto 0)
Definition: glink_interface.vhd:31
CMX_top_Base.D_CBL_68_B
out D_CBL_68_Bstd_logic
Definition: CMX_top_Base.vhd:678
vme_outreg.ncs
in ncsstd_logic
Definition: vme_outreg_rtl.vhd:23
CMX_top_Base.P12_15
in P12_15std_logic
Definition: CMX_top_Base.vhd:406
Topo_Data_TX.RXP_IN
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
Definition: Topo_Data_TX.vhd:35
CMX_Memory_spy_inhibit.ds
in dsstd_logic
Definition: CMX_Memory_spy_inhibit.vhd:44
CMX_top_Base.Behavioral.test_rw_counter
unsigned (15 downto 0) test_rw_counter
Definition: CMX_top_Base.vhd:938
CMX_top_Base.P7_11
in P7_11std_logic
Definition: CMX_top_Base.vhd:277
CMX_CTP_output_module.sdr_data_out
out sdr_data_outarr_CTP
Definition: CMX_CTP_output_module.vhd:34
CMX_top_Base.P8_12
in P8_12std_logic
Definition: CMX_top_Base.vhd:303
CMX_top_Base.D_CBL_55_B
out D_CBL_55_Bstd_logic
Definition: CMX_top_Base.vhd:665
glink_interface.DAQ_IN
in DAQ_INstd_logic_vector (19 downto 0)
Definition: glink_interface.vhd:22
CMX_top_Base.P4_3
in P4_3std_logic
Definition: CMX_top_Base.vhd:194
daq_glink.clk4008
in clk4008std_logic
Definition: daq_glink.vhd:32
CMX_top_Base.P0_9
in P0_9std_logic
Definition: CMX_top_Base.vhd:100
SFP_Data_TXRX.DFESENSCAL
out DFESENSCALstd_logic_vector (2 downto 0)
Definition: SFP_TXRX.vhd:60
CMX_top_Base.P11_9
in P11_9std_logic
Definition: CMX_top_Base.vhd:375
vme_inreg_async.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_async_rtl.vhd:26
CMX_top_Base.P6_12
in P6_12std_logic
Definition: CMX_top_Base.vhd:253
CMX_top_Base.P13_7
in P13_7std_logic
Definition: CMX_top_Base.vhd:423
CMX_top_Base.D_CBL_36_B
out D_CBL_36_Bstd_logic
Definition: CMX_top_Base.vhd:644
vme_inreg_notri.rd_nwr
in rd_nwrstd_logic
Definition: vme_inreg_rtl_notri.vhd:28
CMX_top_Base.D_CBL_56_B
out D_CBL_56_Bstd_logic
Definition: CMX_top_Base.vhd:666
CMX_top_Base.CLK_40MHz08_DSKW_1_BF_LOGIC_CMP
in CLK_40MHz08_DSKW_1_BF_LOGIC_CMPstd_logic
Definition: CMX_top_Base.vhd:497
CMX_top_Base.P9_24
in P9_24std_logic
Definition: CMX_top_Base.vhd:340
CMX_clock_manager.buf_clk40_90o
out buf_clk40_90ostd_logic
Definition: CMX_clock_manager.vhd:33
CMX_top_Base.BF_DOUT_CTP_48
out BF_DOUT_CTP_48std_logic
Definition: CMX_top_Base.vhd:588
CMX_top_Base.OCB_A02
in OCB_A02std_logic
Definition: CMX_top_Base.vhd:33
SFP_Data_TXRX.MGTREFCLK
in MGTREFCLKstd_logic
Definition: SFP_TXRX.vhd:33
CMX_top_Base.P4_0
in P4_0std_logic
Definition: CMX_top_Base.vhd:191
CMX_top_Base.D_CBL_50_B
out D_CBL_50_Bstd_logic
Definition: CMX_top_Base.vhd:658
adder_top.datai
in dataiarr_4Xword (max_jems - 1 downto 0)
Definition: adder_top_vs.vhd:37
CMX_top_Base.D_CBL_40_B
out D_CBL_40_Bstd_logic
Definition: CMX_top_Base.vhd:648
CMX_top_Base.BF_DOUT_CTP_44
out BF_DOUT_CTP_44std_logic
Definition: CMX_top_Base.vhd:584
CMX_system_cable_input_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_system_cable_input_module.vhd:37
CMX_top_Base.BF_SYSMON_08_P
in BF_SYSMON_08_PSTD_LOGIC
Definition: CMX_top_Base.vhd:73
CMX_top_Base.P9_23
in P9_23std_logic
Definition: CMX_top_Base.vhd:339
CMX_CTP_output_module.buf_clk40_center
in buf_clk40_centerstd_logic
Definition: CMX_CTP_output_module.vhd:37
CMX_cable_clocked_80Mbps_output_module.buf_clk200
in buf_clk200std_logic
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:31
CMX_top_Base.P13_12
in P13_12std_logic
Definition: CMX_top_Base.vhd:428
CMX_top_Base.BF_DOUT_CTP_52
out BF_DOUT_CTP_52std_logic
Definition: CMX_top_Base.vhd:592
CMX_top_Base.P15_9
in P15_9std_logic
Definition: CMX_top_Base.vhd:475
CMX_VME_defs
test registers
Definition: CMX_VME_defs.vhd:13
CMX_system_cable_input_module.spy_write_inhibit
in spy_write_inhibitstd_logic
Definition: CMX_system_cable_input_module.vhd:42
CMX_clock_manager.I_DS2
in I_DS2std_logic
Definition: CMX_clock_manager.vhd:40
CMX_local_package
Definition: CMX_local_package.vhd:13
CMX_top_Base.D_CBL_12_B
out D_CBL_12_Bstd_logic
Definition: CMX_top_Base.vhd:618
CMX_top_Base.OCB_A20
in OCB_A20std_logic
Definition: CMX_top_Base.vhd:51
CMX_top_Base.P0_4
in P0_4std_logic
Definition: CMX_top_Base.vhd:95
CMX_BASE_VME_BSPT.clk40
in clk40std_logic
Definition: cmx_base_vme_bspt.vhd:26
CMX_top_Base.P6_13
in P6_13std_logic
Definition: CMX_top_Base.vhd:254
CMX_top_Base.Behavioral.bus_drive_from_below_top
std_logic_vector (1762 downto 0) bus_drive_from_below_top
Definition: CMX_top_Base.vhd:864
CMX_CTP_output_module.ds
in dsstd_logic
Definition: CMX_CTP_output_module.vhd:45
glink_interface.DAQ_ENCODED_DIAG
out DAQ_ENCODED_DIAGstd_logic_vector (23 downto 0)
Definition: glink_interface.vhd:28
CMX_top_Base.P10_3
in P10_3std_logic
Definition: CMX_top_Base.vhd:344
CMX_top_Base.Behavioral.keep
string keep
Definition: CMX_top_Base.vhd:773
CMX_top_Base.P1_3
in P1_3std_logic
Definition: CMX_top_Base.vhd:119
CMX_top_Base.P0_3
in P0_3std_logic
Definition: CMX_top_Base.vhd:94
CMX_top_Base.BF_REQ_CTP_2_INPUT
out BF_REQ_CTP_2_INPUTstd_logic
Definition: CMX_top_Base.vhd:519
CMX_top_Base.P14_15
in P14_15std_logic
Definition: CMX_top_Base.vhd:456
CMX_top_Base.P9_5
in P9_5std_logic
Definition: CMX_top_Base.vhd:321
CMX_top_Base.Behavioral.vme_inreg_notri
vme_inreg_notri
Definition: CMX_top_Base.vhd:899
SFP_Data_TXRX.clk40_out
out clk40_outstd_logic
Definition: SFP_TXRX.vhd:46
CMX_top_Base.P9_19
in P9_19std_logic
Definition: CMX_top_Base.vhd:335
glink_interface.DAQ_BYTE
out DAQ_BYTEstd_logic_vector (7 downto 0)
Definition: glink_interface.vhd:26
vme_outreg_notri_async.ia_vme
ia_vmeinteger :=0
Definition: vme_outreg_rtl_notri_async.vhd:18
CMX_top_Base.D_CBL_46_B
out D_CBL_46_Bstd_logic
Definition: CMX_top_Base.vhd:654
CMX_top_Base.P7_8
in P7_8std_logic
Definition: CMX_top_Base.vhd:274
CMX_top_Base.MP1_F02_QUAD_112_TRN_2_CMP
out MP1_F02_QUAD_112_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:730
CMX_top_Base.P14_0
in P14_0std_logic
Definition: CMX_top_Base.vhd:441
CMX_top_Base.P2_2
in P2_2std_logic
Definition: CMX_top_Base.vhd:143
CMX_cable_clocked_80Mbps_output_module.data
in datastd_logic_vector ((numbits_in_cable_connector * 2) - 1 downto 0)
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:26
CMX_top_Base.P10_0
in P10_0std_logic
Definition: CMX_top_Base.vhd:341
sys_monitor.bus_drive
out bus_drivestd_logic
Definition: sys_monitor.vhd:59
CMX_top_Base.MP2_F00_QUAD_115_TRN_3_CMP
out MP2_F00_QUAD_115_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:756
CMX_top_Base.P6_2
in P6_2std_logic
Definition: CMX_top_Base.vhd:243
vme_outreg_notri_async.ds
in dsstd_logic
Definition: vme_outreg_rtl_notri_async.vhd:24
decoder.pll_locked
in pll_lockedstd_logic
Definition: jet_decoder.vhd:46
CMX_top_Base.P10_7
in P10_7std_logic
Definition: CMX_top_Base.vhd:348
sys_monitor.BF_SYSMON_12_N
in BF_SYSMON_12_NSTD_LOGIC
Definition: sys_monitor.vhd:45
CMX_top_Base.P10_22
in P10_22std_logic
Definition: CMX_top_Base.vhd:363
adder_top.thresholds
in thresholdsarr_16 (max_jems * 25 * 4 - 1 downto 0)
Definition: adder_top_vs.vhd:36
CMX_top_Base.P4_5
in P4_5std_logic
Definition: CMX_top_Base.vhd:196
CMX_top_Base.P8_4
in P8_4std_logic
Definition: CMX_top_Base.vhd:295
CMX_top_Base.P7_1
in P7_1std_logic
Definition: CMX_top_Base.vhd:267
Topo_Data_TX.clk40
in clk40std_logic
Definition: Topo_Data_TX.vhd:38
sys_monitor
Definition: sys_monitor.vhd:20
CMX_top_Base.MP2_F05_QUAD_113_TRN_3_CMP
out MP2_F05_QUAD_113_TRN_3_CMPstd_logic
Definition: CMX_top_Base.vhd:740
CMX_top_Base.MP1_F08_QUAD_111_TRN_3_DIR
out MP1_F08_QUAD_111_TRN_3_DIRstd_logic
Definition: CMX_top_Base.vhd:723
CMX_top_Base.Behavioral.write_detect_inreg_test
std_logic write_detect_inreg_test
Definition: CMX_top_Base.vhd:937
Topo_Data_TX.pll_locked
in pll_lockedstd_logic
Definition: Topo_Data_TX.vhd:40
decoder.clk40MHz_m180o
in clk40MHz_m180ostd_logic
Definition: jet_decoder.vhd:45
CMX_top_Base.Behavioral.vme_inreg_notri_async
vme_inreg_notri_async
Definition: CMX_top_Base.vhd:869
CMX_top_Base.P15_1
in P15_1std_logic
Definition: CMX_top_Base.vhd:467
vme_inreg_notri.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: vme_inreg_rtl_notri.vhd:32
CMX_top_Base.OCB_D
inout OCB_Dstd_logic_vector (15 downto 0)
Definition: CMX_top_Base.vhd:62
CMX_top_Base.P13_10
in P13_10std_logic
Definition: CMX_top_Base.vhd:426
CMX_top_Base.D_CBL_35_B
in D_CBL_35_Bstd_logic
Definition: CMX_top_Base.vhd:643
SFP_Data_TXRX.DFETAPOVRD
in DFETAPOVRDstd_logic
Definition: SFP_TXRX.vhd:69
CMX_version.ds
in dsstd_logic
Definition: CMX_version.vhd:24
CMX_top_Base.P0_2
in P0_2std_logic
Definition: CMX_top_Base.vhd:93
CMX_top_Base.P10_20
in P10_20std_logic
Definition: CMX_top_Base.vhd:361
CMX_top_Base.P2_8
in P2_8std_logic
Definition: CMX_top_Base.vhd:149
CMX_top_Base.P5_5
in P5_5std_logic
Definition: CMX_top_Base.vhd:221
vme_inreg_async.ncs
in ncsstd_logic
Definition: vme_inreg_async_rtl.vhd:25
CMX_clock_manager.IB_DS1
in IB_DS1std_logic
Definition: CMX_clock_manager.vhd:31
CMX_top_Base.P15_11
in P15_11std_logic
Definition: CMX_top_Base.vhd:477
CMX_top_Base.BF_DOUT_CTP_02
out BF_DOUT_CTP_02std_logic
Definition: CMX_top_Base.vhd:540
decoder.bus_drive
out bus_drivestd_logic
Definition: jet_decoder.vhd:69
CMX_top_Base.MP1_F01_QUAD_110_TRN_0_CMP
out MP1_F01_QUAD_110_TRN_0_CMPstd_logic
Definition: CMX_top_Base.vhd:710
CMX_top_Base.P3_9
in P3_9std_logic
Definition: CMX_top_Base.vhd:175
CMX_top_Base.D_CBL_31_B
in D_CBL_31_Bstd_logic
Definition: CMX_top_Base.vhd:639
vme_inreg_async.data_vme
inout data_vmestd_logic_vector (15 downto 0)
Definition: vme_inreg_async_rtl.vhd:30
vme_outreg_notri.read_detect
out read_detectstd_logic
Definition: vme_outreg_rtl_notri.vhd:31
adder_top.data_vme_in
in data_vme_instd_logic_vector (15 downto 0)
Definition: adder_top_vs.vhd:53
vme_outreg_notri_async.data_to_vme
in data_to_vmestd_logic_vector (width - 1 downto 0)
Definition: vme_outreg_rtl_notri_async.vhd:30
CMX_top_Base.D_CBL_13_B
out D_CBL_13_Bstd_logic
Definition: CMX_top_Base.vhd:619
CMX_top_Base.CLK_40MHz08_DSKW_1_BF_LOGIC_DIR
in CLK_40MHz08_DSKW_1_BF_LOGIC_DIRstd_logic
Definition: CMX_top_Base.vhd:496
CMX_top_Base.BF_DOUT_CTP_13
out BF_DOUT_CTP_13std_logic
Definition: CMX_top_Base.vhd:551
CMX_top_Base.P13_1
in P13_1std_logic
Definition: CMX_top_Base.vhd:417
CMX_top_Base.Behavioral.CMX_version
CMX_version
Definition: CMX_top_Base.vhd:948
CMX_top_Base.MP2_F02_QUAD_115_TRN_2_CMP
out MP2_F02_QUAD_115_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:754
CMX_top_Base.P15_7
in P15_7std_logic
Definition: CMX_top_Base.vhd:473
CMX_top_Base.MP2_F06_QUAD_115_TRN_1_CMP
out MP2_F06_QUAD_115_TRN_1_CMPstd_logic
Definition: CMX_top_Base.vhd:752
CMX_top_Base.D_CBL_61_B
out D_CBL_61_Bstd_logic
Definition: CMX_top_Base.vhd:671
CMX_version.clk40
in clk40std_logic
Definition: CMX_version.vhd:21
CMX_clock_manager.buf_clk40_ds2
out buf_clk40_ds2std_logic
Definition: CMX_clock_manager.vhd:42
CMX_system_cable_input_module.pll_locked_ds2
in pll_locked_ds2std_logic
Definition: CMX_system_cable_input_module.vhd:38
CMX_top_Base.P6_17
in P6_17std_logic
Definition: CMX_top_Base.vhd:258
CMX_top_Base.P5_3
in P5_3std_logic
Definition: CMX_top_Base.vhd:219
CMX_top_Base.BF_DOUT_CTP_59
out BF_DOUT_CTP_59std_logic
Definition: CMX_top_Base.vhd:599
CMX_top_Base.D_CBL_71_B
out D_CBL_71_Bstd_logic
Definition: CMX_top_Base.vhd:681
glink_interface.ROI_DAV
in ROI_DAVstd_logic
Definition: glink_interface.vhd:25
CMX_input_module.buf_clk200
in buf_clk200std_logic
Definition: CMX_input_module.vhd:30
CMX_top_Base.CLK_40MHz08_DSKW_2_BF_LOGIC_DIR
in CLK_40MHz08_DSKW_2_BF_LOGIC_DIRstd_logic
Definition: CMX_top_Base.vhd:499
CMX_top_Base.BF_TO_TP_ROI_SLINK_RETURN_DIR
in BF_TO_TP_ROI_SLINK_RETURN_DIRstd_logic
Definition: CMX_top_Base.vhd:695
CMX_input_module.rd_nwr
in rd_nwrstd_logic
Definition: CMX_input_module.vhd:58
CMX_top_Base.BF_DOUT_CTP_56
out BF_DOUT_CTP_56std_logic
Definition: CMX_top_Base.vhd:596
vme_outreg_notri
Definition: vme_outreg_rtl_notri.vhd:14
CMX_top_Base.P15_17
in P15_17std_logic
Definition: CMX_top_Base.vhd:483
Topo_Data_TX.GTXTXRESET_IN
in GTXTXRESET_INstd_logic
Definition: Topo_Data_TX.vhd:29
CMX_top_Base.MP2_F07_QUAD_113_TRN_2_CMP
out MP2_F07_QUAD_113_TRN_2_CMPstd_logic
Definition: CMX_top_Base.vhd:738
CMX_top_Base.P4_7
in P4_7std_logic
Definition: CMX_top_Base.vhd:198
CMX_top_Base.P2_20
in P2_20std_logic
Definition: CMX_top_Base.vhd:161
CMX_top_Base.D_CBL_19_B
out D_CBL_19_Bstd_logic
Definition: CMX_top_Base.vhd:625
adder_top.addr_vme
in addr_vmestd_logic_vector (15 downto 0)
Definition: adder_top_vs.vhd:52
CMX_top_Base.P14_23
in P14_23std_logic
Definition: CMX_top_Base.vhd:464
CMX_top_Base.BF_DOUT_CTP_11
out BF_DOUT_CTP_11std_logic
Definition: CMX_top_Base.vhd:549
CMX_top_Base.P3_17
in P3_17std_logic
Definition: CMX_top_Base.vhd:183
decoder.counter_reset
in counter_resetstd_logic
Definition: jet_decoder.vhd:62
vme_inreg
Definition: vme_inreg_rtl.vhd:19
CMX_top_Base.BF_DOUT_CTP_36
out BF_DOUT_CTP_36std_logic
Definition: CMX_top_Base.vhd:576
vme_inreg_notri.ds
in dsstd_logic
Definition: vme_inreg_rtl_notri.vhd:29
CMX_top_Base.MP1_F03_QUAD_110_TRN_1_DIR
out MP1_F03_QUAD_110_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:711
CMX_top_Base.UNISIM
_library_ UNISIMUNISIM
Definition: CMX_top_Base.vhd:12
CMX_top_Base.D_CBL_66_B
out D_CBL_66_Bstd_logic
Definition: CMX_top_Base.vhd:676
daq_glink.data_out
out data_outstd_logic_vector (19 downto 0)
Definition: daq_glink.vhd:29
vme_local_switch.bus_drive_from_below
in bus_drive_from_belowstd_logic_vector
Definition: vme_local_switch.vhd:40
SFP_Data_TXRX.RXP_IN
in RXP_INstd_logic
Definition: SFP_TXRX.vhd:43
CMX_top_Base.P11_15
in P11_15std_logic
Definition: CMX_top_Base.vhd:381
CMX_top_Base.P5_23
in P5_23std_logic
Definition: CMX_top_Base.vhd:239
CMX_top_Base.P13_16
in P13_16std_logic
Definition: CMX_top_Base.vhd:432
CMX_top_Base.P9_0
in P9_0std_logic
Definition: CMX_top_Base.vhd:316
vme_inreg_notri_async
Definition: vme_inreg_rtl_notri_async.vhd:18
CMX_top_Base.P1_12
in P1_12std_logic
Definition: CMX_top_Base.vhd:128
CMX_delay_generator.start_address
start_addressinteger
Definition: CMX_delay_generator.vhd:30
CMX_top_Base.BF_SYSMON_12_N
in BF_SYSMON_12_NSTD_LOGIC
Definition: CMX_top_Base.vhd:82
CMX_cable_clocked_80Mbps_output_module.pll_locked
in pll_lockedstd_logic
Definition: CMX_cable_clocked_80Mbps_output_module.vhd:32
adder_top.rd_nwr
in rd_nwrstd_logic
Definition: adder_top_vs.vhd:50
adder_top.ADDR_REG_RW_PIPELINE_DELAY_LENGTH
ADDR_REG_RW_PIPELINE_DELAY_LENGTHinteger :=0
Definition: adder_top_vs.vhd:31
CMX_top_Base.P8_22
in P8_22std_logic
Definition: CMX_top_Base.vhd:313
CMX_top_Base.BF_DEBUG_1
out BF_DEBUG_1std_logic
Definition: CMX_top_Base.vhd:507
CMX_top_Base.D_CBL_02_B
out D_CBL_02_Bstd_logic
Definition: CMX_top_Base.vhd:608
CMX_top_Base.D_CBL_52_B
out D_CBL_52_Bstd_logic
Definition: CMX_top_Base.vhd:660
CMX_top_Base.P11_17
in P11_17std_logic
Definition: CMX_top_Base.vhd:383
CMX_top_Base.D_CBL_18_B
out D_CBL_18_Bstd_logic
Definition: CMX_top_Base.vhd:624
CMX_top_Base.D_CBL_10_B
out D_CBL_10_Bstd_logic
Definition: CMX_top_Base.vhd:616
CMX_CP_Topo_Encoder.overflow
in overflowstd_logic_vector (num_copies - 1 downto 0)
Definition: CMX_CP_Topo_Encoder.vhd:31
CMX_top_Base.P10_17
in P10_17std_logic
Definition: CMX_top_Base.vhd:358
daq_collector.din_lcl
in din_lclT_SLV60
Definition: daq_collector.vhd:28
CMX_top_Base.MP2_F06_QUAD_115_TRN_1_DIR
out MP2_F06_QUAD_115_TRN_1_DIRstd_logic
Definition: CMX_top_Base.vhd:751
CMX_top_Base.BF_DOUT_CTP_12
out BF_DOUT_CTP_12std_logic
Definition: CMX_top_Base.vhd:550
CMX_top_Base.D_CBL_45_B
out D_CBL_45_Bstd_logic
Definition: CMX_top_Base.vhd:653