1 ----------------------------------------------------------------------------------
7 ----------------------------------------------------------------------------------
9 use IEEE.STD_LOGIC_1164.
ALL;
10 use IEEE.NUMERIC_STD.
ALL;
13 use UNISIM.VComponents.
all;
26 ----------------------------------------------------------------------------
27 -- VME-- backplane (65 signals)
28 ----------------------------------------------------------------------------
29 --GEOADDR0: in std_logic; -- GeoAddr0
31 --VMEADDR: in std_logic_vector(23 downto 1); -- Address bus
55 --VMEDS_L: in std_logic; -- DS strobe VMEDS_L
57 --VMEWR_L: in std_logic; -- VME Write VMEWR_L
59 --VMERST_L: in std_logic; -- System reset VMERST_L
61 --VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA
62 OCB_D: inout (15 downto 0);
63 ----------------------------------------------------------------------------
493 --CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
494 --CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
503 --CLK_320MHz64_LHC_BF_LOGIC_DIR : in std_logic;
504 --CLK_320MHz64_LHC_BF_LOGIC_CMP : in std_logic;
761 --clk40 : in std_logic;
762 RXN_IN : in ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
763 RXP_IN : in ((num_GTX_per_group*num_GTX_groups)-1 downto 0)
773 attribute keep : ;
-- keep signals in synthesis
777 ------------------------------------------------------------------------------
778 -- VME interface component used in BSPT FPGA (Ian's vme_interface)
779 ------------------------------------------------------------------------------
782 clk40 :
IN ;
-- 40MHz Clk
791 -- signals for CMX_BASE_VME_INTERFACE component
792 signal ds: ;
-- board_ds output from VME (Ian model)
793 signal ncs: ;
-- brdsel_n output from VME (Ian model)
947 -- the first variable is
948 -- yet one more register
1004 P :
in mat_var (numactchan
-1 downto 0);
1009 ODATA :
out arr_4Xword (numactchan
-1 downto 0);
1033 --signal PAR_ERROR: std_logic_vector(numactchan-1 downto 0);
1038 signal data_from_vme_REG_RW_QUIET_FORCE : (15 downto 0);
1039 signal data_to_vme_REG_RW_QUIET_FORCE : (15 downto 0);
1041 signal DATA96 : arr_4Xword (numactchan-1 downto 0);
--96 bit data at 40MHz
1042 signal ODATA_first_half : arr_2Xword(numactchan-1 downto 0);
1044 signal P : mat_var (numactchan-1 downto 0);
1046 signal BF_DEBUG : (9 downto 0);
1048 signal counter_enable_inputmod_sig: (numactchan-1 downto 0);
1062 end component CMX_Memory_spy_inhibit;
1064 signal spy_write_inhibit : ;
1066 -- VME signal definitions
1067 signal data_from_vme_REG_RW_MISS_E_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1068 signal data_to_vme_REG_RW_MISS_E_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1070 signal data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1071 signal data_to_vme_REG_RW_MISS_E_RES_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1073 signal data_from_vme_REG_RW_SUM_ET_THR_BLOCK : arr_16(num_thresholds-1 downto 0);
1074 signal data_to_vme_REG_RW_SUM_ET_THR_BLOCK : arr_16(num_thresholds-1 downto 0);
1076 signal data_from_vme_REG_RW_SUM_ET_RES_THR_BLOCK : arr_16(num_thresholds-1 downto 0);
1077 signal data_to_vme_REG_RW_SUM_ET_RES_THR_BLOCK : arr_16(num_thresholds-1 downto 0);
1079 signal data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1080 signal data_to_vme_REG_RW_XS_T2_A2_THR_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1082 signal data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1083 signal data_to_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1085 signal data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1086 signal data_to_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK : arr_16((2*num_thresholds)-1 downto 0);
1088 signal data_from_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1089 signal data_to_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1091 signal data_from_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1092 signal data_to_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1094 signal data_from_vme_REG_RW_XS_B2_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1095 signal data_to_vme_REG_RW_XS_B2_PARAM_BLOCK : arr_16(num_thresholds-1 downto 0);
1105 MISS_E_THR :
in arr_ctr_31bit(num_thresholds
-1 downto 0);
1107 SUM_ET_THR :
in arr_ctr_15bit(num_thresholds
-1 downto 0);
1109 XS_T2_A2 :
in arr_ctr_31bit(num_thresholds
-1 downto 0);
1111 T_MISS_E_MIN :
in arr_ctr_31bit(num_thresholds
-1 downto 0);
1112 T_MISS_E_MAX :
in arr_ctr_31bit(num_thresholds
-1 downto 0);
1113 T_SUM_E_MIN :
in arr_ctr_15bit(num_thresholds
-1 downto 0);
1114 T_SUM_E_MAX :
in arr_ctr_15bit(num_thresholds
-1 downto 0);
1115 XS_B2 :
in arr_ctr_15bit(num_thresholds
-1 downto 0);
1125 par_err :
in (
1 downto 0);
-- parity error (input module - 0, RTM - 1)
1126 force :
in T_SL;
-- force
1127 ncs :
in ;
--ports forwarded to the vme register instances
1130 addr_vme :
in (
15 downto 0);
1131 data_vme_in :
in (
15 downto 0);
1132 data_vme_out :
out (
15 downto 0);
1135 end component CMX_Sum_Et;
1137 signal par_err : (1 downto 0);
1139 signal ENERGY_REMOTE : (26*4-1 downto 0);
1140 signal CTP_CABLE_0 : (23 downto 0);
1141 signal CTP_CABLE_1 : (23 downto 0);
1143 signal MISS_E_THR : arr_ctr_31bit(num_thresholds-1 downto 0);
1144 signal MISS_E_RES_THR : arr_ctr_31bit(num_thresholds-1 downto 0);
1145 signal SUM_ET_THR : arr_ctr_15bit(num_thresholds-1 downto 0);
1146 signal SUM_ET_RES_THR : arr_ctr_15bit(num_thresholds-1 downto 0);
1147 signal XS_T2_A2 : arr_ctr_31bit(num_thresholds-1 downto 0);
1149 signal T_MISS_E_MIN : arr_ctr_31bit(num_thresholds-1 downto 0);
1150 signal T_MISS_E_MAX : arr_ctr_31bit(num_thresholds-1 downto 0);
1151 signal T_SUM_E_MIN : arr_ctr_15bit(num_thresholds-1 downto 0);
1152 signal T_SUM_E_MAX : arr_ctr_15bit(num_thresholds-1 downto 0);
1153 signal XS_B2 : arr_ctr_15bit(num_thresholds-1 downto 0);
1156 signal slv_MISS_E_THR : arr_31(num_thresholds-1 downto 0);
1157 signal slv_MISS_E_RES_THR : arr_31(num_thresholds-1 downto 0);
1158 signal slv_SUM_ET_THR : arr_15(num_thresholds-1 downto 0);
1159 signal slv_SUM_ET_RES_THR : arr_15(num_thresholds-1 downto 0);
1160 signal slv_XS_T2_A2 : arr_31(num_thresholds-1 downto 0);
1162 signal slv_T_MISS_E_MIN : arr_31(num_thresholds-1 downto 0);
1163 signal slv_T_MISS_E_MAX : arr_31(num_thresholds-1 downto 0);
1164 signal slv_T_SUM_E_MIN : arr_15(num_thresholds-1 downto 0);
1165 signal slv_T_SUM_E_MAX : arr_15(num_thresholds-1 downto 0);
1166 signal slv_XS_B2 : arr_15(num_thresholds-1 downto 0);
1168 -- overflows and sums
1169 signal ov_all_out : (5 downto 0);
1170 signal sums_all_out : arr_ctr_15bit(5 downto 0);
1172 signal BACKPLANE_DATA_IN : energy_array;
1174 signal LOCAL_CABLE_OUT : (4*26-1 downto 0);
1177 signal ddr_data_in_RTM1 : (numbits_in_RTM_connector downto 0);
1178 signal ddr_data_in_RTM2 : (numbits_in_RTM_connector downto 0);
1179 signal sig_arr_RTM: arr_RTM(num_RTM_cables-1 downto 0);
1180 signal data_from_RTM : (numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1184 data :
out (numbits_in_RTM_connector*
2*num_RTM_cables
- 1 downto 0);
1186 ddr_data_in :
in arr_RTM(num_RTM_cables
-1 downto 0);
1200 end component CMX_system_cable_input_module;
1202 --component CMX_cable_clocked_80Mbps_input_module
1204 -- numbits_in_cable_connector : integer);
1206 -- data : out std_logic_vector((numbits_in_cable_connector*2)-1 downto 0);
1207 -- parity : out std_logic;
1208 -- forwarded_clock : out std_logic;
1209 -- ddr_data_in : in std_logic_vector(numbits_in_cable_connector downto 0);
1210 -- buf_clk40 : in std_logic;
1211 -- buf_clk200 : in std_logic;
1212 -- pll_locked : in std_logic;
1213 -- del_array : in cable_del_array_type(numbits_in_cable_connector downto 0);
1214 -- upload_delays : in std_logic);
1217 --signal forwarded_clock_CTP2 : std_logic;
1218 --signal data_CTP2 : std_logic_vector((numbits_in_CTP_connector*2)-1 downto 0);
1219 --signal parity_CTP2 : std_logic;
1220 --signal ddr_data_in_CTP2 : std_logic_vector(numbits_in_CTP_connector downto 0);
1222 --signal forwarded_clock_RTM3 : std_logic;
1223 --signal data_RTM3 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1224 --signal parity_RTM3 : std_logic;
1225 --signal ddr_data_in_RTM3 : std_logic_vector(numbits_in_RTM_connector downto 0);
1233 ncs :
in ;
--ports forwarded to the vme register instances
1241 signal BCID_counter_sig : (11 downto 0);
1242 signal BCID_delayed_decoder : (11 downto 0);
1243 signal BCID_delayed_daq : (11 downto 0);
1254 RXN_IN :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1255 RXP_IN :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1256 TXN_OUT :
out ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1257 TXP_OUT :
out ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1261 send_align :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1262 BCID :
in (
11 downto 0);
1263 indata :
in (TX_indata_length
-1 downto 0);
1272 end component Topo_Data_TX;
1277 send_align_out :
out (num_GTX_groups*num_GTX_per_group
- 1 downto 0);
1278 Data_out :
out (TX_indata_length
- 1 downto 0);
1282 end component CMX_SumET_Topo_Encoder;
1284 signal bcid_adj : (11 downto 0);
1286 signal TXN_OUT : ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1287 signal TXP_OUT : ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1289 signal MGTREFCLK_PAD_N_IN : (num_GTX_groups-1 downto 0);
1290 signal MGTREFCLK_PAD_P_IN : (num_GTX_groups-1 downto 0);
1292 signal GTX_RX_READY_OUT : ;
1293 signal GTX_TX_READY_OUT : ;
1296 signal GTXTXRESET_IN : ;
1297 signal GTXRXRESET_IN : ;
1299 signal send_align : (23 downto 0);
1301 signal indata_Topo_TX : (TX_indata_length-1 downto 0);
1303 signal data_to_vme_REG_RW_TOPOTR_GTX_RESET : (15 downto 0);
1304 signal data_from_vme_REG_RW_TOPOTR_GTX_RESET : (15 downto 0);
1306 signal data_to_vme_REG_RO_TOPOTR_GTX_STATUS : (15 downto 0);
1308 signal data_from_vme_REG_RW_DAQ_ROI_RESET : (15 downto 0);
1309 signal data_to_vme_REG_RW_DAQ_ROI_RESET : (15 downto 0);
1311 signal data_to_vme_REG_RO_DAQ_ROI_STATUS : (15 downto 0);
1313 signal data_from_vme_REG_RW_DAQ_ROI_GTX_RESET: (15 downto 0);
1314 signal data_to_vme_REG_RW_DAQ_ROI_GTX_RESET: (15 downto 0);
1315 signal gtx_reset_SFP_DAQ, gtx_reset_SFP_ROI : ;
1317 signal BUF_TTC_L1_ACCEPT_r: ;
1318 signal l1a_synced: ;
1321 signal bc_reset_synced : ;
1322 signal BUF_TTC_BNCH_CNT_RES_r : ;
1336 end component CMX_rate_counter_inhibit;
1338 signal counter_inhibit : ;
1339 signal counter_reset : ;
1341 --signal CONTROL2 : std_logic_vector(35 downto 0);
1344 --component chipscope_ila_CMX_top_inputmodclk
1346 -- CONTROL : inout std_logic_vector(35 downto 0);
1347 -- CLK : in std_logic;
1348 -- DATA : in std_logic_vector(2375 downto 0);
1349 -- TRIG0 : in std_logic_vector(35 downto 0));
1352 --signal DATA_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(2375 downto 0);
1353 --signal TRIG0_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(35 downto 0);
1354 ----signal TRIG_forward_inputmodclk_outputmodclk : std_logic_vector(0 downto 0);
1356 --component chipscope_ila_IDELAY
1358 -- CONTROL : inout std_logic_vector(35 downto 0);
1359 -- CLK : in std_logic;
1360 -- DATA : in std_logic_vector(2000 downto 0);
1361 -- TRIG0 : in std_logic_vector(0 to 0));
1364 --signal DATA_chipscope_ila_IDELAY : std_logic_vector(2000 downto 0);
1367 --component chipscope_ila_CTP2
1369 -- CONTROL : inout std_logic_vector(35 downto 0);
1370 -- CLK : in std_logic;
1371 -- DATA : in std_logic_vector(64 downto 0);
1372 -- TRIG0 : in std_logic_vector(0 to 0));
1375 --component chipscope_ila_RTM
1377 -- CONTROL : inout std_logic_vector(35 downto 0);
1378 -- CLK : in std_logic;
1379 -- DATA : in std_logic_vector(52 downto 0);
1380 -- TRIG0 : in std_logic_vector(0 to 0));
1383 --component chipscope_ila_LVDS_TX_CTP_RTM
1385 -- CONTROL : inout std_logic_vector(35 downto 0);
1386 -- CLK : in std_logic;
1387 -- DATA : in std_logic_vector(117 downto 0);
1388 -- TRIG0 : in std_logic_vector(1 downto 0));
1414 end component CMX_clock_manager;
1417 signal buf_clk40 : ;
1418 signal buf_clk40_m180o : ;
1419 signal buf_clk40_center : ;
1420 signal buf_clk320 : ;
1421 signal buf_clk160 : ;
1422 signal buf_clk200 : ;
1423 signal pll_locked : ;
1425 signal buf_clk40_ds2 : ;
1426 signal pll_locked_ds2 : ;
1446 data :
in ((numbits_in_CTP_connector*
2)
-1 downto 0);
1461 end component CMX_CTP_output_module;
1463 signal sdr_data_CTP: arr_CTP;
1464 signal data_to_CTP: ((numbits_in_CTP_connector*2)-1 downto 0);
1467 component CMX_CTP_out_tester
1469 sdr_data_out :
out (
31 downto 0);
1475 addr_vme :
in (
15 downto 0);
1476 data_vme :
inout (
15 downto 0));
1503 indata :
in (
7 downto 0);
1504 odata :
out (
7 downto 0);
1525 signal MGTREFCLK_Q118 : ;
1527 signal GTXTXRESET_IN_TX_SFP_DAQ : ;
1528 signal GTXRXRESET_IN_TX_SFP_DAQ : ;
1529 signal local_pll_lock_out_SFP_DAQ : ;
1530 signal GTX_TX_READY_OUT_TX_SFP_DAQ : ;
1531 signal GTX_RX_READY_OUT_TX_SFP_DAQ : ;
1532 signal PLLLKDET_diag_TX_SFP_DAQ : ;
1533 signal local_gtx_reset_diag_TX_SFP_DAQ : ;
1534 signal local_mmcm_reset_diag_TX_SFP_DAQ : ;
1535 signal GTXTEST_diag_TX_SFP_DAQ : ;
1536 signal RXN_IN_TX_SFP_DAQ : ;
1537 signal RXP_IN_TX_SFP_DAQ : ;
1538 signal TXN_OUT_TX_SFP_DAQ : ;
1539 signal TXP_OUT_TX_SFP_DAQ : ;
1540 signal clk40_out_TX_SFP_DAQ : ;
1541 signal clk120_out_TX_SFP_DAQ : ;
1542 signal clk40_in_TX_SFP_DAQ : ;
1543 signal clk120_in_TX_SFP_DAQ : ;
1544 signal indata_TX_SFP_DAQ : (7 downto 0);
1545 signal odata_TX_SFP_DAQ : (7 downto 0);
1546 signal TXPREEMPHASIS_IN_TX_SFP_DAQ : (3 downto 0);
1547 signal TXPOSTEMPHASIS_IN_TX_SFP_DAQ : (4 downto 0);
1548 signal TXDIFFCTRL_IN_TX_SFP_DAQ : (3 downto 0);
1549 signal RXEQMIX_IN_TX_SFP_DAQ : (2 downto 0);
1550 signal DFECLKDLYADJ_TX_SFP_DAQ : (5 downto 0);
1551 signal DFECLKDLYADJMON_TX_SFP_DAQ : (5 downto 0);
1552 signal DFEDLYOVRD_TX_SFP_DAQ : ;
1553 signal DFEEYEDACMON_TX_SFP_DAQ : (4 downto 0);
1554 signal DFESENSCAL_TX_SFP_DAQ : (2 downto 0);
1555 signal DFETAP1_TX_SFP_DAQ : (4 downto 0);
1556 signal DFETAP1MONITOR_TX_SFP_DAQ : (4 downto 0);
1557 signal DFETAP2_TX_SFP_DAQ : (4 downto 0);
1558 signal DFETAP2MONITOR_TX_SFP_DAQ : (4 downto 0);
1559 signal DFETAP3_TX_SFP_DAQ : (3 downto 0);
1560 signal DFETAP3MONITOR_TX_SFP_DAQ : (3 downto 0);
1561 signal DFETAP4_TX_SFP_DAQ : (3 downto 0);
1562 signal DFETAP4MONITOR_TX_SFP_DAQ : (3 downto 0);
1563 signal DFETAPOVRD_TX_SFP_DAQ : ;
1565 signal GTXTXRESET_IN_TX_SFP_ROI : ;
1566 signal GTXRXRESET_IN_TX_SFP_ROI : ;
1567 signal local_pll_lock_out_SFP_ROI : ;
1568 signal GTX_TX_READY_OUT_TX_SFP_ROI : ;
1569 signal GTX_RX_READY_OUT_TX_SFP_ROI : ;
1570 signal PLLLKDET_diag_TX_SFP_ROI : ;
1571 signal local_gtx_reset_diag_TX_SFP_ROI : ;
1572 signal local_mmcm_reset_diag_TX_SFP_ROI : ;
1573 signal GTXTEST_diag_TX_SFP_ROI : ;
1574 signal RXN_IN_TX_SFP_ROI : ;
1575 signal RXP_IN_TX_SFP_ROI : ;
1576 signal TXN_OUT_TX_SFP_ROI : ;
1577 signal TXP_OUT_TX_SFP_ROI : ;
1578 signal clk40_out_TX_SFP_ROI : ;
1579 signal clk120_out_TX_SFP_ROI : ;
1580 signal clk40_in_TX_SFP_ROI : ;
1581 signal clk120_in_TX_SFP_ROI : ;
1582 signal indata_TX_SFP_ROI : (7 downto 0);
1583 signal odata_TX_SFP_ROI : (7 downto 0);
1584 signal TXPREEMPHASIS_IN_TX_SFP_ROI : (3 downto 0);
1585 signal TXPOSTEMPHASIS_IN_TX_SFP_ROI : (4 downto 0);
1586 signal TXDIFFCTRL_IN_TX_SFP_ROI : (3 downto 0);
1587 signal RXEQMIX_IN_TX_SFP_ROI : (2 downto 0);
1588 signal DFECLKDLYADJ_TX_SFP_ROI : (5 downto 0);
1589 signal DFECLKDLYADJMON_TX_SFP_ROI : (5 downto 0);
1590 signal DFEDLYOVRD_TX_SFP_ROI : ;
1591 signal DFEEYEDACMON_TX_SFP_ROI : (4 downto 0);
1592 signal DFESENSCAL_TX_SFP_ROI : (2 downto 0);
1593 signal DFETAP1_TX_SFP_ROI : (4 downto 0);
1594 signal DFETAP1MONITOR_TX_SFP_ROI : (4 downto 0);
1595 signal DFETAP2_TX_SFP_ROI : (4 downto 0);
1596 signal DFETAP2MONITOR_TX_SFP_ROI : (4 downto 0);
1597 signal DFETAP3_TX_SFP_ROI : (3 downto 0);
1598 signal DFETAP3MONITOR_TX_SFP_ROI : (3 downto 0);
1599 signal DFETAP4_TX_SFP_ROI : (3 downto 0);
1600 signal DFETAP4MONITOR_TX_SFP_ROI : (3 downto 0);
1601 signal DFETAPOVRD_TX_SFP_ROI : ;
1611 DAQ_IN :
in (
19 DOWNTO 0);
1612 ROI_IN :
in (
19 DOWNTO 0);
1625 -- Glink emulator signals
1627 signal daq_in : (19 DOWNTO 0);
1628 signal roi_in : (19 DOWNTO 0);
1631 signal daq_byte : (7 downto 0);
1632 signal roi_byte : (7 downto 0);
1633 signal reset_daq : ;
1634 signal daq_encoded_diag : (23 downto 0);
1635 signal daq_byte_out : (1 downto 0);
1637 signal byte_pos_out : (5 downto 0);
1638 signal word_sel_out : (1 downto 0);
1639 signal readout_rst_out : ;
1641 -- masked out by Pawel Plucinski on 2015-04-28
1643 -- component chipscope_icon_u2_c3
1645 -- CONTROL0 : inout std_logic_vector(35 downto 0);
1646 -- CONTROL1 : inout std_logic_vector(35 downto 0);
1647 -- CONTROL2 : inout std_logic_vector(35 downto 0)
1651 -- signal CONTROL0 : std_logic_vector(35 downto 0);
1652 -- signal CONTROL1 : std_logic_vector(35 downto 0);
1653 -- signal CONTROL2 : std_logic_vector(35 downto 0);
1655 -- signal data_ila_daq : std_logic_vector (53 downto 0);
1656 -- signal trig_ila_daq : std_logic_vector (33 downto 0);
1658 -- signal data_ila_encoder : std_logic_vector (20 downto 0);
1659 -- signal trig_ila_encoder : std_logic_vector (11 downto 0);
1661 -- signal data_ila_gtx_start : std_logic_vector (12 downto 0);
1662 -- signal trig_ila_gtx_start : std_logic_vector (2 downto 0);
1665 --signal data_ila_1 : std_logic_vector (16 downto 0);
1667 -- component glink_chipscope_analyzer
1669 -- CONTROL: inout std_logic_vector(35 downto 0);
1670 -- CLK: in std_logic;
1671 -- DATA: in std_logic_vector(53 downto 0);
1672 -- TRIG0: in std_logic_vector(33 downto 0));
1675 -- component glink_chipscope_analyzer_encoder
1677 -- CONTROL: inout std_logic_vector(35 downto 0);
1678 -- CLK: in std_logic;
1679 -- DATA: in std_logic_vector(20 downto 0);
1680 -- TRIG0: in std_logic_vector(11 downto 0));
1683 -- component glink_chipscope_analyzer_gtx_start is
1685 -- CONTROL : inout std_logic_vector(35 downto 0);
1686 -- CLK : in std_logic;
1687 -- DATA : in std_logic_vector(10 downto 0);
1688 -- TRIG0 : in std_logic_vector(0 to 0));
1689 -- end component glink_chipscope_analyzer_gtx_start;
1695 data_in :
in arr_96(
19 downto 0);
1709 signal RAM_global_offset : (7 downto 0);
1710 signal RAM_rel_offsets : arr_ctr_8bit(18 downto 0);
1711 signal nslices : (7 downto 0);
1713 signal data_in_daq: arr_96(19 downto 0);
1715 --control of daq delays
1716 signal data_from_vme_REG_RW_DAQ_SLICE: (15 downto 0);
1717 signal data_to_vme_REG_RW_DAQ_SLICE: (15 downto 0);
1718 signal data_from_vme_REG_RW_DAQ_RAM_OFFSET: (15 downto 0);
1719 signal data_to_vme_REG_RW_DAQ_RAM_OFFSET: (15 downto 0);
1721 signal data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1722 signal data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1725 attribute keep of start_playback_r1, BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r, send_align: signal is "TRUE";
--, ODATA_first_half
1726 attribute IOB of BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r : signal is "FORCE";
1729 --attribute IOB of BF_DOUT_CTP_00 : signal is "TRUE";
1730 --attribute IOB of BF_DOUT_CTP_01 : signal is "TRUE";
1731 --attribute IOB of BF_DOUT_CTP_02 : signal is "TRUE";
1732 --attribute IOB of BF_DOUT_CTP_03 : signal is "TRUE";
1733 --attribute IOB of BF_DOUT_CTP_04 : signal is "TRUE";
1734 --attribute IOB of BF_DOUT_CTP_05 : signal is "TRUE";
1735 --attribute IOB of BF_DOUT_CTP_06 : signal is "TRUE";
1736 --attribute IOB of BF_DOUT_CTP_07 : signal is "TRUE";
1737 --attribute IOB of BF_DOUT_CTP_08 : signal is "TRUE";
1738 --attribute IOB of BF_DOUT_CTP_09 : signal is "TRUE";
1739 --attribute IOB of BF_DOUT_CTP_10 : signal is "TRUE";
1740 --attribute IOB of BF_DOUT_CTP_11 : signal is "TRUE";
1741 --attribute IOB of BF_DOUT_CTP_12 : signal is "TRUE";
1742 --attribute IOB of BF_DOUT_CTP_13 : signal is "TRUE";
1743 --attribute IOB of BF_DOUT_CTP_14 : signal is "TRUE";
1744 --attribute IOB of BF_DOUT_CTP_15 : signal is "TRUE";
1745 --attribute IOB of BF_DOUT_CTP_16 : signal is "TRUE";
1746 --attribute IOB of BF_DOUT_CTP_17 : signal is "TRUE";
1747 --attribute IOB of BF_DOUT_CTP_18 : signal is "TRUE";
1748 --attribute IOB of BF_DOUT_CTP_19 : signal is "TRUE";
1749 --attribute IOB of BF_DOUT_CTP_20 : signal is "TRUE";
1750 --attribute IOB of BF_DOUT_CTP_21 : signal is "TRUE";
1751 --attribute IOB of BF_DOUT_CTP_22 : signal is "TRUE";
1752 --attribute IOB of BF_DOUT_CTP_23 : signal is "TRUE";
1753 --attribute IOB of BF_DOUT_CTP_24 : signal is "TRUE";
1754 --attribute IOB of BF_DOUT_CTP_25 : signal is "TRUE";
1755 --attribute IOB of BF_DOUT_CTP_26 : signal is "TRUE";
1756 --attribute IOB of BF_DOUT_CTP_27 : signal is "TRUE";
1757 --attribute IOB of BF_DOUT_CTP_28 : signal is "TRUE";
1758 --attribute IOB of BF_DOUT_CTP_29 : signal is "TRUE";
1759 --attribute IOB of BF_DOUT_CTP_64 : signal is "TRUE";
1761 --attribute IOB of BF_DOUT_CTP_32 : signal is "TRUE";
1762 --attribute IOB of BF_DOUT_CTP_33 : signal is "TRUE";
1763 --attribute IOB of BF_DOUT_CTP_34 : signal is "TRUE";
1764 --attribute IOB of BF_DOUT_CTP_35 : signal is "TRUE";
1765 --attribute IOB of BF_DOUT_CTP_36 : signal is "TRUE";
1766 --attribute IOB of BF_DOUT_CTP_37 : signal is "TRUE";
1767 --attribute IOB of BF_DOUT_CTP_38 : signal is "TRUE";
1768 --attribute IOB of BF_DOUT_CTP_39 : signal is "TRUE";
1769 --attribute IOB of BF_DOUT_CTP_40 : signal is "TRUE";
1770 --attribute IOB of BF_DOUT_CTP_41 : signal is "TRUE";
1771 --attribute IOB of BF_DOUT_CTP_42 : signal is "TRUE";
1772 --attribute IOB of BF_DOUT_CTP_43 : signal is "TRUE";
1773 --attribute IOB of BF_DOUT_CTP_44 : signal is "TRUE";
1774 --attribute IOB of BF_DOUT_CTP_45 : signal is "TRUE";
1775 --attribute IOB of BF_DOUT_CTP_46 : signal is "TRUE";
1776 --attribute IOB of BF_DOUT_CTP_47 : signal is "TRUE";
1777 --attribute IOB of BF_DOUT_CTP_48 : signal is "TRUE";
1778 --attribute IOB of BF_DOUT_CTP_49 : signal is "TRUE";
1779 --attribute IOB of BF_DOUT_CTP_50 : signal is "TRUE";
1780 --attribute IOB of BF_DOUT_CTP_51 : signal is "TRUE";
1781 --attribute IOB of BF_DOUT_CTP_52 : signal is "TRUE";
1782 --attribute IOB of BF_DOUT_CTP_53 : signal is "TRUE";
1783 --attribute IOB of BF_DOUT_CTP_54 : signal is "TRUE";
1784 --attribute IOB of BF_DOUT_CTP_55 : signal is "TRUE";
1785 --attribute IOB of BF_DOUT_CTP_56 : signal is "TRUE";
1786 --attribute IOB of BF_DOUT_CTP_57 : signal is "TRUE";
1787 --attribute IOB of BF_DOUT_CTP_58 : signal is "TRUE";
1788 --attribute IOB of BF_DOUT_CTP_59 : signal is "TRUE";
1789 --attribute IOB of BF_DOUT_CTP_60 : signal is "TRUE";
1790 --attribute IOB of BF_DOUT_CTP_61 : signal is "TRUE";
1813 --BF_TO_FROM_BSPT_0 <= '0';
1814 --BF_TO_FROM_BSPT_1 <= '0';
1899 --ddr_data_in_CTP2(0) <=BF_DOUT_CTP_32;
1900 --ddr_data_in_CTP2(1) <=BF_DOUT_CTP_33;
1901 --ddr_data_in_CTP2(2) <=BF_DOUT_CTP_34;
1902 --ddr_data_in_CTP2(3) <=BF_DOUT_CTP_35;
1903 --ddr_data_in_CTP2(4) <=BF_DOUT_CTP_36;
1904 --ddr_data_in_CTP2(5) <=BF_DOUT_CTP_37;
1905 --ddr_data_in_CTP2(6) <=BF_DOUT_CTP_38;
1906 --ddr_data_in_CTP2(7) <=BF_DOUT_CTP_39;
1907 --ddr_data_in_CTP2(8) <=BF_DOUT_CTP_40;
1908 --ddr_data_in_CTP2(9) <=BF_DOUT_CTP_41;
1909 --ddr_data_in_CTP2(10) <=BF_DOUT_CTP_42;
1910 --ddr_data_in_CTP2(11) <=BF_DOUT_CTP_43;
1911 --ddr_data_in_CTP2(12) <=BF_DOUT_CTP_44;
1912 --ddr_data_in_CTP2(13) <=BF_DOUT_CTP_45;
1913 --ddr_data_in_CTP2(14) <=BF_DOUT_CTP_46;
1914 --ddr_data_in_CTP2(15) <=BF_DOUT_CTP_47;
1915 --ddr_data_in_CTP2(16) <=BF_DOUT_CTP_48;
1916 --ddr_data_in_CTP2(17) <=BF_DOUT_CTP_49;
1917 --ddr_data_in_CTP2(18) <=BF_DOUT_CTP_50;
1918 --ddr_data_in_CTP2(19) <=BF_DOUT_CTP_51;
1919 --ddr_data_in_CTP2(20) <=BF_DOUT_CTP_52;
1920 --ddr_data_in_CTP2(21) <=BF_DOUT_CTP_53;
1921 --ddr_data_in_CTP2(22) <=BF_DOUT_CTP_54;
1922 --ddr_data_in_CTP2(23) <=BF_DOUT_CTP_55;
1923 --ddr_data_in_CTP2(24) <=BF_DOUT_CTP_56;
1924 --ddr_data_in_CTP2(25) <=BF_DOUT_CTP_57;
1925 --ddr_data_in_CTP2(26) <=BF_DOUT_CTP_58;
1926 --ddr_data_in_CTP2(27) <=BF_DOUT_CTP_59;
1927 --ddr_data_in_CTP2(28) <=BF_DOUT_CTP_60;
1928 --ddr_data_in_CTP2(29) <=BF_DOUT_CTP_61;
1929 --ddr_data_in_CTP2(30) <=BF_DOUT_CTP_62;
1930 --ddr_data_in_CTP2(31) <=BF_DOUT_CTP_65;
1931 --ddr_data_in_CTP2(32) <=BF_DOUT_CTP_63;
1992 sig_arr_RTM(0)<=ddr_data_in_RTM1;
1993 sig_arr_RTM(1)<=ddr_data_in_RTM2;
1995 --D_CBL_81_B <= '0';
1996 --D_CBL_82_B <= '0';
1998 --BF_TO_TP_DAQ_SLINK_RETURN_DIR ;--<= '0';
1999 --BF_TO_TP_DAQ_SLINK_RETURN_CMP ;--<= '0';
2000 --BF_TO_TP_ROI_SLINK_RETURN_DIR ;--<= '0';
2001 --BF_TO_TP_ROI_SLINK_RETURN_CMP ;--<= '0';
2004 --backplane bus assignment
2464 --debug pins bus assignment
2477 ODDR_inst_buf_clk_40 : ODDR
2479 DDR_CLK_EDGE =>
"SAME_EDGE",
-- "OPPOSITE_EDGE" or "SAME_EDGE"
2480 INIT => '0',
-- Initial value for Q port ('1' or '0')
2481 SRTYPE =>
"SYNC") -- Reset Type ("ASYNC" or "SYNC")
2483 Q => BF_DEBUG
(8),
-- 1-bit DDR output
2484 C => buf_clk40,
-- 1-bit clock input
2485 CE => '1',
-- 1-bit clock enable input
2486 D1 => '1',
-- 1-bit data input (positive edge)
2487 D2 => '0',
-- 1-bit data input (negative edge)
2488 R =>
(not pll_locked
),
-- 1-bit reset input
2489 S => '0'
-- 1-bit set input
2492 ODDR_inst_buf_clk_40_ds2 : ODDR
2494 DDR_CLK_EDGE =>
"SAME_EDGE",
-- "OPPOSITE_EDGE" or "SAME_EDGE"
2495 INIT => '0',
-- Initial value for Q port ('1' or '0')
2496 SRTYPE =>
"SYNC") -- Reset Type ("ASYNC" or "SYNC")
2498 Q => BF_DEBUG
(9),
-- 1-bit DDR output
2499 C => buf_clk40_ds2,
-- 1-bit clock input
2500 CE => '1',
-- 1-bit clock enable input
2501 D1 => '1',
-- 1-bit data input (positive edge)
2502 D2 => '0',
-- 1-bit data input (negative edge)
2503 R =>
(not pll_locked_ds2
),
-- 1-bit reset input
2504 S => '0'
-- 1-bit set input
2508 --BF_DEBUG(8) <= buf_clk40;
2509 --BF_DEBUG(9) <= DATA96(5)(0);--start_playback;--BF_TO_TP_DAQ_SLINK_RETURN_DIR;--send_align(0);-- BUF_TTC_BNCH_CNT_RES; --bunch counter reset
2511 BF_DEBUG(7 downto 0)<=(others=>'0');
2537 ------------------------------------------------------------------------------
2538 -- VME interface component used in BSPT FPGA (Ian's vme_interface)
2539 ------------------------------------------------------------------------------
2542 ----------------------------------------------------------------------------
2544 ----------------------------------------------------------------------------
2545 clk40 => buf_clk40 ,
2551 ----------------------------------------------------------------------------
2553 ----------------------------------------------------------------------------
2554 board_ds =>
ds,
-- board_ds output from VME (Ian model)
2555 brdsel_n =>
ncs -- brdsel_n output from VME (Ian model)
2578 clk40 => buf_clk40 ,
2628 if rising_edge(buf_clk40) then
2642 ia_vme => ADDR_REG_RO_test ,
2655 --vme_outreg_test: vme_outreg
2657 -- ia_vme => ADDR_REG_RO_test,
2660 -- clk => buf_clk40,
2661 -- addr_vme => vme_address(16 downto 1),
2663 -- rd_nwr => OCB_WRITE_B,
2665 -- data_to_vme => data_to_vme_test_r,
2666 -- read_detect => read_detect_outreg_test,
2667 -- data_vme => OCB_D);
2672 ia_vme => ADDR_REG_RW_test ,
2688 --vme_inreg_test: vme_inreg
2690 -- ia_vme => ADDR_REG_RW_test,
2693 -- clk => buf_clk40,
2695 -- rd_nwr => OCB_WRITE_B,
2697 -- data_from_vme => data_from_vme_test_rw,
2698 -- data_to_vme => data_to_vme_test_rw,
2699 -- addr_vme => vme_address(16 downto 1),
2700 -- read_detect => read_detect_inreg_test,
2701 -- write_detect => write_detect_inreg_test,
2702 -- data_vme => OCB_D);
2706 --chipscope_ila_CMX_top_inputmodclk_inst: chipscope_ila_CMX_top_inputmodclk
2708 -- CONTROL => CONTROL0,
2709 -- CLK => buf_clk40,
2710 -- DATA => DATA_chipscope_ila_CMX_top_inputmodclk,
2711 -- TRIG0 => TRIG0_chipscope_ila_CMX_top_inputmodclk);
2713 --TRIG0_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2714 --TRIG0_chipscope_ila_CMX_top_inputmodclk(33)<=start_playback;
2715 --TRIG0_chipscope_ila_CMX_top_inputmodclk(34)<=data_to_CTP(0);
2716 --TRIG0_chipscope_ila_CMX_top_inputmodclk(35)<=data_from_RTM(0);
2719 --DATA_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2721 --gen_data_chipscope_ila: for ichannel in numactchan-1 downto 0 generate
2723 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(1+ichannel*2)<=PAR_ERROR(ichannel);
2724 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(2+ichannel*2)<=counter_enable_inputmod_sig(ichannel);
2726 -- DATA_chipscope_ila_CMX_top_inputmodclk(1+ichannel*98)<=PAR_ERROR(ichannel);
2727 -- DATA_chipscope_ila_CMX_top_inputmodclk(2+ichannel*98)<=counter_enable_inputmod_sig(ichannel);
2728 -- DATA_chipscope_ila_CMX_top_inputmodclk(95+3+ichannel*98 downto 3+ichannel*98)<=DATA96(ichannel);
2730 --end generate gen_data_chipscope_ila;
2734 --DATA_chipscope_ila_CMX_top_inputmodclk(1630 downto 1569)<=data_to_CTP;
2735 --DATA_chipscope_ila_CMX_top_inputmodclk(1734 downto 1631)<=data_from_RTM;
2736 --DATA_chipscope_ila_CMX_top_inputmodclk(1735)<=start_playback;
2737 --DATA_chipscope_ila_CMX_top_inputmodclk(2375 downto 1736)<=(others=>'0');
2740 --chipscope_ila_IDELAY_1: chipscope_ila_IDELAY
2742 -- CONTROL => CONTROL1,
2743 -- CLK => buf_clk40,
2744 -- DATA => DATA_chipscope_ila_IDELAY,
2745 -- TRIG0(0) => upload_delays);
2747 --gen_chipscpe_data_idelay_ichan: for ichan in numactchan-1 downto 0 generate
2748 -- --no -1 because the clock adds one:
2749 -- gen_chipscpe_data_idelay_ibit: for ibit in numbitsinchan downto 0 generate
2750 -- DATA_chipscope_ila_IDELAY( (ichan*(numbitsinchan+1)+ibit)*5 + 4 downto (ichan*(numbitsinchan+1)+ibit)*5)<=
2751 -- del_register(ichan,ibit);
2752 -- end generate gen_chipscpe_data_idelay_ibit;
2753 --end generate gen_chipscpe_data_idelay_ichan;
2754 --DATA_chipscope_ila_IDELAY(2000)<=upload_delays;
2760 clk40 => buf_clk40 ,
2771 --upload_delays<='0';
2772 --del_register<=(others=>(others=>(others=>'0')));
2776 reset => bc_reset_synced ,
2791 if rising_edge(buf_clk40) then
2806 --ODATA_WORD0 => open,
2827 ia_vme => ADDR_REG_RW_QUIET_FORCE ,
2840 data_to_vme_REG_RW_QUIET_FORCE<=data_from_vme_REG_RW_QUIET_FORCE;
2841 quiet<=data_from_vme_REG_RW_QUIET_FORCE(1);
2842 force<=data_from_vme_REG_RW_QUIET_FORCE(0);
2858 --no decoder in the sense of jet/cp sense
2859 --zero out the bus slot that is not used in this flavor
2863 gen_data_vme_bus_drive_zeros: for i in 0 to 1599 generate
2866 end generate gen_data_vme_bus_drive_zeros;
2906 -- ===========================================================================================
2910 -- ===========================================================================================
2912 gen_REG_RW_MISS_E_THR_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
2916 ia_vme => ADDR_REG_RW_MISS_E_THR_BLOCK+2*i_thr,
2926 data_from_vme => data_from_vme_REG_RW_MISS_E_THR_BLOCK
(i_thr
),
2927 data_to_vme => data_to_vme_REG_RW_MISS_E_THR_BLOCK
(i_thr
));
2929 data_to_vme_REG_RW_MISS_E_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_MISS_E_THR_BLOCK(i_thr);
2931 end generate gen_REG_RW_MISS_E_THR_BLOCK;
2933 gen_MISS_E_THR: for i_thr in 0 to num_thresholds-1 generate
2934 MISS_E_THR(i_thr)<= (slv_MISS_E_THR(i_thr));
2935 slv_MISS_E_THR(i_thr)(15 downto 0) <= data_from_vme_REG_RW_MISS_E_THR_BLOCK(2*i_thr)(15 downto 0);
2936 slv_MISS_E_THR(i_thr)(30 downto 16) <= data_from_vme_REG_RW_MISS_E_THR_BLOCK(2*i_thr+1)(14 downto 0);
2937 end generate gen_MISS_E_THR;
2940 -- ===========================================================================================
2944 -- ===========================================================================================
2946 gen_REG_RW_MISS_E_RES_THR_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
2950 ia_vme => ADDR_REG_RW_MISS_E_RES_THR_BLOCK+2*i_thr,
2960 data_from_vme => data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK
(i_thr
),
2961 data_to_vme => data_to_vme_REG_RW_MISS_E_RES_THR_BLOCK
(i_thr
));
2963 data_to_vme_REG_RW_MISS_E_RES_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK(i_thr);
2965 end generate gen_REG_RW_MISS_E_RES_THR_BLOCK;
2967 gen_MISS_E_RES_THR: for i_thr in 0 to num_thresholds-1 generate
2968 MISS_E_RES_THR(i_thr)<=(slv_MISS_E_RES_THR(i_thr));
2969 slv_MISS_E_RES_THR(i_thr)(15 downto 0) <= data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK(2*i_thr)(15 downto 0);
2970 slv_MISS_E_RES_THR(i_thr)(30 downto 16) <= data_from_vme_REG_RW_MISS_E_RES_THR_BLOCK(2*i_thr+1)(14 downto 0);
2971 end generate gen_MISS_E_RES_THR;
2973 -- ===========================================================================================
2977 -- ===========================================================================================
2979 gen_REG_RW_SUM_ET_THR_BLOCK: for i_thr in 0 to num_thresholds-1 generate
2983 ia_vme => ADDR_REG_RW_SUM_ET_THR_BLOCK+2*i_thr,
2993 data_from_vme => data_from_vme_REG_RW_SUM_ET_THR_BLOCK
(i_thr
),
2994 data_to_vme => data_to_vme_REG_RW_SUM_ET_THR_BLOCK
(i_thr
));
2996 data_to_vme_REG_RW_SUM_ET_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_SUM_ET_THR_BLOCK(i_thr);
2997 SUM_ET_THR(i_thr)<=(slv_SUM_ET_THR(i_thr));
2998 slv_SUM_ET_THR(i_thr) <= data_from_vme_REG_RW_SUM_ET_THR_BLOCK(i_thr)(14 downto 0);
3000 end generate gen_REG_RW_SUM_ET_THR_BLOCK;
3002 -- ===========================================================================================
3006 -- ===========================================================================================
3009 gen_REG_RW_SUM_ET_RES_THR_BLOCK: for i_thr in 0 to num_thresholds-1 generate
3013 ia_vme => ADDR_REG_RW_SUM_ET_RES_THR_BLOCK+2*i_thr,
3023 data_from_vme => data_from_vme_REG_RW_SUM_ET_RES_THR_BLOCK
(i_thr
),
3024 data_to_vme => data_to_vme_REG_RW_SUM_ET_RES_THR_BLOCK
(i_thr
));
3026 data_to_vme_REG_RW_SUM_ET_RES_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_SUM_ET_RES_THR_BLOCK(i_thr);
3027 SUM_ET_RES_THR(i_thr)<=(slv_SUM_ET_RES_THR(i_thr));
3028 slv_SUM_ET_RES_THR(i_thr) <= data_from_vme_REG_RW_SUM_ET_RES_THR_BLOCK(i_thr)(14 downto 0);
3030 end generate gen_REG_RW_SUM_ET_RES_THR_BLOCK;
3032 -- ===========================================================================================
3036 -- ===========================================================================================
3038 gen_REG_RW_XS_T2_A2_THR_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
3042 ia_vme => ADDR_REG_RW_XS_T2_A2_THR_BLOCK+2*i_thr,
3052 data_from_vme => data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK
(i_thr
),
3053 data_to_vme => data_to_vme_REG_RW_XS_T2_A2_THR_BLOCK
(i_thr
));
3055 data_to_vme_REG_RW_XS_T2_A2_THR_BLOCK(i_thr)<=data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK(i_thr);
3057 end generate gen_REG_RW_XS_T2_A2_THR_BLOCK;
3059 gen_XS_T2_A2_THR: for i_thr in 0 to num_thresholds-1 generate
3060 XS_T2_A2(i_thr)<=(slv_XS_T2_A2(i_thr));
3061 slv_XS_T2_A2(i_thr)(15 downto 0) <= data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK(2*i_thr)(15 downto 0);
3062 slv_XS_T2_A2(i_thr)(30 downto 16) <= data_from_vme_REG_RW_XS_T2_A2_THR_BLOCK(2*i_thr+1)(14 downto 0);
3063 end generate gen_XS_T2_A2_THR;
3065 -- ===========================================================================================
3069 -- ===========================================================================================
3071 gen_REG_RW_T_MISS_E_MIN_PARAM_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
3075 ia_vme => ADDR_REG_RW_T_MISS_E_MIN_PARAM_BLOCK+2*i_thr,
3085 data_from_vme => data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK
(i_thr
),
3086 data_to_vme => data_to_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK
(i_thr
));
3088 data_to_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(i_thr);
3090 end generate gen_REG_RW_T_MISS_E_MIN_PARAM_BLOCK;
3092 gen_T_MISS_E_MIN_PARAM: for i_thr in 0 to num_thresholds-1 generate
3093 T_MISS_E_MIN(i_thr)<=(slv_T_MISS_E_MIN(i_thr));
3094 slv_T_MISS_E_MIN(i_thr)(15 downto 0) <= data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(2*i_thr)(15 downto 0);
3095 slv_T_MISS_E_MIN(i_thr)(30 downto 16) <= data_from_vme_REG_RW_T_MISS_E_MIN_PARAM_BLOCK(2*i_thr+1)(14 downto 0);
3096 end generate gen_T_MISS_E_MIN_PARAM;
3098 -- ===========================================================================================
3102 -- ===========================================================================================
3105 gen_REG_RW_T_MISS_E_MAX_PARAM_BLOCK: for i_thr in 0 to (2*num_thresholds)-1 generate
3109 ia_vme => ADDR_REG_RW_T_MISS_E_MAX_PARAM_BLOCK+2*i_thr,
3119 data_from_vme => data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK
(i_thr
),
3120 data_to_vme => data_to_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK
(i_thr
));
3122 data_to_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(i_thr);
3124 end generate gen_REG_RW_T_MISS_E_MAX_PARAM_BLOCK;
3126 gen_T_MISS_E_MAX_PARAM: for i_thr in 0 to num_thresholds-1 generate
3127 T_MISS_E_MAX(i_thr)<=(slv_T_MISS_E_MAX(i_thr));
3128 slv_T_MISS_E_MAX(i_thr)(15 downto 0) <= data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(2*i_thr)(15 downto 0);
3129 slv_T_MISS_E_MAX(i_thr)(30 downto 16) <= data_from_vme_REG_RW_T_MISS_E_MAX_PARAM_BLOCK(2*i_thr+1)(14 downto 0);
3130 end generate gen_T_MISS_E_MAX_PARAM;
3132 -- ===========================================================================================
3136 -- ===========================================================================================
3139 gen_REG_RW_T_SUM_E_MIN_PARAM_BLOCK: for i_thr in 0 to num_thresholds-1 generate
3143 ia_vme => ADDR_REG_RW_T_SUM_E_MIN_PARAM_BLOCK+2*i_thr,
3153 data_from_vme => data_from_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK
(i_thr
),
3154 data_to_vme => data_to_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK
(i_thr
));
3156 data_to_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK(i_thr);
3158 T_SUM_E_MIN(i_thr)<=(slv_T_SUM_E_MIN(i_thr));
3159 slv_T_SUM_E_MIN(i_thr) <= data_from_vme_REG_RW_T_SUM_E_MIN_PARAM_BLOCK(i_thr)(14 downto 0);
3161 end generate gen_REG_RW_T_SUM_E_MIN_PARAM_BLOCK;
3163 -- ===========================================================================================
3167 -- ===========================================================================================
3170 gen_REG_RW_T_SUM_E_MAX_PARAM_BLOCK: for i_thr in 0 to num_thresholds-1 generate
3174 ia_vme => ADDR_REG_RW_T_SUM_E_MAX_PARAM_BLOCK+2*i_thr,
3184 data_from_vme => data_from_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK
(i_thr
),
3185 data_to_vme => data_to_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK
(i_thr
));
3187 data_to_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK(i_thr);
3188 T_SUM_E_MAX(i_thr)<=(slv_T_SUM_E_MAX(i_thr));
3189 slv_T_SUM_E_MAX(i_thr) <= data_from_vme_REG_RW_T_SUM_E_MAX_PARAM_BLOCK(i_thr)(14 downto 0);
3191 end generate gen_REG_RW_T_SUM_E_MAX_PARAM_BLOCK;
3193 -- ===========================================================================================
3197 -- ===========================================================================================
3200 gen_REG_RW_XS_B2_PARAM_BLOCK: for i_thr in 0 to num_thresholds-1 generate
3204 ia_vme => ADDR_REG_RW_XS_B2_PARAM_BLOCK+2*i_thr,
3214 data_from_vme => data_from_vme_REG_RW_XS_B2_PARAM_BLOCK
(i_thr
),
3215 data_to_vme => data_to_vme_REG_RW_XS_B2_PARAM_BLOCK
(i_thr
));
3217 data_to_vme_REG_RW_XS_B2_PARAM_BLOCK(i_thr)<=data_from_vme_REG_RW_XS_B2_PARAM_BLOCK(i_thr);
3218 XS_B2(i_thr)<=(slv_XS_B2(i_thr));
3219 slv_XS_B2(i_thr) <= data_from_vme_REG_RW_XS_B2_PARAM_BLOCK(i_thr)(14 downto 0);
3221 end generate gen_REG_RW_XS_B2_PARAM_BLOCK;
3223 -- ===========================================================================================
3227 -- ===========================================================================================
3229 gen_ET_data : for ch in numactchan-1 downto 0 generate
3230 BACKPLANE_DATA_IN(ch)(13 downto 0)<=DATA96(ch)(13 downto 0);
3231 BACKPLANE_DATA_IN(ch)(27 downto 14)<=DATA96(ch)(37 downto 24);
3232 BACKPLANE_DATA_IN(ch)(41 downto 28)<=DATA96(ch)(61 downto 48);
3233 end generate gen_ET_data;
3235 ENERGY_REMOTE<=data_from_RTM;
3237 data_to_CTP(23 downto 0)<=CTP_CABLE_0;
3238 data_to_CTP(30)<=xor_reduce(CTP_CABLE_0) xor '1';
3239 data_to_CTP(29 downto 24)<=(others=>'0');
3241 data_to_CTP(54 downto 31)<=CTP_CABLE_1;
3242 data_to_CTP(61)<=xor_reduce(CTP_CABLE_1) xor '1';
3243 data_to_CTP(60 downto 55)<=(others=>'0');
3248 data => data_to_CTP,
3268 data => data_from_RTM,
3286 --chipscope_ila_LVDS_TX_CTP_RTM_inst: chipscope_ila_LVDS_TX_CTP_RTM
3288 -- CONTROL => CONTROL1,
3289 -- CLK => buf_clk40,
3290 -- DATA(31 downto 0) => sdr_data_out,
3291 -- DATA(63 downto 32) => (others=>'0'),
3292 -- DATA(115 downto 64) => data_RTM,
3293 -- DATA(116) => '0',
3294 -- DATA(117) => '0',
3330 --CMX_Jet_Topo_Encoder_inst: CMX_Jet_Topo_Encoder
3332 -- DATA_Et1 => tot_Et1,
3333 -- DATA_Et2 => tot_Et2,
3334 -- DATA_pos => tot_pos,
3335 -- overflow => overflow,
3336 -- send_align_out => send_align,
3337 -- Data_out => indata_Topo_TX);
3358 indata => indata_Topo_TX ,
3375 bcid_in => BCID_delayed_decoder ,
3382 ia_vme => ADDR_REG_RW_TOPOTR_GTX_RESET ,
3393 data_to_vme => data_to_vme_REG_RW_TOPOTR_GTX_RESET
3396 GTXTXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(1);
3397 GTXRXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(0);
3399 data_to_vme_REG_RW_TOPOTR_GTX_RESET<=data_from_vme_REG_RW_TOPOTR_GTX_RESET;
3404 ia_vme => ADDR_REG_RO_TOPOTR_GTX_STATUS ,
3413 data_to_vme => data_to_vme_REG_RO_TOPOTR_GTX_STATUS
);
3415 data_to_vme_REG_RO_TOPOTR_GTX_STATUS(1)<=GTX_TX_READY_OUT;
3416 data_to_vme_REG_RO_TOPOTR_GTX_STATUS(0)<=GTX_RX_READY_OUT;
3418 data_to_vme_REG_RO_TOPOTR_GTX_STATUS(15 downto 2)<=(others=>'0');
3437 RXN_IN => RXN_IN_TX_SFP_DAQ ,
3438 RXP_IN => RXP_IN_TX_SFP_DAQ ,
3439 TXN_OUT => TXN_OUT_TX_SFP_DAQ,
3440 TXP_OUT => TXP_OUT_TX_SFP_DAQ,
3445 indata => indata_TX_SFP_DAQ ,
3446 odata => odata_TX_SFP_DAQ ,
3456 DFETAP1 => DFETAP1_TX_SFP_DAQ,
3458 DFETAP2 => DFETAP2_TX_SFP_DAQ,
3460 DFETAP3 => DFETAP3_TX_SFP_DAQ,
3462 DFETAP4 => DFETAP4_TX_SFP_DAQ,
3481 RXN_IN => RXN_IN_TX_SFP_ROI ,
3482 RXP_IN => RXP_IN_TX_SFP_ROI ,
3483 TXN_OUT => TXN_OUT_TX_SFP_ROI,
3484 TXP_OUT => TXP_OUT_TX_SFP_ROI,
3489 indata => indata_TX_SFP_ROI ,
3490 odata => odata_TX_SFP_ROI ,
3500 DFETAP1 => DFETAP1_TX_SFP_ROI,
3502 DFETAP2 => DFETAP2_TX_SFP_ROI,
3504 DFETAP3 => DFETAP3_TX_SFP_ROI,
3506 DFETAP4 => DFETAP4_TX_SFP_ROI,
3515 CLK_40MHz => clk40_in_TX_SFP_ROI,
-- clk40MHz
3516 CLK_120MHz => clk120_in_TX_SFP_ROI ,
-- clk120MHz
3517 RST => reset_daq ,
--not pll_locked, --reset(0), -- reset
3518 DAQ_IN => daq_in,
-- Input data (DAQ)
3519 ROI_IN => roi_in,
-- Input data (ROI)
3520 DAQ_DAV => daq_dav,
-- Control (DAQ)
3521 ROI_DAV => roi_dav,
-- Control (ROI)
3522 DAQ_BYTE => daq_byte,
-- Output Byte (DAQ)
3523 ROI_BYTE => roi_byte,
-- Output Byte (ROI)
3532 );
-- daq_encoded_DIAG
3534 MGT_118_clk0_ibufds_i : IBUFDS_GTXE1
3537 O => MGTREFCLK_Q118,
3550 clk40_in_TX_SFP_ROI<=clk40_out_TX_SFP_DAQ;
3551 clk120_in_TX_SFP_ROI<=clk120_out_TX_SFP_DAQ;
3553 indata_TX_SFP_DAQ<=daq_byte;
-- from GLINK emulator
3554 indata_TX_SFP_ROI<=roi_byte;
-- from GLINK emulator;
3558 --vio_data_i : diagn_module_vio
3560 -- CONTROL => control1,
3561 -- ASYNC_OUT => reset);
3566 ia_vme => ADDR_REG_RW_DAQ_ROI_RESET ,
3579 reset_daq<=data_from_vme_REG_RW_DAQ_ROI_RESET(0);
3580 data_to_vme_REG_RW_DAQ_ROI_RESET<=data_from_vme_REG_RW_DAQ_ROI_RESET;
3584 ia_vme => ADDR_REG_RW_DAQ_ROI_GTX_RESET ,
3595 data_to_vme => data_to_vme_REG_RW_DAQ_ROI_GTX_RESET
);
3597 gtx_reset_SFP_DAQ<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(0);
3598 gtx_reset_SFP_ROI<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(1);
3599 data_to_vme_REG_RW_DAQ_ROI_GTX_RESET<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET;
3604 ia_vme => ADDR_REG_RO_DAQ_ROI_STATUS ,
3613 data_to_vme => data_to_vme_REG_RO_DAQ_ROI_STATUS
);
3615 data_to_vme_REG_RO_DAQ_ROI_STATUS(0)<=local_pll_lock_out_SFP_DAQ;
3616 data_to_vme_REG_RO_DAQ_ROI_STATUS(1)<=GTX_TX_READY_OUT_TX_SFP_DAQ;
3617 data_to_vme_REG_RO_DAQ_ROI_STATUS(2)<=GTX_RX_READY_OUT_TX_SFP_DAQ;
3618 data_to_vme_REG_RO_DAQ_ROI_STATUS(3)<=PLLLKDET_diag_TX_SFP_DAQ;
3619 data_to_vme_REG_RO_DAQ_ROI_STATUS(4)<=local_pll_lock_out_SFP_ROI;
3620 data_to_vme_REG_RO_DAQ_ROI_STATUS(5)<=GTX_TX_READY_OUT_TX_SFP_ROI;
3621 data_to_vme_REG_RO_DAQ_ROI_STATUS(6)<=GTX_RX_READY_OUT_TX_SFP_ROI;
3622 data_to_vme_REG_RO_DAQ_ROI_STATUS(7)<=PLLLKDET_diag_TX_SFP_ROI;
3623 data_to_vme_REG_RO_DAQ_ROI_STATUS(8)<=readout_rst_out;
3625 data_to_vme_REG_RO_DAQ_ROI_STATUS(15 downto 9) <= (others=>'0');
3628 -- masked by Pawel Plucinski on 2015-04-28
3630 -- -- Chipscope analyzer
3631 -- chipscope_icon_u2_c3_inst: chipscope_icon_u2_c3
3633 -- CONTROL0 => CONTROL0,
3634 -- CONTROL1 => CONTROL1,
3635 -- CONTROL2 => CONTROL2
3638 -- ila_daq_glink : glink_chipscope_analyzer
3640 -- CONTROL => control0,
3641 -- CLK => clk40_in_TX_SFP_ROI,
3642 -- DATA => data_ila_daq,
3643 -- TRIG0 => trig_ila_daq);
3645 -- ila_glink_encoder : glink_chipscope_analyzer_encoder
3647 -- CONTROL => control1,
3648 -- CLK => clk120_in_TX_SFP_ROI,
3649 -- DATA => data_ila_encoder,
3650 -- TRIG0 => trig_ila_encoder);
3652 -- ila_gtx_start: entity work.glink_chipscope_analyzer_gtx_start
3654 -- CONTROL => CONTROL2,
3655 -- CLK => MGTREFCLK_Q118,
3656 -- DATA => data_ila_gtx_start,
3657 -- TRIG0 => trig_ila_gtx_start);
3659 -- data_ila_daq <= daq_in &
3660 -- daq_encoded_diag &
3662 -- local_pll_lock_out_SFP_DAQ &
3663 -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3664 -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3665 -- local_pll_lock_out_SFP_ROI &
3666 -- GTX_TX_READY_OUT_TX_SFP_ROI &
3667 -- GTX_RX_READY_OUT_TX_SFP_ROI &
3673 -- trig_ila_daq <= daq_encoded_diag &
3675 -- local_pll_lock_out_SFP_DAQ &
3676 -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3677 -- GTX_RX_READY_OUT_TX_SFP_DAQ &
3678 -- local_pll_lock_out_SFP_ROI &
3679 -- GTX_TX_READY_OUT_TX_SFP_ROI &
3680 -- GTX_RX_READY_OUT_TX_SFP_ROI &
3687 -- trig_ila_encoder <= GTX_TX_READY_OUT_TX_SFP_DAQ &
3693 -- data_ila_encoder <= byte_pos_out &
3695 -- readout_rst_out &
3696 -- GTX_TX_READY_OUT_TX_SFP_DAQ &
3702 -- trig_ila_gtx_start(0)<=pll_locked;
3703 -- trig_ila_gtx_start(1)<=gtx_reset_SFP_DAQ;
3704 -- trig_ila_gtx_start(2)<=gtx_reset_SFP_ROI;
3708 -- data_ila_gtx_start(0)<= pll_locked;
3709 -- data_ila_gtx_start(1)<= gtx_reset_SFP_DAQ;
3710 -- data_ila_gtx_start(2)<= gtx_reset_SFP_ROI;
3711 -- data_ila_gtx_start(3)<= GTX_TX_READY_OUT_TX_SFP_DAQ;
3712 -- data_ila_gtx_start(4)<= PLLLKDET_diag_TX_SFP_DAQ;
3713 -- data_ila_gtx_start(5)<= local_gtx_reset_diag_TX_SFP_DAQ;
3714 -- data_ila_gtx_start(6)<= local_mmcm_reset_diag_TX_SFP_DAQ;
3715 -- data_ila_gtx_start(7)<= GTXTEST_diag_TX_SFP_DAQ;
3716 -- data_ila_gtx_start(8)<= GTX_TX_READY_OUT_TX_SFP_ROI;
3717 -- data_ila_gtx_start(9)<= PLLLKDET_diag_TX_SFP_ROI;
3718 -- data_ila_gtx_start(10)<= local_gtx_reset_diag_TX_SFP_ROI;
3719 -- data_ila_gtx_start(11)<= local_mmcm_reset_diag_TX_SFP_ROI;
3720 -- data_ila_gtx_start(12)<= GTXTEST_diag_TX_SFP_ROI;
3728 if rising_edge(buf_clk40) then
3729 l1a_synced<=BUF_TTC_L1_ACCEPT_r;
3732 bc_reset_synced<=BUF_TTC_BNCH_CNT_RES_r;
3773 clk4000 => clk40_out_TX_SFP_DAQ ,
3775 reset => reset_daq ,
--not pll_locked,
3789 clk4000 => clk40_out_TX_SFP_DAQ ,
3791 reset => reset_daq ,
--not pll_locked,
3799 --readout control registers
3802 ia_vme => ADDR_REG_RW_DAQ_SLICE,
3815 nslices(1 downto 0) <= (data_to_vme_REG_RW_DAQ_SLICE(1 downto 0));
3816 nslices(7 downto 2) <= (others=>'0');
3818 data_to_vme_REG_RW_DAQ_SLICE<=data_from_vme_REG_RW_DAQ_SLICE;
3823 ia_vme => ADDR_REG_RW_DAQ_RAM_OFFSET ,
3834 data_to_vme => data_to_vme_REG_RW_DAQ_RAM_OFFSET
);
3836 data_to_vme_REG_RW_DAQ_RAM_OFFSET<=data_from_vme_REG_RW_DAQ_RAM_OFFSET;
3837 RAM_global_offset <= (data_from_vme_REG_RW_DAQ_RAM_OFFSET(7 downto 0));
3840 rel_offset_gen: for i_row in 1 to 19 generate
3843 ia_vme =>
(ADDR_REG_RW_DAQ_RAM_RELATIVE_OFFSET+2*
(i_row-
1)),
3853 data_from_vme => data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET
(i_row-
1),
3854 data_to_vme => data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET
(i_row-
1));
3856 data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)<=data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1);
3857 RAM_rel_offsets(i_row-1)<=(data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)(7 downto 0));
3858 end generate rel_offset_gen;
out BF_DOUT_CTP_41std_logic
in BF_SYSMON_13_NSTD_LOGIC
out TXN_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
in BF_SYSMON_14_PSTD_LOGIC
out BF_DOUT_CTP_01std_logic
out BF_TO_FROM_BSPT_2std_logic
out BF_DAQ_DATA_OUT_CMPstd_logic
in CLK_120MHz000_XTAL_1_BF_TRNCV_DIRstd_logic
in BF_SYSMON_09_PSTD_LOGIC
out data_vme_outstd_logic_vector (15 downto 0)
in BF_TO_TP_ROI_SLINK_RETURN_CMPstd_logic
out BF_TO_FROM_BSPT_3std_logic
out MP1_F11_QUAD_111_TRN_1_CMPstd_logic
out bcid_adjstd_logic_vector (11 downto 0)
out write_detectstd_logic
std_logic read_detect_inreg_test
out BF_LED_REQ_4std_logic
in BF_TO_FROM_BSPT_0std_logic
out BF_DOUT_CTP_61std_logic
out data_in_daqarr_96 (19 downto 0)
out sums_all_outarr_ctr_15bit (5 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out data_vme_outstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_34std_logic
in MGTREFCLK_PAD_N_INstd_logic_vector (num_GTX_groups - 1 downto 0)
out MP1_F04_QUAD_112_TRN_0_DIRstd_logic
inout data_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_32std_logic
in data_inarr_96 (19 downto 0)
out data_vme_outstd_logic_vector (15 downto 0)
out MP1_F07_QUAD_110_TRN_2_DIRstd_logic
out data_vmestd_logic_vector (15 downto 0)
out BF_TO_FROM_BSPT_6std_logic
out data_vme_outstd_logic_vector (15 downto 0)
out local_gtx_reset_diagstd_logic
out DFETAP2MONITORstd_logic_vector (4 downto 0)
out BF_LED_REQ_1std_logic
out MP2_F01_QUAD_113_TRN_0_CMPstd_logic
in data_vme_instd_logic_vector (15 downto 0)
out BF_DOUT_CTP_21std_logic
in BACKPLANE_DATA_INenergy_array
out MP1_F10_QUAD_111_TRN_2_DIRstd_logic
in T_SUM_E_MAXarr_ctr_15bit (num_thresholds - 1 downto 0)
std_logic_vector (15 downto 0) data_to_vme_test_rw
out BF_DOUT_CTP_46std_logic
in start_playbackstd_logic
in addr_vmestd_logic_vector (15 downto 0)
in DFETAP4std_logic_vector (3 downto 0)
in BF_SYSMON_03_NSTD_LOGIC
out BF_DOUT_CTP_04std_logic
in BF_SYSMON_10_PSTD_LOGIC
out BF_DOUT_CTP_65std_logic
out BF_DOUT_CTP_55std_logic
in BF_SYSMON_13_NSTD_LOGIC
std_logic_vector (15 downto 0) data_vme_up_top
in BF_SYSMON_13_PSTD_LOGIC
out BF_DOUT_CTP_19std_logic
in BF_SYSMON_12_PSTD_LOGIC
in TXDIFFCTRL_INstd_logic_vector (3 downto 0)
out BF_DOUT_CTP_14std_logic
out BF_DOUT_CTP_47std_logic
out send_align_outstd_logic_vector (num_GTX_groups * num_GTX_per_group - 1 downto 0)
in BF_SYSMON_01_NSTD_LOGIC
inout data_vmestd_logic_vector (15 downto 0)
the tri-stated port
in BF_SYSMON_10_NSTD_LOGIC
in addr_vmestd_logic_vector (15 downto 0)
out BF_LED_REQ_2std_logic
in BF_TO_TP_DAQ_SLINK_RETURN_DIRstd_logic
in spy_write_inhibitstd_logic
out MP2_F11_QUAD_114_TRN_1_DIRstd_logic
out data_from_vmestd_logic_vector (width - 1 downto 0)
in RAM_rel_offsetsarr_ctr_8bit (18 downto 0)
out BF_LED_REQ_0std_logic
out BF_DOUT_CTP_00std_logic
out BCID_outstd_logic_vector (11 downto 0)
in TXPREEMPHASIS_INstd_logic_vector (3 downto 0)
out data_from_vmestd_logic_vector (width - 1 downto 0)
in CLK_320MHz64_LHC_BF_QUAD_114_DIRstd_logic
in BF_SYSMON_03_PSTD_LOGIC
std_logic_vector (15 downto 0) data_to_vme_outreg_test
out MP2_F07_QUAD_113_TRN_2_DIRstd_logic
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out del_registerdel_register_type
out BF_DOUT_CTP_49std_logic
in BF_SYSMON_09_NSTD_LOGIC
in BF_SYSMON_13_PSTD_LOGIC
out BF_DOUT_CTP_64std_logic
out MP1_F04_QUAD_112_TRN_0_CMPstd_logic
out DFECLKDLYADJMONstd_logic_vector (5 downto 0)
out BCID_delayedstd_logic_vector (11 downto 0)
in BF_SYSMON_15_PSTD_LOGIC
out data_vme_outstd_logic_vector (15 downto 0)
in BF_SYSMON_03_NSTD_LOGIC
out data_from_vmestd_logic_vector (width - 1 downto 0)
out BF_ROI_DATA_OUT_DIRstd_logic
in energy_extra1std_logic_vector (23 downto 0)
in BF_SYSMON_11_NSTD_LOGIC
in data_vme_from_belowarr_16
--! inputs from local registers and from
out data_from_vmestd_logic_vector (width - 1 downto 0)
out GTXTEST_diagstd_logic
in bus_drive_from_belowstd_logic
--! a request to drive the outside
in addr_vmestd_logic_vector (15 downto 0)
out MP1_F01_QUAD_110_TRN_0_DIRstd_logic
in BF_SYSMON_07_NSTD_LOGIC
out BF_DOUT_CTP_05std_logic
in energy_extra0std_logic_vector (23 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
out BF_DOUT_CTP_50std_logic
in BCID_instd_logic_vector (11 downto 0)
in BF_SYSMON_14_NSTD_LOGIC
in BF_SYSMON_01_NSTD_LOGIC
out MP2_F04_QUAD_115_TRN_0_CMPstd_logic
out data_vme_outstd_logic_vector (15 downto 0)
out data_vmestd_logic_vector (15 downto 0)
in CLK_40MHz08_DSKW_2_BF_LOGIC_CMPstd_logic
in BF_SYSMON_04_NSTD_LOGIC
in data_vme_instd_logic_vector (15 downto 0)
out buf_clk40_m180ostd_logic
in BF_SYSMON_12_PSTD_LOGIC
out MP2_F04_QUAD_115_TRN_0_DIRstd_logic
in addr_vmestd_logic_vector (15 downto 0)
std_logic_vector (23 downto 1) vme_address
out BF_DOUT_CTP_57std_logic
out BF_DOUT_CTP_42std_logic
out LOCAL_CABLE_OUTstd_logic_vector (4 * 26 - 1 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
in send_alignstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out BF_DOUT_CTP_51std_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
out BF_DOUT_CTP_54std_logic
out MP1_F02_QUAD_112_TRN_2_DIRstd_logic
in BF_TO_FROM_BSPT_1std_logic
in local_datastd_logic_vector (4 * 26 - 1 downto 0)
out BF_DOUT_CTP_45std_logic
in BF_SYSMON_07_PSTD_LOGIC
out data_vme_outstd_logic_vector (15 downto 0)
out write_detectstd_logic
out MP2_F08_QUAD_114_TRN_3_DIRstd_logic
arr_16 (1762 downto 0) data_vme_from_below_top
out BF_DOUT_CTP_60std_logic
in ENERGY_REMOTEstd_logic_vector (26 * 4 - 1 downto 0)
std_logic bus_drive_up_top
out BF_DOUT_CTP_07std_logic
out BF_TO_FROM_BSPT_5std_logic
out MP2_F01_QUAD_113_TRN_0_DIRstd_logic
out local_mmcm_reset_diagstd_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
in DFETAP3std_logic_vector (3 downto 0)
out MP1_F07_QUAD_110_TRN_2_CMPstd_logic
in addr_vmestd_logic_vector (15 downto 0)
in BF_SYSMON_09_PSTD_LOGIC
out DFEEYEDACMONstd_logic_vector (4 downto 0)
out BF_DOUT_CTP_17std_logic
in BF_SYSMON_01_PSTD_LOGIC
in T_MISS_E_MINarr_ctr_31bit (num_thresholds - 1 downto 0)
out BF_DOUT_CTP_31std_logic
out BF_DOUT_CTP_38std_logic
out BF_DOUT_CTP_37std_logic
out MP2_F08_QUAD_114_TRN_3_CMPstd_logic
in addr_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_29std_logic
out BF_REQ_CABLE_3_INPUTstd_logic
out BF_DOUT_CTP_35std_logic
in nslicesunsigned (7 downto 0)
out BF_DOUT_CTP_26std_logic
out BF_DOUT_CTP_39std_logic
out GTX_RX_READY_OUTstd_logic
out BF_DOUT_CTP_23std_logic
in DFECLKDLYADJstd_logic_vector (5 downto 0)
out MP2_F09_QUAD_114_TRN_0_DIRstd_logic
out BF_DOUT_CTP_16std_logic
out data_vme_outstd_logic_vector (15 downto 0)
out local_pll_lock_outstd_logic
std_logic_vector (numactchan - 1 downto 0) counter_values
in BF_SYSMON_10_NSTD_LOGIC
out upload_delaysstd_logic
in T_MISS_E_MAXarr_ctr_31bit (num_thresholds - 1 downto 0)
out data_vme_going_belowstd_logic_vector (15 downto 0)
in TXPOSTEMPHASIS_INstd_logic_vector (4 downto 0)
in vme_addressstd_logic_vector (23 downto 1)
in BCID_instd_logic_vector (11 downto 0)
in T_SUM_E_MINarr_ctr_15bit (num_thresholds - 1 downto 0)
std_logic start_playback_r1
out data_vme_outstd_logic_vector (15 downto 0)
std_logic_vector (15 downto 0) data_vme_going_below
in data_to_vmestd_logic_vector (width - 1 downto 0)
out MP1_F00_QUAD_112_TRN_3_CMPstd_logic
out BF_DOUT_CTP_28std_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
in GTXRXRESET_INstd_logic
in MGTREFCLK_PAD_P_INstd_logic_vector (num_GTX_groups - 1 downto 0)
in BF_SYSMON_04_NSTD_LOGIC
in BF_SYSMON_14_PSTD_LOGIC
std_logic_vector (15 downto 0) data_from_vme_test_rw
out data_vme_upstd_logic_vector (15 downto 0)
--! connect this to
in addr_vmestd_logic_vector (15 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_24std_logic
in bc_counterunsigned (11 downto 0)
in BF_TO_TP_DAQ_SLINK_RETURN_CMPstd_logic
out GTX_TX_READY_OUTstd_logic
in BF_SYSMON_09_NSTD_LOGIC
out BF_DOUT_CTP_53std_logic
out MP2_F02_QUAD_115_TRN_2_DIRstd_logic
in datastd_logic_vector ((numbits_in_CTP_connector * 2) - 1 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out BF_REQ_CABLE_1_INPUTstd_logic
std_logic read_detect_outreg_test
del_register_type del_register
in SUM_ET_RES_THRarr_ctr_15bit (num_thresholds - 1 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out MP2_F09_QUAD_114_TRN_0_CMPstd_logic
in data_vme_instd_logic_vector (15 downto 0)
in CLK_120MHz000_XTAL_1_BF_TRNCV_CMPstd_logic
out BF_DOUT_CTP_18std_logic
out BF_DOUT_CTP_06std_logic
out BF_DOUT_CTP_27std_logic
out BF_DOUT_CTP_43std_logic
out MP2_F03_QUAD_113_TRN_1_DIRstd_logic
in BF_SYSMON_11_NSTD_LOGIC
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out BCID_delayedstd_logic_vector (11 downto 0)
std_logic_vector (15 downto 0) data_to_vme_test_r
out MP2_F11_QUAD_114_TRN_1_CMPstd_logic
out DFETAP3MONITORstd_logic_vector (3 downto 0)
in energy_localstd_logic_vector (26 * 4 - 1 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
out TXP_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out MP1_F00_QUAD_112_TRN_3_DIRstd_logic
out MP1_F06_QUAD_112_TRN_1_CMPstd_logic
in BF_SYSMON_11_PSTD_LOGIC
out GTX_RX_READY_OUTstd_logic
in BF_SYSMON_01_PSTD_LOGIC
out BF_DOUT_CTP_58std_logic
out BF_DOUT_CTP_10std_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
in OCB_SYS_RESET_Bstd_logic
in par_errstd_logic_vector (1 downto 0)
in DFETAP1std_logic_vector (4 downto 0)
in SUM_ET_THRarr_ctr_15bit (num_thresholds - 1 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out bus_drive_upstd_logic
or of all bus drive requests from below
out BF_DOUT_CTP_03std_logic
in BUF_TTC_BNCH_CNT_RESstd_logic
out MP2_F10_QUAD_114_TRN_2_CMPstd_logic
in RAM_global_offsetunsigned (7 downto 0)
out MP1_F10_QUAD_111_TRN_2_CMPstd_logic
in BF_SYSMON_07_PSTD_LOGIC
in energy_totalarr_ctr_15bit (5 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
in BF_SYSMON_08_NSTD_LOGIC
out counter_inhibitstd_logic
out MP1_F09_QUAD_111_TRN_0_DIRstd_logic
out BF_REQ_CTP_1_INPUTstd_logic
out BF_LED_REQ_3std_logic
out data_vme_outstd_logic_vector (15 downto 0)
out BF_TO_FROM_BSPT_7std_logic
out BF_DOUT_CTP_25std_logic
in CLK_320MHz64_LHC_BF_QUAD_114_CMPstd_logic
in BF_SYSMON_14_NSTD_LOGIC
in data_vme_instd_logic_vector (15 downto 0)
in BF_SYSMON_07_NSTD_LOGIC
out ROI_BYTEstd_logic_vector (7 downto 0)
in BF_SYSMON_08_PSTD_LOGIC
in energy_ovflwstd_logic_vector (5 downto 0)
out DFETAP4MONITORstd_logic_vector (3 downto 0)
out MP1_F05_QUAD_110_TRN_3_DIRstd_logic
out BF_DOUT_CTP_20std_logic
in BF_SYSMON_15_NSTD_LOGIC
in data_vme_from_belowstd_logic_vector (15 downto 0)
--! input: ORed
out buf_clk40_m90ostd_logic
in ROI_INstd_logic_vector (19 downto 0)
out MP1_F06_QUAD_112_TRN_1_DIRstd_logic
out BF_DOUT_CTP_30std_logic
in BF_SYSMON_11_PSTD_LOGIC
out MP2_F05_QUAD_113_TRN_3_DIRstd_logic
in addr_vmestd_logic_vector (15 downto 0)
out MP1_F09_QUAD_111_TRN_0_CMPstd_logic
out MP1_F05_QUAD_110_TRN_3_CMPstd_logic
in BUF_TTC_L1_ACCEPTstd_logic
in bcid_instd_logic_vector (11 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
in BF_SYSMON_08_NSTD_LOGIC
in BF_SYSMON_10_PSTD_LOGIC
in RXEQMIX_INstd_logic_vector (2 downto 0)
in MISS_E_THRarr_ctr_31bit (num_thresholds - 1 downto 0)
out BF_DAQ_DATA_OUT_DIRstd_logic
out BF_DOUT_CTP_22std_logic
in indatastd_logic_vector (7 downto 0)
out BF_DOUT_CTP_08std_logic
out daq_byte_outstd_logic_vector (1 downto 0)
in CLK_320MHz64_LHC_BF_QUAD_111_CMPstd_logic
ADDR_REG_RO_SYSMON_DATA_BLOCKinteger :=16#1364#
out counter_resetstd_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
out BF_TO_FROM_BSPT_4std_logic
out data_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_09std_logic
out odatastd_logic_vector (7 downto 0)
out MP1_F08_QUAD_111_TRN_3_CMPstd_logic
out GTX_TX_READY_OUTstd_logic
in BF_SYSMON_15_PSTD_LOGIC
in CLK_320MHz64_LHC_BF_QUAD_111_DIRstd_logic
out MP1_F11_QUAD_111_TRN_1_DIRstd_logic
out MP1_F03_QUAD_110_TRN_1_CMPstd_logic
out BF_REQ_CABLE_2_INPUTstd_logic
out MP2_F03_QUAD_113_TRN_1_CMPstd_logic
out readout_rst_outstd_logic
out data_vme_outstd_logic_vector (15 downto 0)
out pll_locked_ds2std_logic
in OCB_GEO_ADRS_0std_logic
out spy_write_inhibitstd_logic
out DFETAP1MONITORstd_logic_vector (4 downto 0)
out MP2_F10_QUAD_114_TRN_2_DIRstd_logic
in data_vme_instd_logic_vector (15 downto 0)
in DFETAP2std_logic_vector (4 downto 0)
in indatastd_logic_vector (TX_indata_length - 1 downto 0)
out BF_DOUT_CTP_63std_logic
in BF_SYSMON_03_PSTD_LOGIC
in XS_B2arr_ctr_15bit (num_thresholds - 1 downto 0)
out Data_outstd_logic_vector (TX_indata_length - 1 downto 0)
in BF_SYSMON_04_PSTD_LOGIC
in BCIDstd_logic_vector (11 downto 0)
out BF_DOUT_CTP_40std_logic
in dataiarr_4Xword (max_jems - 1 downto 0)
out PLLLKDET_diagstd_logic
in BF_SYSMON_04_PSTD_LOGIC
out BF_ROI_DATA_OUT_CMPstd_logic
out BF_DOUT_CTP_15std_logic
out BF_DOUT_CTP_62std_logic
out byte_pos_outstd_logic_vector (5 downto 0)
out BF_DOUT_CTP_33std_logic
in addr_vmestd_logic_vector (15 downto 0)
in BF_SYSMON_15_NSTD_LOGIC
out MP2_F00_QUAD_115_TRN_3_DIRstd_logic
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out word_sel_outstd_logic_vector (1 downto 0)
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
unsigned (15 downto 0) test_rw_counter
in DAQ_INstd_logic_vector (19 downto 0)
out DFESENSCALstd_logic_vector (2 downto 0)
in energy_remotestd_logic_vector (26 * 4 - 1 downto 0)
in CLK_40MHz08_DSKW_1_BF_LOGIC_CMPstd_logic
out buf_clk40_90ostd_logic
out BF_DOUT_CTP_48std_logic
out BF_DOUT_CTP_44std_logic
in BF_SYSMON_08_PSTD_LOGIC
in buf_clk40_centerstd_logic
out BF_DOUT_CTP_52std_logic
in MISS_E_RES_THRarr_ctr_31bit (num_thresholds - 1 downto 0)
std_logic_vector (1762 downto 0) bus_drive_from_below_top
out DAQ_ENCODED_DIAGstd_logic_vector (23 downto 0)
out BF_REQ_CTP_2_INPUTstd_logic
out DAQ_BYTEstd_logic_vector (7 downto 0)
out MP1_F02_QUAD_112_TRN_2_CMPstd_logic
out MP2_F00_QUAD_115_TRN_3_CMPstd_logic
in BF_SYSMON_12_NSTD_LOGIC
out MP2_F05_QUAD_113_TRN_3_CMPstd_logic
in XS_T2_A2arr_ctr_31bit (num_thresholds - 1 downto 0)
out MP1_F08_QUAD_111_TRN_3_DIRstd_logic
std_logic write_detect_inreg_test
out ov_all_outstd_logic_vector (5 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
inout OCB_Dstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_02std_logic
out MP1_F01_QUAD_110_TRN_0_CMPstd_logic
inout data_vmestd_logic_vector (15 downto 0)
out CTP_CABLE_1std_logic_vector (23 downto 0)
in data_to_vmestd_logic_vector (width - 1 downto 0)
in CLK_40MHz08_DSKW_1_BF_LOGIC_DIRstd_logic
out BF_DOUT_CTP_13std_logic
out MP2_F02_QUAD_115_TRN_2_CMPstd_logic
out MP2_F06_QUAD_115_TRN_1_CMPstd_logic
out buf_clk40_ds2std_logic
out BF_DOUT_CTP_59std_logic
in CLK_40MHz08_DSKW_2_BF_LOGIC_DIRstd_logic
in BF_TO_TP_ROI_SLINK_RETURN_DIRstd_logic
out BF_DOUT_CTP_56std_logic
in GTXTXRESET_INstd_logic
out MP2_F07_QUAD_113_TRN_2_CMPstd_logic
out BF_DOUT_CTP_11std_logic
out BF_DOUT_CTP_36std_logic
out MP1_F03_QUAD_110_TRN_1_DIRstd_logic
out data_outstd_logic_vector (19 downto 0)
in bus_drive_from_belowstd_logic_vector
in BF_SYSMON_12_NSTD_LOGIC
out CTP_CABLE_0std_logic_vector (23 downto 0)
out MP2_F06_QUAD_115_TRN_1_DIRstd_logic
out BF_DOUT_CTP_12std_logic