1 ----------------------------------------------------------------------------------
3 -- Engineer: W. Fedorko
5 -- Create Date: 30 Apr 2013
7 -- Module Name: mini_fifo_synchroniser - Behavioral
11 -- Description: This modules provides synchronisers for the mini fifos that
12 -- transfer the data into the GTX TX Clock domains
15 -- Dependencies: CoreGen wrapper for a Block Ram
18 -- Revision 0.01 - File Created
19 -- Additional Comments:
21 ----------------------------------------------------------------------------------
23 use IEEE.STD_LOGIC_1164.
ALL;
29 -- Uncomment the following library declaration if using
30 -- arithmetic functions with Signed or Unsigned values
31 -- use IEEE.NUMERIC_STD.ALL;
33 -- Uncomment the following library declaration if instantiating
34 -- any Xilinx primitives in this code.
36 --use UNISIM.VComponents.all;
40 set_mem_ctr_i_out :
out ;
41 set_mem_ctr_o_out :
out ;
44 set : in );
--set signal (active high)
45 end mini_fifo_synchroniser;
68 begin -- process i_ctr_proc
70 set_mem_ctr_i<=set_rr_clk_i;
71 set_rr_clk_i<=set_r_clk_i;
77 begin -- process i_ctr_proc
80 set_mem_ctr_o <= set_rr_clk_i_r_clk_o;
81 set_rr_clk_i_r_clk_o <= set_rr_clk_i;
85 set_mem_ctr_o_out<=set_mem_ctr_o;
86 set_mem_ctr_i_out<=set_mem_ctr_i;
std_logic set_rr_clk_i_r_clk_o