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parity_gen.vhd
Go to the documentation of this file.
1
11
LIBRARY
ieee
;
12
USE
ieee
.std_logic_1164.
all
;
13
USE
ieee
.numeric_std.
all
;
14
15
ENTITY
parity_gen
IS
16
GENERIC
(
17
width
:
integer
:=
60
18
)
;
19
PORT
(
20
din
:
IN
std_logic_vector
(
width
-
1
downto
0
)
;
21
parity
:
OUT
std_logic
22
)
;
23
24
-- Declarations
25
26
END
parity_gen
;
27
28
-- renoir interface_end
29
ARCHITECTURE
rtl
OF
parity_gen
IS
30
--------------------------------------------------------------------------------
31
-- Calculate the (odd) parity of incoming data and output result.
32
--
33
--------------------------------------------------------------------------------
34
BEGIN
35
36
parity_check
:
process
(
din
)
37
variable
iparity
:
std_logic
;
38
begin
39
iparity
:=
'
1
'
;
-- odd parity
40
for
i
in
0
to
(
width
-
1
)
loop
41
iparity
:=
iparity
xor
din
(
i
)
;
42
end
loop
;
43
parity
<=
iparity
;
44
end
process
;
45
46
47
END
rtl
;
parity_gen
Definition:
parity_gen.vhd:18
parity_gen.rtl.parity_check
parity_checkdin
Definition:
parity_gen.vhd:39
parity_gen.ieee
_library_ ieeeieee
Definition:
parity_gen.vhd:14
parity_gen.parity
out paritystd_logic
Definition:
parity_gen.vhd:24
parity_gen.width
widthinteger :=60
Definition:
parity_gen.vhd:20
parity_gen.din
in dinstd_logic_vector (width - 1 downto 0)
Definition:
parity_gen.vhd:23
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parity_gen.vhd
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