1 ----------------------------------------------------------------------------------
7 ----------------------------------------------------------------------------------
9 use IEEE.STD_LOGIC_1164.
ALL;
10 use IEEE.NUMERIC_STD.
ALL;
13 use UNISIM.VComponents.
all;
26 ----------------------------------------------------------------------------
27 -- VME-- backplane (65 signals)
28 ----------------------------------------------------------------------------
29 --GEOADDR0: in std_logic; -- GeoAddr0
31 --VMEADDR: in std_logic_vector(23 downto 1); -- Address bus
55 --VMEDS_L: in std_logic; -- DS strobe VMEDS_L
57 --VMEWR_L: in std_logic; -- VME Write VMEWR_L
59 --VMERST_L: in std_logic; -- System reset VMERST_L
61 --VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA
62 OCB_D: inout (15 downto 0);
63 ----------------------------------------------------------------------------
493 --CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
494 --CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
503 --CLK_320MHz64_LHC_BF_LOGIC_DIR : in std_logic;
504 --CLK_320MHz64_LHC_BF_LOGIC_CMP : in std_logic;
761 --clk40 : in std_logic;
762 RXN_IN : in ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
763 RXP_IN : in ((num_GTX_per_group*num_GTX_groups)-1 downto 0)
773 attribute keep : ;
-- keep signals in synthesis
777 ------------------------------------------------------------------------------
778 -- VME interface component used in BSPT FPGA (Ian's vme_interface)
779 ------------------------------------------------------------------------------
782 clk40 :
IN ;
-- 40MHz Clk
791 -- signals for CMX_BASE_VME_INTERFACE component
792 signal ds: ;
-- board_ds output from VME (Ian model)
793 signal ncs: ;
-- brdsel_n output from VME (Ian model)
944 -- the first variable is
945 -- yet one more register
1002 P :
in mat_var (numactchan
-1 downto 0);
1007 ODATA :
out arr_4Xword (numactchan
-1 downto 0);
1031 --signal PAR_ERROR: std_logic_vector(numactchan-1 downto 0);
1036 signal data_from_vme_REG_RW_QUIET_FORCE : (15 downto 0);
1037 signal data_to_vme_REG_RW_QUIET_FORCE : (15 downto 0);
1039 signal DATA96 : arr_4Xword (numactchan-1 downto 0);
--96 bit data at 40MHz
1040 signal ODATA_first_half : arr_2Xword(numactchan-1 downto 0);
1042 signal P : mat_var (numactchan-1 downto 0);
1044 signal BF_DEBUG : (9 downto 0);
1046 signal counter_enable_inputmod_sig: (numactchan-1 downto 0);
1060 end component CMX_Memory_spy_inhibit;
1062 signal spy_write_inhibit : ;
1072 datai :
in arr_4Xword(max_cps
-1 downto 0);
1075 overflow :
out (num_copies
-1 downto 0);
1078 --tob rate counter contol
1088 end component decoder;
1090 signal Tobs_to_TOPO : copy_arr_TOB;
1091 signal overflow : (num_copies-1 downto 0);
1094 signal data_from_vme_REG_RW_JET_THRESHOLD_BLOCK : arr_16(1599 downto 0);
1095 signal data_to_vme_REG_RW_JET_THRESHOLD_BLOCK : arr_16(1599 downto 0);
1102 clk :
in T_SL;
-- clock
1103 thresholds :
in arr_16(max_cps*
16*
4-1 downto 0);
-- thresholds
1104 datai :
in arr_4Xword(max_cps
-1 downto 0);
-- input data
1105 din_cbl :
in T_SLV150;
-- remote input (multiplicty)
1109 dout_lcl :
out T_SLV48;
-- local multiplicity
1111 dout :
out T_SLV62;
-- global output data (multiplicity), including parity
1112 dout_ro :
out T_SL;
-- global overflow
1113 dout_cbla_mux0 :
out (
33 downto 0);
-- cable output data (multiplicity), including parity
1114 dout_cbla_mux1 :
out (
33 downto 0);
-- cable output data (multiplicity), including parity
1123 par_err :
in T_SLV2;
-- parity error (input module - 0, RTM - 1)
1124 force :
in T_SL;
-- force
1131 signal par_err : T_SLV2;
1136 datai :
in arr_4Xword(max_cps
-1 downto 0);
1150 signal dout_cbla_mux0 : (33 downto 0);
1151 signal dout_cbla_mux1 : (33 downto 0);
1153 signal data_to_RTM1 : ((numbits_in_RTM_connector*2)-1 downto 0);
1156 signal thresholds : arr_16(16*25*4-1 downto 0);
-- thresholds
1158 signal dout_lcl : T_SLV48;
-- local multiplicity
1159 signal dout_lcl_ro : T_SL;
-- local overflow
1161 signal din_cbl : T_SLV150;
--dummy just to not flag parity errors in daq
1165 data :
in (numbits_in_RTM_connector*
2*num_RTM_cables
- 1 downto 0);
1179 end component CMX_crate_cable_output_module;
1181 signal data_to_RTM : ( numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1182 signal ddr_data_out_RTM : arr_RTM(num_RTM_cables-1 downto 0);
1184 signal sdr_data_out_CTP1 : (31 downto 0);
1185 signal sdr_data_out_CTP2 : (31 downto 0);
1186 --signal sdr_data_out : std_logic_vector(31 downto 0);
1188 signal ddr_data_out_RTM1 : (numbits_in_RTM_connector downto 0);
1189 --signal ddr_data_out_RTM2 : std_logic_vector(numbits_in_RTM_connector downto 0);
1190 --signal del_array_RTM : cable_del_array_type(numbits_in_RTM_connector downto 0);
1192 --signal ddr_data_in_RTM1 : std_logic_vector(numbits_in_RTM_connector downto 0);
1193 --signal ddr_data_in_RTM2 : std_logic_vector(numbits_in_RTM_connector downto 0);
1194 --signal sig_arr_RTM: arr_RTM(num_RTM_cables-1 downto 0);
1195 --signal data_from_RTM : std_logic_vector(numbits_in_RTM_connector*2*num_RTM_cables - 1 downto 0);
1201 --signal forwarded_clock_CTP2 : std_logic;
1202 --signal data_CTP2 : std_logic_vector((numbits_in_CTP_connector*2)-1 downto 0);
1203 --signal parity_CTP2 : std_logic;
1204 --signal ddr_data_in_CTP2 : std_logic_vector(numbits_in_CTP_connector downto 0);
1206 --signal forwarded_clock_RTM3 : std_logic;
1207 --signal data_RTM3 : std_logic_vector((numbits_in_RTM_connector*2)-1 downto 0);
1208 --signal parity_RTM3 : std_logic;
1209 --signal ddr_data_in_RTM3 : std_logic_vector(numbits_in_RTM_connector downto 0);
1217 ncs :
in ;
--ports forwarded to the vme register instances
1226 signal BCID_counter_sig : (11 downto 0);
1227 signal BCID_delayed_decoder : (11 downto 0);
1228 signal BCID_delayed_daq : (11 downto 0);
1240 RXN_IN :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1241 RXP_IN :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1242 TXN_OUT :
out ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1243 TXP_OUT :
out ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1247 send_align :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
1248 BCID :
in (
11 downto 0);
1249 indata :
in (TX_indata_length
-1 downto 0);
1258 end component Topo_Data_TX;
1263 overflow :
in (num_copies
-1 downto 0);
1264 send_align_out :
out (num_GTX_groups*num_GTX_per_group
- 1 downto 0);
1265 Data_out :
out (TX_indata_length
- 1 downto 0));
1266 end component CMX_CP_Topo_Encoder;
1268 signal TXN_OUT : ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1269 signal TXP_OUT : ((num_GTX_per_group*num_GTX_groups)-1 downto 0);
1271 signal MGTREFCLK_PAD_N_IN : (num_GTX_groups-1 downto 0);
1272 signal MGTREFCLK_PAD_P_IN : (num_GTX_groups-1 downto 0);
1274 signal GTX_RX_READY_OUT : ;
1275 signal GTX_TX_READY_OUT : ;
1278 signal GTXTXRESET_IN : ;
1279 signal GTXRXRESET_IN : ;
1281 signal send_align : (23 downto 0);
1283 signal indata_Topo_TX : (TX_indata_length-1 downto 0);
1285 signal data_to_vme_REG_RW_TOPOTR_GTX_RESET : (15 downto 0);
1286 signal data_from_vme_REG_RW_TOPOTR_GTX_RESET : (15 downto 0);
1288 signal data_to_vme_REG_RO_TOPOTR_GTX_STATUS : (15 downto 0);
1290 signal data_from_vme_REG_RW_DAQ_ROI_RESET : (15 downto 0);
1291 signal data_to_vme_REG_RW_DAQ_ROI_RESET : (15 downto 0);
1293 signal data_to_vme_REG_RO_DAQ_ROI_STATUS : (15 downto 0);
1295 signal data_from_vme_REG_RW_DAQ_ROI_GTX_RESET: (15 downto 0);
1296 signal data_to_vme_REG_RW_DAQ_ROI_GTX_RESET: (15 downto 0);
1297 signal gtx_reset_SFP_DAQ, gtx_reset_SFP_ROI : ;
1299 signal BUF_TTC_L1_ACCEPT_r: ;
1300 signal l1a_synced: ;
1302 signal bc_reset_synced : ;
1303 signal BUF_TTC_BNCH_CNT_RES_r : ;
1317 end component CMX_rate_counter_inhibit;
1319 signal counter_inhibit : ;
1320 signal counter_reset : ;
1324 component chipscope_icon_u2_c3
1326 CONTROL0 :
inout (
35 downto 0);
1327 CONTROL1 :
inout (
35 downto 0);
1328 CONTROL2 :
inout (
35 downto 0)
1332 signal CONTROL0 : (35 downto 0);
1333 signal CONTROL1 : (35 downto 0);
1334 signal CONTROL2 : (35 downto 0);
1337 --component chipscope_ila_CMX_top_inputmodclk
1339 -- CONTROL : inout std_logic_vector(35 downto 0);
1340 -- CLK : in std_logic;
1341 -- DATA : in std_logic_vector(2375 downto 0);
1342 -- TRIG0 : in std_logic_vector(35 downto 0));
1345 --signal DATA_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(2375 downto 0);
1346 --signal TRIG0_chipscope_ila_CMX_top_inputmodclk : std_logic_vector(35 downto 0);
1347 --signal TRIG_forward_inputmodclk_outputmodclk : std_logic_vector(0 downto 0);
1349 --component chipscope_ila_IDELAY
1351 -- CONTROL : inout std_logic_vector(35 downto 0);
1352 -- CLK : in std_logic;
1353 -- DATA : in std_logic_vector(2000 downto 0);
1354 -- TRIG0 : in std_logic_vector(0 to 0));
1357 --signal DATA_chipscope_ila_IDELAY : std_logic_vector(2000 downto 0);
1360 --component chipscope_ila_CTP2
1362 -- CONTROL : inout std_logic_vector(35 downto 0);
1363 -- CLK : in std_logic;
1364 -- DATA : in std_logic_vector(64 downto 0);
1365 -- TRIG0 : in std_logic_vector(0 to 0));
1368 --component chipscope_ila_RTM
1370 -- CONTROL : inout std_logic_vector(35 downto 0);
1371 -- CLK : in std_logic;
1372 -- DATA : in std_logic_vector(52 downto 0);
1373 -- TRIG0 : in std_logic_vector(0 to 0));
1376 --component chipscope_ila_LVDS_TX_CTP_RTM
1378 -- CONTROL : inout std_logic_vector(35 downto 0);
1379 -- CLK : in std_logic;
1380 -- DATA : in std_logic_vector(117 downto 0);
1381 -- TRIG0 : in std_logic_vector(1 downto 0));
1408 end component CMX_clock_manager;
1412 signal buf_clk40 : ;
1413 signal buf_clk40_m180o : ;
1414 signal buf_clk40_90o : ;
1415 signal buf_clk40_m90o : ;
1417 signal buf_clk320 : ;
1418 signal buf_clk160 : ;
1419 signal buf_clk200 : ;
1420 signal pll_locked : ;
1422 signal buf_clk40_ds2 : ;
1423 signal pll_locked_ds2 : ;
1441 --no CTP output from the crate
1442 --component CMX_CTP_output_module is
1444 -- data : in std_logic_vector((numbits_in_CTP_connector*2)-1 downto 0);
1445 -- sdr_data_out : out arr_CTP;
1446 -- buf_clk40 : in std_logic;
1447 -- buf_clk40_center : in std_logic;
1448 -- buf_clk200 : in std_logic;
1449 -- pll_locked : in std_logic;
1450 -- start_playback : in std_logic;
1451 -- spy_write_inhibit : in std_logic;
1452 -- ncs : in std_logic;
1453 -- rd_nwr : in std_logic;
1454 -- ds : in std_logic;
1455 -- addr_vme : in std_logic_vector (15 downto 0);
1456 -- data_vme : inout std_logic_vector (15 downto 0));
1457 --end component CMX_CTP_output_module;
1459 --signal sdr_data_CTP: arr_CTP;
1485 indata :
in (
7 downto 0);
1486 odata :
out (
7 downto 0);
1507 signal MGTREFCLK_Q118 : ;
1509 signal GTXTXRESET_IN_TX_SFP_DAQ : ;
1510 signal GTXRXRESET_IN_TX_SFP_DAQ : ;
1511 signal local_pll_lock_out_SFP_DAQ : ;
1512 signal GTX_TX_READY_OUT_TX_SFP_DAQ : ;
1513 signal GTX_RX_READY_OUT_TX_SFP_DAQ : ;
1514 signal PLLLKDET_diag_TX_SFP_DAQ : ;
1515 signal local_gtx_reset_diag_TX_SFP_DAQ : ;
1516 signal local_mmcm_reset_diag_TX_SFP_DAQ : ;
1517 signal GTXTEST_diag_TX_SFP_DAQ : ;
1518 signal RXN_IN_TX_SFP_DAQ : ;
1519 signal RXP_IN_TX_SFP_DAQ : ;
1520 signal TXN_OUT_TX_SFP_DAQ : ;
1521 signal TXP_OUT_TX_SFP_DAQ : ;
1522 signal clk40_out_TX_SFP_DAQ : ;
1523 signal clk120_out_TX_SFP_DAQ : ;
1524 signal clk40_in_TX_SFP_DAQ : ;
1525 signal clk120_in_TX_SFP_DAQ : ;
1526 signal indata_TX_SFP_DAQ : (7 downto 0);
1527 signal odata_TX_SFP_DAQ : (7 downto 0);
1528 signal TXPREEMPHASIS_IN_TX_SFP_DAQ : (3 downto 0);
1529 signal TXPOSTEMPHASIS_IN_TX_SFP_DAQ : (4 downto 0);
1530 signal TXDIFFCTRL_IN_TX_SFP_DAQ : (3 downto 0);
1531 signal RXEQMIX_IN_TX_SFP_DAQ : (2 downto 0);
1532 signal DFECLKDLYADJ_TX_SFP_DAQ : (5 downto 0);
1533 signal DFECLKDLYADJMON_TX_SFP_DAQ : (5 downto 0);
1534 signal DFEDLYOVRD_TX_SFP_DAQ : ;
1535 signal DFEEYEDACMON_TX_SFP_DAQ : (4 downto 0);
1536 signal DFESENSCAL_TX_SFP_DAQ : (2 downto 0);
1537 signal DFETAP1_TX_SFP_DAQ : (4 downto 0);
1538 signal DFETAP1MONITOR_TX_SFP_DAQ : (4 downto 0);
1539 signal DFETAP2_TX_SFP_DAQ : (4 downto 0);
1540 signal DFETAP2MONITOR_TX_SFP_DAQ : (4 downto 0);
1541 signal DFETAP3_TX_SFP_DAQ : (3 downto 0);
1542 signal DFETAP3MONITOR_TX_SFP_DAQ : (3 downto 0);
1543 signal DFETAP4_TX_SFP_DAQ : (3 downto 0);
1544 signal DFETAP4MONITOR_TX_SFP_DAQ : (3 downto 0);
1545 signal DFETAPOVRD_TX_SFP_DAQ : ;
1547 signal GTXTXRESET_IN_TX_SFP_ROI : ;
1548 signal GTXRXRESET_IN_TX_SFP_ROI : ;
1549 signal local_pll_lock_out_SFP_ROI : ;
1550 signal GTX_TX_READY_OUT_TX_SFP_ROI : ;
1551 signal PLLLKDET_diag_TX_SFP_ROI : ;
1552 signal local_gtx_reset_diag_TX_SFP_ROI : ;
1553 signal local_mmcm_reset_diag_TX_SFP_ROI : ;
1554 signal GTXTEST_diag_TX_SFP_ROI : ;
1555 signal GTX_RX_READY_OUT_TX_SFP_ROI : ;
1556 signal RXN_IN_TX_SFP_ROI : ;
1557 signal RXP_IN_TX_SFP_ROI : ;
1558 signal TXN_OUT_TX_SFP_ROI : ;
1559 signal TXP_OUT_TX_SFP_ROI : ;
1560 signal clk40_out_TX_SFP_ROI : ;
1561 signal clk120_out_TX_SFP_ROI : ;
1562 signal clk40_in_TX_SFP_ROI : ;
1563 signal clk120_in_TX_SFP_ROI : ;
1564 signal indata_TX_SFP_ROI : (7 downto 0);
1565 signal odata_TX_SFP_ROI : (7 downto 0);
1566 signal TXPREEMPHASIS_IN_TX_SFP_ROI : (3 downto 0);
1567 signal TXPOSTEMPHASIS_IN_TX_SFP_ROI : (4 downto 0);
1568 signal TXDIFFCTRL_IN_TX_SFP_ROI : (3 downto 0);
1569 signal RXEQMIX_IN_TX_SFP_ROI : (2 downto 0);
1570 signal DFECLKDLYADJ_TX_SFP_ROI : (5 downto 0);
1571 signal DFECLKDLYADJMON_TX_SFP_ROI : (5 downto 0);
1572 signal DFEDLYOVRD_TX_SFP_ROI : ;
1573 signal DFEEYEDACMON_TX_SFP_ROI : (4 downto 0);
1574 signal DFESENSCAL_TX_SFP_ROI : (2 downto 0);
1575 signal DFETAP1_TX_SFP_ROI : (4 downto 0);
1576 signal DFETAP1MONITOR_TX_SFP_ROI : (4 downto 0);
1577 signal DFETAP2_TX_SFP_ROI : (4 downto 0);
1578 signal DFETAP2MONITOR_TX_SFP_ROI : (4 downto 0);
1579 signal DFETAP3_TX_SFP_ROI : (3 downto 0);
1580 signal DFETAP3MONITOR_TX_SFP_ROI : (3 downto 0);
1581 signal DFETAP4_TX_SFP_ROI : (3 downto 0);
1582 signal DFETAP4MONITOR_TX_SFP_ROI : (3 downto 0);
1583 signal DFETAPOVRD_TX_SFP_ROI : ;
1593 DAQ_IN :
in (
19 DOWNTO 0);
1594 ROI_IN :
in (
19 DOWNTO 0);
1607 -- Glink emulator signals
1609 signal daq_in : (19 DOWNTO 0);
1610 signal roi_in : (19 DOWNTO 0);
1613 signal daq_byte : (7 downto 0);
1614 signal roi_byte : (7 downto 0);
1615 signal reset_daq : ;
1616 signal daq_encoded_diag : (23 downto 0);
1617 signal daq_byte_out : (1 downto 0);
1619 signal byte_pos_out : (5 downto 0);
1620 signal word_sel_out : (1 downto 0);
1621 signal readout_rst_out : ;
1625 component diagn_module_vio
1627 CONTROL:
inout (
35 downto 0);
1628 ASYNC_OUT:
out (
0 downto 0));
1631 -- chipscope control signals
1635 signal data_ila_daq : (53 downto 0);
1636 signal trig_ila_daq : (33 downto 0);
1638 signal data_ila_encoder : (20 downto 0);
1639 signal trig_ila_encoder : (11 downto 0);
1641 signal data_ila_gtx_start : (12 downto 0);
1642 signal trig_ila_gtx_start : (2 downto 0);
1645 --signal data_ila_1 : std_logic_vector (16 downto 0);
1647 component glink_chipscope_analyzer
1649 CONTROL:
inout (
35 downto 0);
1651 DATA:
in (
53 downto 0);
1652 TRIG0:
in (
33 downto 0));
1655 component glink_chipscope_analyzer_encoder
1657 CONTROL:
inout (
35 downto 0);
1659 DATA:
in (
20 downto 0);
1660 TRIG0:
in (
11 downto 0));
1663 component glink_chipscope_analyzer_gtx_start
is
1665 CONTROL :
inout (
35 downto 0);
1667 DATA :
in (
10 downto 0);
1668 TRIG0 :
in (
0 to 0));
1669 end component glink_chipscope_analyzer_gtx_start;
1676 data_in :
in arr_96(
19 downto 0);
1689 signal RAM_global_offset : (7 downto 0);
1690 signal RAM_rel_offsets : arr_ctr_8bit(18 downto 0);
1691 signal nslices : (7 downto 0);
1693 signal data_in_daq: arr_96(19 downto 0);
1695 --control of daq delays
1696 signal data_from_vme_REG_RW_DAQ_SLICE: (15 downto 0);
1697 signal data_to_vme_REG_RW_DAQ_SLICE: (15 downto 0);
1698 signal data_from_vme_REG_RW_DAQ_RAM_OFFSET: (15 downto 0);
1699 signal data_to_vme_REG_RW_DAQ_RAM_OFFSET: (15 downto 0);
1701 signal data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1702 signal data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET: arr_16(18 downto 0);
1707 attribute keep of start_playback_r1, BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r, send_align, ODATA_first_half : signal is "TRUE";
1708 attribute IOB of BUF_TTC_L1_ACCEPT_r, BUF_TTC_BNCH_CNT_RES_r : signal is "FORCE";
1710 --attribute IOB of BF_DOUT_CTP_00 : signal is "TRUE";
1711 --attribute IOB of BF_DOUT_CTP_01 : signal is "TRUE";
1712 --attribute IOB of BF_DOUT_CTP_02 : signal is "TRUE";
1713 --attribute IOB of BF_DOUT_CTP_03 : signal is "TRUE";
1714 --attribute IOB of BF_DOUT_CTP_04 : signal is "TRUE";
1715 --attribute IOB of BF_DOUT_CTP_05 : signal is "TRUE";
1716 --attribute IOB of BF_DOUT_CTP_06 : signal is "TRUE";
1717 --attribute IOB of BF_DOUT_CTP_07 : signal is "TRUE";
1718 --attribute IOB of BF_DOUT_CTP_08 : signal is "TRUE";
1719 --attribute IOB of BF_DOUT_CTP_09 : signal is "TRUE";
1720 --attribute IOB of BF_DOUT_CTP_10 : signal is "TRUE";
1721 --attribute IOB of BF_DOUT_CTP_11 : signal is "TRUE";
1722 --attribute IOB of BF_DOUT_CTP_12 : signal is "TRUE";
1723 --attribute IOB of BF_DOUT_CTP_13 : signal is "TRUE";
1724 --attribute IOB of BF_DOUT_CTP_14 : signal is "TRUE";
1725 --attribute IOB of BF_DOUT_CTP_15 : signal is "TRUE";
1726 --attribute IOB of BF_DOUT_CTP_16 : signal is "TRUE";
1727 --attribute IOB of BF_DOUT_CTP_17 : signal is "TRUE";
1728 --attribute IOB of BF_DOUT_CTP_18 : signal is "TRUE";
1729 --attribute IOB of BF_DOUT_CTP_19 : signal is "TRUE";
1730 --attribute IOB of BF_DOUT_CTP_20 : signal is "TRUE";
1731 --attribute IOB of BF_DOUT_CTP_21 : signal is "TRUE";
1732 --attribute IOB of BF_DOUT_CTP_22 : signal is "TRUE";
1733 --attribute IOB of BF_DOUT_CTP_23 : signal is "TRUE";
1734 --attribute IOB of BF_DOUT_CTP_24 : signal is "TRUE";
1735 --attribute IOB of BF_DOUT_CTP_25 : signal is "TRUE";
1736 --attribute IOB of BF_DOUT_CTP_26 : signal is "TRUE";
1737 --attribute IOB of BF_DOUT_CTP_27 : signal is "TRUE";
1738 --attribute IOB of BF_DOUT_CTP_28 : signal is "TRUE";
1739 --attribute IOB of BF_DOUT_CTP_29 : signal is "TRUE";
1740 --attribute IOB of BF_DOUT_CTP_64 : signal is "TRUE";
1742 --attribute IOB of BF_DOUT_CTP_32 : signal is "TRUE";
1743 --attribute IOB of BF_DOUT_CTP_33 : signal is "TRUE";
1744 --attribute IOB of BF_DOUT_CTP_34 : signal is "TRUE";
1745 --attribute IOB of BF_DOUT_CTP_35 : signal is "TRUE";
1746 --attribute IOB of BF_DOUT_CTP_36 : signal is "TRUE";
1747 --attribute IOB of BF_DOUT_CTP_37 : signal is "TRUE";
1748 --attribute IOB of BF_DOUT_CTP_38 : signal is "TRUE";
1749 --attribute IOB of BF_DOUT_CTP_39 : signal is "TRUE";
1750 --attribute IOB of BF_DOUT_CTP_40 : signal is "TRUE";
1751 --attribute IOB of BF_DOUT_CTP_41 : signal is "TRUE";
1752 --attribute IOB of BF_DOUT_CTP_42 : signal is "TRUE";
1753 --attribute IOB of BF_DOUT_CTP_43 : signal is "TRUE";
1754 --attribute IOB of BF_DOUT_CTP_44 : signal is "TRUE";
1755 --attribute IOB of BF_DOUT_CTP_45 : signal is "TRUE";
1756 --attribute IOB of BF_DOUT_CTP_46 : signal is "TRUE";
1757 --attribute IOB of BF_DOUT_CTP_47 : signal is "TRUE";
1758 --attribute IOB of BF_DOUT_CTP_48 : signal is "TRUE";
1759 --attribute IOB of BF_DOUT_CTP_49 : signal is "TRUE";
1760 --attribute IOB of BF_DOUT_CTP_50 : signal is "TRUE";
1761 --attribute IOB of BF_DOUT_CTP_51 : signal is "TRUE";
1762 --attribute IOB of BF_DOUT_CTP_52 : signal is "TRUE";
1763 --attribute IOB of BF_DOUT_CTP_53 : signal is "TRUE";
1764 --attribute IOB of BF_DOUT_CTP_54 : signal is "TRUE";
1765 --attribute IOB of BF_DOUT_CTP_55 : signal is "TRUE";
1766 --attribute IOB of BF_DOUT_CTP_56 : signal is "TRUE";
1767 --attribute IOB of BF_DOUT_CTP_57 : signal is "TRUE";
1768 --attribute IOB of BF_DOUT_CTP_58 : signal is "TRUE";
1769 --attribute IOB of BF_DOUT_CTP_59 : signal is "TRUE";
1770 --attribute IOB of BF_DOUT_CTP_60 : signal is "TRUE";
1771 --attribute IOB of BF_DOUT_CTP_61 : signal is "TRUE";
1794 --BF_TO_FROM_BSPT_0 <= '0';
1795 --BF_TO_FROM_BSPT_1 <= '0';
1880 --ddr_data_in_CTP2(0) <=BF_DOUT_CTP_32;
1881 --ddr_data_in_CTP2(1) <=BF_DOUT_CTP_33;
1882 --ddr_data_in_CTP2(2) <=BF_DOUT_CTP_34;
1883 --ddr_data_in_CTP2(3) <=BF_DOUT_CTP_35;
1884 --ddr_data_in_CTP2(4) <=BF_DOUT_CTP_36;
1885 --ddr_data_in_CTP2(5) <=BF_DOUT_CTP_37;
1886 --ddr_data_in_CTP2(6) <=BF_DOUT_CTP_38;
1887 --ddr_data_in_CTP2(7) <=BF_DOUT_CTP_39;
1888 --ddr_data_in_CTP2(8) <=BF_DOUT_CTP_40;
1889 --ddr_data_in_CTP2(9) <=BF_DOUT_CTP_41;
1890 --ddr_data_in_CTP2(10) <=BF_DOUT_CTP_42;
1891 --ddr_data_in_CTP2(11) <=BF_DOUT_CTP_43;
1892 --ddr_data_in_CTP2(12) <=BF_DOUT_CTP_44;
1893 --ddr_data_in_CTP2(13) <=BF_DOUT_CTP_45;
1894 --ddr_data_in_CTP2(14) <=BF_DOUT_CTP_46;
1895 --ddr_data_in_CTP2(15) <=BF_DOUT_CTP_47;
1896 --ddr_data_in_CTP2(16) <=BF_DOUT_CTP_48;
1897 --ddr_data_in_CTP2(17) <=BF_DOUT_CTP_49;
1898 --ddr_data_in_CTP2(18) <=BF_DOUT_CTP_50;
1899 --ddr_data_in_CTP2(19) <=BF_DOUT_CTP_51;
1900 --ddr_data_in_CTP2(20) <=BF_DOUT_CTP_52;
1901 --ddr_data_in_CTP2(21) <=BF_DOUT_CTP_53;
1902 --ddr_data_in_CTP2(22) <=BF_DOUT_CTP_54;
1903 --ddr_data_in_CTP2(23) <=BF_DOUT_CTP_55;
1904 --ddr_data_in_CTP2(24) <=BF_DOUT_CTP_56;
1905 --ddr_data_in_CTP2(25) <=BF_DOUT_CTP_57;
1906 --ddr_data_in_CTP2(26) <=BF_DOUT_CTP_58;
1907 --ddr_data_in_CTP2(27) <=BF_DOUT_CTP_59;
1908 --ddr_data_in_CTP2(28) <=BF_DOUT_CTP_60;
1909 --ddr_data_in_CTP2(29) <=BF_DOUT_CTP_61;
1910 --ddr_data_in_CTP2(30) <=BF_DOUT_CTP_62;
1911 --ddr_data_in_CTP2(31) <=BF_DOUT_CTP_65;
1912 --ddr_data_in_CTP2(32) <=BF_DOUT_CTP_63;
2003 --backplane bus assignment
2463 --debug pins bus assignment
2475 --BF_DEBUG(8) <= buf_clk40;
2477 ODDR_inst_buf_clk_40 : ODDR
2479 DDR_CLK_EDGE =>
"SAME_EDGE",
-- "OPPOSITE_EDGE" or "SAME_EDGE"
2480 INIT => '0',
-- Initial value for Q port ('1' or '0')
2481 SRTYPE =>
"SYNC") -- Reset Type ("ASYNC" or "SYNC")
2483 Q => BF_DEBUG
(8),
-- 1-bit DDR output
2484 C => buf_clk40,
-- 1-bit clock input
2485 CE => '1',
-- 1-bit clock enable input
2486 D1 => '1',
-- 1-bit data input (positive edge)
2487 D2 => '0',
-- 1-bit data input (negative edge)
2488 R =>
(not pll_locked
),
-- 1-bit reset input
2489 S => '0'
-- 1-bit set input
2492 BF_DEBUG(9) <= l1a_synced;
-- DATA96(5)(0);--start_playback;--BF_TO_TP_DAQ_SLINK_RETURN_DIR;--send_align(0);-- BUF_TTC_BNCH_CNT_RES; --bunch counter reset
2494 BF_DEBUG(7 downto 0)<=(others=>'0');
2520 ------------------------------------------------------------------------------
2521 -- VME interface component used in BSPT FPGA (Ian's vme_interface)
2522 ------------------------------------------------------------------------------
2525 ----------------------------------------------------------------------------
2527 ----------------------------------------------------------------------------
2528 clk40 => buf_clk40 ,
2534 ----------------------------------------------------------------------------
2536 ----------------------------------------------------------------------------
2537 board_ds =>
ds,
-- board_ds output from VME (Ian model)
2538 brdsel_n =>
ncs -- brdsel_n output from VME (Ian model)
2560 clk40 => buf_clk40 ,
2608 if rising_edge(buf_clk40) then
2622 ia_vme => ADDR_REG_RO_test ,
2635 --vme_outreg_test: vme_outreg
2637 -- ia_vme => ADDR_REG_RO_test,
2640 -- clk => buf_clk40,
2641 -- addr_vme => vme_address(16 downto 1),
2643 -- rd_nwr => OCB_WRITE_B,
2645 -- data_to_vme => data_to_vme_test_r,
2646 -- read_detect => read_detect_outreg_test,
2647 -- data_vme => OCB_D);
2652 ia_vme => ADDR_REG_RW_test ,
2668 --vme_inreg_test: vme_inreg
2670 -- ia_vme => ADDR_REG_RW_test,
2673 -- clk => buf_clk40,
2675 -- rd_nwr => OCB_WRITE_B,
2677 -- data_from_vme => data_from_vme_test_rw,
2678 -- data_to_vme => data_to_vme_test_rw,
2679 -- addr_vme => vme_address(16 downto 1),
2680 -- read_detect => read_detect_inreg_test,
2681 -- write_detect => write_detect_inreg_test,
2682 -- data_vme => OCB_D);
2689 chipscope_icon_u2_c3_inst: chipscope_icon_u2_c3
2691 CONTROL0 => CONTROL0,
2692 CONTROL1 => CONTROL1,
2693 CONTROL2 => CONTROL2
2696 --chipscope_ila_CMX_top_inputmodclk_inst: chipscope_ila_CMX_top_inputmodclk
2698 -- CONTROL => CONTROL0,
2699 -- CLK => buf_clk40,
2700 -- DATA => DATA_chipscope_ila_CMX_top_inputmodclk,
2701 -- TRIG0 => TRIG0_chipscope_ila_CMX_top_inputmodclk);
2704 --TRIG0_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2705 --TRIG0_chipscope_ila_CMX_top_inputmodclk(33)<=start_playback;
2706 --TRIG0_chipscope_ila_CMX_top_inputmodclk(34)<='0';
2707 --TRIG0_chipscope_ila_CMX_top_inputmodclk(35)<=data_to_RTM(0);
2710 --DATA_chipscope_ila_CMX_top_inputmodclk(0)<=pll_locked;
2712 --gen_data_chipscope_ila: for ichannel in numactchan-1 downto 0 generate
2714 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(1+ichannel*2)<=PAR_ERROR(ichannel);
2715 -- TRIG0_chipscope_ila_CMX_top_inputmodclk(2+ichannel*2)<=counter_enable_inputmod_sig(ichannel);
2717 -- DATA_chipscope_ila_CMX_top_inputmodclk(1+ichannel*98)<=PAR_ERROR(ichannel);
2718 -- DATA_chipscope_ila_CMX_top_inputmodclk(2+ichannel*98)<=counter_enable_inputmod_sig(ichannel);
2719 -- DATA_chipscope_ila_CMX_top_inputmodclk(95+3+ichannel*98 downto 3+ichannel*98)<=DATA96(ichannel);
2721 --end generate gen_data_chipscope_ila;
2723 --DATA_chipscope_ila_CMX_top_inputmodclk(1630 downto 1569)<=(others=>'0');
2724 --DATA_chipscope_ila_CMX_top_inputmodclk(1682 downto 1631)<=data_to_RTM;
2725 --DATA_chipscope_ila_CMX_top_inputmodclk(1734 downto 1683)<=(others=>'0');
2726 --DATA_chipscope_ila_CMX_top_inputmodclk(1735)<=start_playback;
2727 --DATA_chipscope_ila_CMX_top_inputmodclk(2375 downto 1736) <= (others=>'0');
2734 clk40 => buf_clk40 ,
2745 --upload_delays<='0';
2746 --del_register<=(others=>(others=>(others=>'0')));
2750 reset => bc_reset_synced ,
2766 if rising_edge(buf_clk40) then
2781 --ODATA_WORD0 => open,
2802 ia_vme => ADDR_REG_RW_QUIET_FORCE ,
2815 data_to_vme_REG_RW_QUIET_FORCE<=data_from_vme_REG_RW_QUIET_FORCE;
2816 quiet<=data_from_vme_REG_RW_QUIET_FORCE(1);
2817 force<=data_from_vme_REG_RW_QUIET_FORCE(0);
2833 gen_REG_RW_JET_THRESHOLD_BLOCK: for i_thr in 1599 downto 0 generate
2837 ia_vme => ADDR_REG_RW_JET_THRESHOLD_BLOCK+2*i_thr,
2847 data_from_vme => data_from_vme_REG_RW_JET_THRESHOLD_BLOCK
(i_thr
),
2848 data_to_vme => data_to_vme_REG_RW_JET_THRESHOLD_BLOCK
(i_thr
));
2851 --vme_inreg_async_REG_RW_JET_THRESHOLD_BLOCK: vme_inreg_async
2853 -- ia_vme => ADDR_REG_RW_JET_THRESHOLD_BLOCK+2*i_thr,
2857 -- rd_nwr => OCB_WRITE_B,
2859 -- addr_vme => vme_address(16 downto 1),
2860 -- data_vme => OCB_D,
2861 -- data_from_vme => data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr),
2862 -- data_to_vme => data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr));
2864 data_to_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr)<=data_from_vme_REG_RW_JET_THRESHOLD_BLOCK(i_thr);
2865 end generate gen_REG_RW_JET_THRESHOLD_BLOCK;
2867 thresholds<=data_from_vme_REG_RW_JET_THRESHOLD_BLOCK;
2870 decoder_inst:
entity work.
decoder
2877 datai => DATA96
(14 downto 1),
2901 datai => DATA96
(14 downto 1),
2922 reset => counter_reset ,
2923 inhibit => counter_inhibit
2926 --dummy remote data for readout
2927 din_cbl(149 downto 144)<=(others=>'1');
2928 din_cbl(143 downto 0) <=(others=>'0');
2930 data_to_RTM1(23 downto 0) <= dout_cbla_mux0(23 downto 0);
2931 data_to_RTM1(49 downto 26) <= dout_cbla_mux1(23 downto 0);
2932 data_to_RTM1(25)<=dout_cbla_mux0(32);
2933 data_to_RTM1(51)<=dout_cbla_mux1(32);
2934 data_to_RTM1(24)<='0';
2935 data_to_RTM1(50)<=dout_lcl_ro;
2938 data_to_RTM(numbits_in_RTM_connector*2 -1 downto 0)<=data_to_RTM1;
2941 ddr_data_out_RTM1<=ddr_data_out_RTM(0);
2943 gen_dummy_loc_vme_bus: for i_dummy in 1640 to 1759 generate
2946 end generate gen_dummy_loc_vme_bus;
2950 data => data_to_RTM,
2966 --this address normally assigned to the rtm system cable input module
2970 --no CTP output for the 'crate' type CMX
2971 --CMX_CTP_output_module_inst: entity work.CMX_CTP_output_module
2974 -- sdr_data_out => sdr_data_CTP,
2975 -- buf_clk40 => buf_clk40,
2976 -- buf_clk40_center => buf_clk40_center,
2977 -- buf_clk200 => buf_clk200,
2978 -- pll_locked => pll_locked,
2979 -- start_playback => start_playback,
2980 -- spy_write_inhibit => spy_write_inhibit,
2982 -- rd_nwr => OCB_WRITE_B,
2984 -- addr_vme => vme_address(16 downto 1),
2985 -- data_vme => OCB_D);
3035 clk40 => buf_clk40_m90o,
3039 BCID => BCID_delayed_decoder,
3040 indata => indata_Topo_TX,
3053 --Topo_Data_TX_inst: Topo_Data_TX
3055 -- MGTREFCLK_PAD_N_IN => MGTREFCLK_PAD_N_IN,
3056 -- MGTREFCLK_PAD_P_IN => MGTREFCLK_PAD_P_IN,
3057 -- GTXTXRESET_IN => GTXTXRESET_IN,
3058 -- GTXRXRESET_IN => GTXRXRESET_IN,
3059 -- GTX_TX_READY_OUT => GTX_TX_READY_OUT,
3060 -- GTX_RX_READY_OUT => GTX_RX_READY_OUT,
3061 -- RXN_IN => RXN_IN,
3062 -- RXP_IN => RXP_IN,
3063 -- TXN_OUT => TXN_OUT,
3064 -- TXP_OUT => TXP_OUT,
3065 -- clk40 => buf_clk40,
3066 -- clk320 => buf_clk320,
3067 -- pll_locked => pll_locked,
3068 -- send_align => send_align,
3069 -- BCID => BCID_counter_sig,
3070 -- indata => indata_Topo_TX,
3071 -- ext_trigger => BF_TO_TP_DAQ_SLINK_RETURN_DIR,
3073 -- rd_nwr => OCB_WRITE_B,
3075 -- addr_vme => vme_address(16 downto 1),
3076 -- data_vme => OCB_D);
3080 -- --for the test make a fake data to send topo
3081 -- gen_indata_counter_fiber: for i_fiber in 0 to 23 generate
3082 -- process(buf_clk40)
3084 -- if rising_edge(buf_clk40) then
3085 -- if counter_fake_data_Topo_TX(i_fiber)(11 downto 0)=to_unsigned(0,12) then
3086 -- send_align(i_fiber)<='1';
3088 -- send_align(i_fiber)<='0';
3090 -- counter_fake_data_Topo_TX(i_fiber)<=counter_fake_data_Topo_TX(i_fiber)+1;
3095 -- PRNG_LFSR_BIG_inst: PRNG_LFSR_BIG
3097 -- clk => buf_clk40,
3098 -- rst => (not pll_locked),
3099 -- DATA_PRN => DATA_PRN(i_fiber) );
3101 -- --counter repeated twice for the msb words
3102 -- gen_data_counter_word: for i_word in 6 to 7 generate
3103 -- indata_Topo_TX(128*(i_fiber)+16*(i_word)+15 downto 128*(i_fiber)+16*(i_word))<=std_logic_vector(counter_fake_data_Topo_TX(i_fiber));
3104 -- end generate gen_data_counter_word;
3106 -- --then the 8 msb of the counter
3107 -- indata_Topo_TX(128*(i_fiber)+95 downto 128*(i_fiber)+88) <= std_logic_vector(counter_fake_data_Topo_TX(i_fiber)(15 downto 8));
3109 -- --then the mgt number
3110 -- indata_Topo_TX(128*(i_fiber)+87 downto 128*(i_fiber)+80) <= std_logic_vector(to_unsigned(i_fiber,8));
3112 -- --then the pseudo random number
3113 -- indata_Topo_TX(128*(i_fiber)+79 downto 128*(i_fiber)+16) <= DATA_PRN(i_fiber);
3116 -- --last 12 bits must be 0, four msb bits of the last word have the counter again
3117 -- indata_Topo_TX(128*(i_fiber)+15 downto 128*(i_fiber)+12) <= std_logic_vector(counter_fake_data_Topo_TX(i_fiber)(15 downto 12));
3118 -- indata_Topo_TX(128*(i_fiber)+11 downto 128*(i_fiber))<=(others=>'0');
3120 -- end generate gen_indata_counter_fiber;
3125 ia_vme => ADDR_REG_RW_TOPOTR_GTX_RESET ,
3136 data_to_vme => data_to_vme_REG_RW_TOPOTR_GTX_RESET
3139 GTXTXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(1);
3140 GTXRXRESET_IN<=data_from_vme_REG_RW_TOPOTR_GTX_RESET(0);
3142 data_to_vme_REG_RW_TOPOTR_GTX_RESET<=data_from_vme_REG_RW_TOPOTR_GTX_RESET;
3147 ia_vme => ADDR_REG_RO_TOPOTR_GTX_STATUS ,
3156 data_to_vme => data_to_vme_REG_RO_TOPOTR_GTX_STATUS
);
3158 data_to_vme_REG_RO_TOPOTR_GTX_STATUS(1)<=GTX_TX_READY_OUT;
3159 data_to_vme_REG_RO_TOPOTR_GTX_STATUS(0)<=GTX_RX_READY_OUT;
3161 data_to_vme_REG_RO_TOPOTR_GTX_STATUS(15 downto 2)<=(others=>'0');
3180 RXN_IN => RXN_IN_TX_SFP_DAQ ,
3181 RXP_IN => RXP_IN_TX_SFP_DAQ ,
3182 TXN_OUT => TXN_OUT_TX_SFP_DAQ,
3183 TXP_OUT => TXP_OUT_TX_SFP_DAQ,
3188 indata => indata_TX_SFP_DAQ ,
3189 odata => odata_TX_SFP_DAQ ,
3199 DFETAP1 => DFETAP1_TX_SFP_DAQ,
3201 DFETAP2 => DFETAP2_TX_SFP_DAQ,
3203 DFETAP3 => DFETAP3_TX_SFP_DAQ,
3205 DFETAP4 => DFETAP4_TX_SFP_DAQ,
3224 RXN_IN => RXN_IN_TX_SFP_ROI ,
3225 RXP_IN => RXP_IN_TX_SFP_ROI ,
3226 TXN_OUT => TXN_OUT_TX_SFP_ROI,
3227 TXP_OUT => TXP_OUT_TX_SFP_ROI,
3230 --other_sfp_pll_lock=> local_pll_lock_out_SFP_DAQ,
3233 indata => indata_TX_SFP_ROI ,
3234 odata => odata_TX_SFP_ROI ,
3244 DFETAP1 => DFETAP1_TX_SFP_ROI,
3246 DFETAP2 => DFETAP2_TX_SFP_ROI,
3248 DFETAP3 => DFETAP3_TX_SFP_ROI,
3250 DFETAP4 => DFETAP4_TX_SFP_ROI,
3259 CLK_40MHz => clk40_in_TX_SFP_ROI,
-- clk40MHz
3260 CLK_120MHz => clk120_in_TX_SFP_ROI ,
-- clk120MHz
3261 RST => reset_daq ,
--not pll_locked, --reset(0), -- reset
3262 DAQ_IN => daq_in,
-- Input data (DAQ)
3263 ROI_IN => roi_in,
-- Input data (ROI)
3264 DAQ_DAV => daq_dav,
-- Control (DAQ)
3265 ROI_DAV => roi_dav,
-- Control (ROI)
3266 DAQ_BYTE => daq_byte,
-- Output Byte (DAQ)
3267 ROI_BYTE => roi_byte,
-- Output Byte (ROI)
3276 );
-- daq_encoded_DIAG
3278 MGT_118_clk0_ibufds_i : IBUFDS_GTXE1
3281 O => MGTREFCLK_Q118,
3294 clk40_in_TX_SFP_ROI<=clk40_out_TX_SFP_DAQ;
3295 clk120_in_TX_SFP_ROI<=clk120_out_TX_SFP_DAQ;
3297 indata_TX_SFP_DAQ<=daq_byte;
-- from GLINK emulator
3298 indata_TX_SFP_ROI<=roi_byte;
-- from GLINK emulator;
3302 --vio_data_i : diagn_module_vio
3304 -- CONTROL => control1,
3305 -- ASYNC_OUT => reset);
3309 ia_vme => ADDR_REG_RW_DAQ_ROI_RESET ,
3322 reset_daq<=data_from_vme_REG_RW_DAQ_ROI_RESET(0);
3323 data_to_vme_REG_RW_DAQ_ROI_RESET<=data_from_vme_REG_RW_DAQ_ROI_RESET;
3327 ia_vme => ADDR_REG_RW_DAQ_ROI_GTX_RESET ,
3338 data_to_vme => data_to_vme_REG_RW_DAQ_ROI_GTX_RESET
);
3340 gtx_reset_SFP_DAQ<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(0);
3341 gtx_reset_SFP_ROI<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET(1);
3342 data_to_vme_REG_RW_DAQ_ROI_GTX_RESET<=data_from_vme_REG_RW_DAQ_ROI_GTX_RESET;
3347 ia_vme => ADDR_REG_RO_DAQ_ROI_STATUS ,
3356 data_to_vme => data_to_vme_REG_RO_DAQ_ROI_STATUS
);
3358 data_to_vme_REG_RO_DAQ_ROI_STATUS(0)<=local_pll_lock_out_SFP_DAQ;
3359 data_to_vme_REG_RO_DAQ_ROI_STATUS(1)<=GTX_TX_READY_OUT_TX_SFP_DAQ;
3360 data_to_vme_REG_RO_DAQ_ROI_STATUS(2)<=GTX_RX_READY_OUT_TX_SFP_DAQ;
3361 data_to_vme_REG_RO_DAQ_ROI_STATUS(3)<=PLLLKDET_diag_TX_SFP_DAQ;
3362 data_to_vme_REG_RO_DAQ_ROI_STATUS(4)<=local_pll_lock_out_SFP_ROI;
3363 data_to_vme_REG_RO_DAQ_ROI_STATUS(5)<=GTX_TX_READY_OUT_TX_SFP_ROI;
3364 data_to_vme_REG_RO_DAQ_ROI_STATUS(6)<=GTX_RX_READY_OUT_TX_SFP_ROI;
3365 data_to_vme_REG_RO_DAQ_ROI_STATUS(7)<=PLLLKDET_diag_TX_SFP_ROI;
3366 data_to_vme_REG_RO_DAQ_ROI_STATUS(8)<=readout_rst_out;
3368 data_to_vme_REG_RO_DAQ_ROI_STATUS(15 downto 9) <= (others=>'0');
3371 -- Chipscope analyzer
3373 ila_daq_glink : glink_chipscope_analyzer
3375 CONTROL => control0,
3376 CLK => clk40_in_TX_SFP_ROI ,
3377 DATA => data_ila_daq ,
3378 TRIG0 => trig_ila_daq
);
3380 ila_glink_encoder : glink_chipscope_analyzer_encoder
3382 CONTROL => control1,
3383 CLK => clk120_in_TX_SFP_ROI ,
3384 DATA => data_ila_encoder ,
3385 TRIG0 => trig_ila_encoder
);
3387 ila_gtx_start:
entity work.glink_chipscope_analyzer_gtx_start
3389 CONTROL => CONTROL2,
3390 CLK => MGTREFCLK_Q118 ,
3391 DATA => data_ila_gtx_start ,
3392 TRIG0 => trig_ila_gtx_start
);
3394 data_ila_daq <= daq_in &
3397 local_pll_lock_out_SFP_DAQ &
3398 GTX_TX_READY_OUT_TX_SFP_DAQ &
3399 GTX_RX_READY_OUT_TX_SFP_DAQ &
3400 local_pll_lock_out_SFP_ROI &
3401 GTX_TX_READY_OUT_TX_SFP_ROI &
3402 GTX_RX_READY_OUT_TX_SFP_ROI &
3408 trig_ila_daq <= daq_encoded_diag &
3410 local_pll_lock_out_SFP_DAQ &
3411 GTX_TX_READY_OUT_TX_SFP_DAQ &
3412 GTX_RX_READY_OUT_TX_SFP_DAQ &
3413 local_pll_lock_out_SFP_ROI &
3414 GTX_TX_READY_OUT_TX_SFP_ROI &
3415 GTX_RX_READY_OUT_TX_SFP_ROI &
3422 trig_ila_encoder <= GTX_TX_READY_OUT_TX_SFP_DAQ &
3428 data_ila_encoder <= byte_pos_out &
3431 GTX_TX_READY_OUT_TX_SFP_DAQ &
3437 trig_ila_gtx_start(0)<=pll_locked;
3438 trig_ila_gtx_start(1)<=gtx_reset_SFP_DAQ;
3439 trig_ila_gtx_start(2)<=gtx_reset_SFP_ROI;
3443 data_ila_gtx_start(0)<= pll_locked;
3444 data_ila_gtx_start(1)<= gtx_reset_SFP_DAQ;
3445 data_ila_gtx_start(2)<= gtx_reset_SFP_ROI;
3446 data_ila_gtx_start(3)<= GTX_TX_READY_OUT_TX_SFP_DAQ;
3447 data_ila_gtx_start(4)<= PLLLKDET_diag_TX_SFP_DAQ;
3448 data_ila_gtx_start(5)<= local_gtx_reset_diag_TX_SFP_DAQ;
3449 data_ila_gtx_start(6)<= local_mmcm_reset_diag_TX_SFP_DAQ;
3450 data_ila_gtx_start(7)<= GTXTEST_diag_TX_SFP_DAQ;
3451 data_ila_gtx_start(8)<= GTX_TX_READY_OUT_TX_SFP_ROI;
3452 data_ila_gtx_start(9)<= PLLLKDET_diag_TX_SFP_ROI;
3453 data_ila_gtx_start(10)<= local_gtx_reset_diag_TX_SFP_ROI;
3454 data_ila_gtx_start(11)<= local_mmcm_reset_diag_TX_SFP_ROI;
3455 data_ila_gtx_start(12)<= GTXTEST_diag_TX_SFP_ROI;
3460 if rising_edge(buf_clk40) then
3461 l1a_synced<=BUF_TTC_L1_ACCEPT_r;
3464 bc_reset_synced<=BUF_TTC_BNCH_CNT_RES_r;
3477 clk4000 => clk40_out_TX_SFP_DAQ ,
3479 reset => reset_daq ,
--not pll_locked,
3485 --in this flavor roi and daq have the same behavior
3489 --readout control registers
3492 ia_vme => ADDR_REG_RW_DAQ_SLICE,
3505 nslices(1 downto 0) <= (data_to_vme_REG_RW_DAQ_SLICE(1 downto 0));
3506 nslices(7 downto 2) <= (others=>'0');
3508 data_to_vme_REG_RW_DAQ_SLICE<=data_from_vme_REG_RW_DAQ_SLICE;
3513 ia_vme => ADDR_REG_RW_DAQ_RAM_OFFSET ,
3524 data_to_vme => data_to_vme_REG_RW_DAQ_RAM_OFFSET
);
3526 data_to_vme_REG_RW_DAQ_RAM_OFFSET<=data_from_vme_REG_RW_DAQ_RAM_OFFSET;
3527 RAM_global_offset <= (data_from_vme_REG_RW_DAQ_RAM_OFFSET(7 downto 0));
3530 rel_offset_gen: for i_row in 1 to 19 generate
3533 ia_vme =>
(ADDR_REG_RW_DAQ_RAM_RELATIVE_OFFSET+2*
(i_row-
1)),
3543 data_from_vme => data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET
(i_row-
1),
3544 data_to_vme => data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET
(i_row-
1));
3546 data_to_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)<=data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1);
3547 RAM_rel_offsets(i_row-1)<=(data_from_vme_REG_RW_DAQ_RAM_RELATIVE_OFFSET(i_row-1)(7 downto 0));
3548 end generate rel_offset_gen;
3554 datai => DATA96
(14 downto 1),
3561 dout =>
(others =>'0'
),
out BF_DOUT_CTP_41std_logic
in BF_SYSMON_13_NSTD_LOGIC
out TXN_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
in BF_SYSMON_14_PSTD_LOGIC
out BF_DOUT_CTP_01std_logic
out BF_TO_FROM_BSPT_2std_logic
out BF_DAQ_DATA_OUT_CMPstd_logic
in CLK_120MHz000_XTAL_1_BF_TRNCV_DIRstd_logic
in BF_SYSMON_09_PSTD_LOGIC
out data_vme_outstd_logic_vector (15 downto 0)
in BF_TO_TP_ROI_SLINK_RETURN_CMPstd_logic
out BF_TO_FROM_BSPT_3std_logic
out MP1_F11_QUAD_111_TRN_1_CMPstd_logic
out write_detectstd_logic
std_logic read_detect_inreg_test
out BF_LED_REQ_4std_logic
in start_playbackstd_logic
in BF_TO_FROM_BSPT_0std_logic
out BF_DOUT_CTP_61std_logic
out data_in_daqarr_96 (19 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out data_vme_outstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_34std_logic
in MGTREFCLK_PAD_N_INstd_logic_vector (num_GTX_groups - 1 downto 0)
out MP1_F04_QUAD_112_TRN_0_DIRstd_logic
inout data_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_32std_logic
in data_inarr_96 (19 downto 0)
in buf_clk40_centerstd_logic
out data_vme_outstd_logic_vector (15 downto 0)
out Tobs_to_TOPOcopy_arr_TOB
in datai_first_halfarr_2Xword (max_jems - 1 downto 0)
out MP1_F07_QUAD_110_TRN_2_DIRstd_logic
out data_vmestd_logic_vector (15 downto 0)
out BF_TO_FROM_BSPT_6std_logic
out data_vme_outstd_logic_vector (15 downto 0)
out local_gtx_reset_diagstd_logic
out DFETAP2MONITORstd_logic_vector (4 downto 0)
in counter_inhibitstd_logic
out BF_LED_REQ_1std_logic
out MP2_F01_QUAD_113_TRN_0_CMPstd_logic
in data_vme_instd_logic_vector (15 downto 0)
out BF_DOUT_CTP_21std_logic
out MP1_F10_QUAD_111_TRN_2_DIRstd_logic
std_logic_vector (15 downto 0) data_to_vme_test_rw
out BF_DOUT_CTP_46std_logic
in addr_vmestd_logic_vector (15 downto 0)
in DFETAP4std_logic_vector (3 downto 0)
in BF_SYSMON_03_NSTD_LOGIC
out BF_DOUT_CTP_04std_logic
in BF_SYSMON_10_PSTD_LOGIC
out BF_DOUT_CTP_65std_logic
out BF_DOUT_CTP_55std_logic
in BF_SYSMON_13_NSTD_LOGIC
std_logic_vector (15 downto 0) data_vme_up_top
in BF_SYSMON_13_PSTD_LOGIC
out BF_DOUT_CTP_19std_logic
in BF_SYSMON_12_PSTD_LOGIC
in TXDIFFCTRL_INstd_logic_vector (3 downto 0)
out dout_cbla_mux0std_logic_vector (33 downto 0)
out BF_DOUT_CTP_14std_logic
out BF_DOUT_CTP_47std_logic
out dout_lclstd_logic_vector (59 downto 0)
in BF_SYSMON_01_NSTD_LOGIC
inout data_vmestd_logic_vector (15 downto 0)
the tri-stated port
in BF_SYSMON_10_NSTD_LOGIC
out BF_LED_REQ_2std_logic
in BF_TO_TP_DAQ_SLINK_RETURN_DIRstd_logic
out MP2_F11_QUAD_114_TRN_1_DIRstd_logic
out data_from_vmestd_logic_vector (width - 1 downto 0)
in RAM_rel_offsetsarr_ctr_8bit (18 downto 0)
out BF_LED_REQ_0std_logic
out BF_DOUT_CTP_00std_logic
out BCID_outstd_logic_vector (11 downto 0)
in TXPREEMPHASIS_INstd_logic_vector (3 downto 0)
out data_from_vmestd_logic_vector (width - 1 downto 0)
in CLK_320MHz64_LHC_BF_QUAD_114_DIRstd_logic
in BF_SYSMON_03_PSTD_LOGIC
out Data_outstd_logic_vector (TX_indata_length - 1 downto 0)
std_logic_vector (15 downto 0) data_to_vme_outreg_test
out MP2_F07_QUAD_113_TRN_2_DIRstd_logic
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out del_registerdel_register_type
out BF_DOUT_CTP_49std_logic
in BF_SYSMON_09_NSTD_LOGIC
in BF_SYSMON_13_PSTD_LOGIC
in data_vme_instd_logic_vector (15 downto 0)
out BF_DOUT_CTP_64std_logic
out MP1_F04_QUAD_112_TRN_0_CMPstd_logic
out DFECLKDLYADJMONstd_logic_vector (5 downto 0)
out BCID_delayedstd_logic_vector (11 downto 0)
in BF_SYSMON_15_PSTD_LOGIC
out data_vme_outstd_logic_vector (15 downto 0)
in BF_SYSMON_03_NSTD_LOGIC
out data_from_vmestd_logic_vector (width - 1 downto 0)
out BF_ROI_DATA_OUT_DIRstd_logic
in BF_SYSMON_11_NSTD_LOGIC
in data_vme_from_belowarr_16
--! inputs from local registers and from
out data_from_vmestd_logic_vector (width - 1 downto 0)
out GTXTEST_diagstd_logic
in bus_drive_from_belowstd_logic
--! a request to drive the outside
in addr_vmestd_logic_vector (15 downto 0)
out MP1_F01_QUAD_110_TRN_0_DIRstd_logic
in BF_SYSMON_07_NSTD_LOGIC
out BF_DOUT_CTP_05std_logic
in data_vme_instd_logic_vector (15 downto 0)
out BF_DOUT_CTP_50std_logic
in BCID_instd_logic_vector (11 downto 0)
in BF_SYSMON_14_NSTD_LOGIC
in Tobs_to_TOPOcopy_arr_TOB
in BF_SYSMON_01_NSTD_LOGIC
out MP2_F04_QUAD_115_TRN_0_CMPstd_logic
out data_vmestd_logic_vector (15 downto 0)
in CLK_40MHz08_DSKW_2_BF_LOGIC_CMPstd_logic
in BF_SYSMON_04_NSTD_LOGIC
in data_vme_instd_logic_vector (15 downto 0)
out buf_clk40_m180ostd_logic
in BF_SYSMON_12_PSTD_LOGIC
out MP2_F04_QUAD_115_TRN_0_DIRstd_logic
in addr_vmestd_logic_vector (15 downto 0)
std_logic_vector (23 downto 1) vme_address
out BF_DOUT_CTP_57std_logic
out BF_DOUT_CTP_42std_logic
in addr_vmestd_logic_vector (15 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
in send_alignstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out BF_DOUT_CTP_51std_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
out BF_DOUT_CTP_54std_logic
out MP1_F02_QUAD_112_TRN_2_DIRstd_logic
in BF_TO_FROM_BSPT_1std_logic
out BF_DOUT_CTP_45std_logic
in BF_SYSMON_07_PSTD_LOGIC
out data_vme_outstd_logic_vector (15 downto 0)
out BCID_delayedstd_logic_vector (11 downto 0)
out write_detectstd_logic
out MP2_F08_QUAD_114_TRN_3_DIRstd_logic
arr_16 (1762 downto 0) data_vme_from_below_top
out BF_DOUT_CTP_60std_logic
std_logic bus_drive_up_top
out data_vme_outstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_07std_logic
out BF_TO_FROM_BSPT_5std_logic
out MP2_F01_QUAD_113_TRN_0_DIRstd_logic
out local_mmcm_reset_diagstd_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
in DFETAP3std_logic_vector (3 downto 0)
out MP1_F07_QUAD_110_TRN_2_CMPstd_logic
in addr_vmestd_logic_vector (15 downto 0)
in BF_SYSMON_09_PSTD_LOGIC
out DFEEYEDACMONstd_logic_vector (4 downto 0)
out data_vme_outstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_17std_logic
in BF_SYSMON_01_PSTD_LOGIC
out BF_DOUT_CTP_31std_logic
out BF_DOUT_CTP_38std_logic
out BF_DOUT_CTP_37std_logic
out MP2_F08_QUAD_114_TRN_3_CMPstd_logic
in addr_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_29std_logic
out BF_REQ_CABLE_3_INPUTstd_logic
out BF_DOUT_CTP_35std_logic
in nslicesunsigned (7 downto 0)
out BF_DOUT_CTP_26std_logic
out BF_DOUT_CTP_39std_logic
out GTX_RX_READY_OUTstd_logic
out BF_DOUT_CTP_23std_logic
in DFECLKDLYADJstd_logic_vector (5 downto 0)
out MP2_F09_QUAD_114_TRN_0_DIRstd_logic
out BF_DOUT_CTP_16std_logic
out data_vme_outstd_logic_vector (15 downto 0)
out local_pll_lock_outstd_logic
std_logic_vector (numactchan - 1 downto 0) counter_values
out dout_cbla_mux1std_logic_vector (33 downto 0)
in BF_SYSMON_10_NSTD_LOGIC
out upload_delaysstd_logic
in clk40MHz_m90ostd_logic
out data_vme_going_belowstd_logic_vector (15 downto 0)
in TXPOSTEMPHASIS_INstd_logic_vector (4 downto 0)
in vme_addressstd_logic_vector (23 downto 1)
std_logic start_playback_r1
out data_vme_outstd_logic_vector (15 downto 0)
std_logic_vector (15 downto 0) data_vme_going_below
in data_to_vmestd_logic_vector (width - 1 downto 0)
out MP1_F00_QUAD_112_TRN_3_CMPstd_logic
out BF_DOUT_CTP_28std_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
in GTXRXRESET_INstd_logic
in MGTREFCLK_PAD_P_INstd_logic_vector (num_GTX_groups - 1 downto 0)
in BF_SYSMON_04_NSTD_LOGIC
in BF_SYSMON_14_PSTD_LOGIC
std_logic_vector (15 downto 0) data_from_vme_test_rw
out data_vme_upstd_logic_vector (15 downto 0)
--! connect this to
out send_align_outstd_logic_vector (num_GTX_groups * num_GTX_per_group - 1 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_24std_logic
in bc_counterunsigned (11 downto 0)
in BF_TO_TP_DAQ_SLINK_RETURN_CMPstd_logic
out GTX_TX_READY_OUTstd_logic
in BF_SYSMON_09_NSTD_LOGIC
out BF_DOUT_CTP_53std_logic
out MP2_F02_QUAD_115_TRN_2_DIRstd_logic
in addr_vmestd_logic_vector (15 downto 0)
out BF_REQ_CABLE_1_INPUTstd_logic
std_logic read_detect_outreg_test
del_register_type del_register
in addr_vmestd_logic_vector (15 downto 0)
out MP2_F09_QUAD_114_TRN_0_CMPstd_logic
in data_vme_instd_logic_vector (15 downto 0)
in datastd_logic_vector (numbits_in_RTM_connector * 2 * num_RTM_cables - 1 downto 0)
in CLK_120MHz000_XTAL_1_BF_TRNCV_CMPstd_logic
out BF_DOUT_CTP_18std_logic
out BF_DOUT_CTP_06std_logic
out BF_DOUT_CTP_27std_logic
out BF_DOUT_CTP_43std_logic
out MP2_F03_QUAD_113_TRN_1_DIRstd_logic
out data_vme_outstd_logic_vector (15 downto 0)
in BF_SYSMON_11_NSTD_LOGIC
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
std_logic_vector (15 downto 0) data_to_vme_test_r
out MP2_F11_QUAD_114_TRN_1_CMPstd_logic
in dataiarr_4Xword (max_jems - 1 downto 0)
out DFETAP3MONITORstd_logic_vector (3 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
out TXP_OUTstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out MP1_F00_QUAD_112_TRN_3_DIRstd_logic
out MP1_F06_QUAD_112_TRN_1_CMPstd_logic
in BF_SYSMON_11_PSTD_LOGIC
out GTX_RX_READY_OUTstd_logic
in BF_SYSMON_01_PSTD_LOGIC
out BF_DOUT_CTP_58std_logic
out BF_DOUT_CTP_10std_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
in OCB_SYS_RESET_Bstd_logic
in BCID_instd_logic_vector (11 downto 0)
in DFETAP1std_logic_vector (4 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out bus_drive_upstd_logic
or of all bus drive requests from below
out BF_DOUT_CTP_03std_logic
in BUF_TTC_BNCH_CNT_RESstd_logic
out MP2_F10_QUAD_114_TRN_2_CMPstd_logic
gen_systemstd_logic :='1'
in RAM_global_offsetunsigned (7 downto 0)
out MP1_F10_QUAD_111_TRN_2_CMPstd_logic
in BF_SYSMON_07_PSTD_LOGIC
in data_vme_instd_logic_vector (15 downto 0)
out ddr_data_outarr_RTM (num_RTM_cables - 1 downto 0)
in BF_SYSMON_08_NSTD_LOGIC
out counter_inhibitstd_logic
out MP1_F09_QUAD_111_TRN_0_DIRstd_logic
out BF_REQ_CTP_1_INPUTstd_logic
out BF_LED_REQ_3std_logic
out data_vme_outstd_logic_vector (15 downto 0)
out BF_TO_FROM_BSPT_7std_logic
out BF_DOUT_CTP_25std_logic
in CLK_320MHz64_LHC_BF_QUAD_114_CMPstd_logic
in BF_SYSMON_14_NSTD_LOGIC
in data_vme_instd_logic_vector (15 downto 0)
in BF_SYSMON_07_NSTD_LOGIC
out ROI_BYTEstd_logic_vector (7 downto 0)
in BF_SYSMON_08_PSTD_LOGIC
out DFETAP4MONITORstd_logic_vector (3 downto 0)
out MP1_F05_QUAD_110_TRN_3_DIRstd_logic
out BF_DOUT_CTP_20std_logic
in BF_SYSMON_15_NSTD_LOGIC
in data_vme_from_belowstd_logic_vector (15 downto 0)
--! input: ORed
out buf_clk40_m90ostd_logic
in ROI_INstd_logic_vector (19 downto 0)
out MP1_F06_QUAD_112_TRN_1_DIRstd_logic
out BF_DOUT_CTP_30std_logic
in BF_SYSMON_11_PSTD_LOGIC
out MP2_F05_QUAD_113_TRN_3_DIRstd_logic
in addr_vmestd_logic_vector (15 downto 0)
out MP1_F09_QUAD_111_TRN_0_CMPstd_logic
out MP1_F05_QUAD_110_TRN_3_CMPstd_logic
in BUF_TTC_L1_ACCEPTstd_logic
in addr_vmestd_logic_vector (15 downto 0)
in BF_SYSMON_08_NSTD_LOGIC
in BF_SYSMON_10_PSTD_LOGIC
in RXEQMIX_INstd_logic_vector (2 downto 0)
out BF_DAQ_DATA_OUT_DIRstd_logic
out BF_DOUT_CTP_22std_logic
in indatastd_logic_vector (7 downto 0)
out BF_DOUT_CTP_08std_logic
out daq_byte_outstd_logic_vector (1 downto 0)
in CLK_320MHz64_LHC_BF_QUAD_111_CMPstd_logic
ADDR_REG_RO_SYSMON_DATA_BLOCKinteger :=16#1364#
out counter_resetstd_logic
in data_to_vmestd_logic_vector (width - 1 downto 0)
out BF_TO_FROM_BSPT_4std_logic
out data_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_09std_logic
out odatastd_logic_vector (7 downto 0)
in addr_vmestd_logic_vector (15 downto 0)
out MP1_F08_QUAD_111_TRN_3_CMPstd_logic
out GTX_TX_READY_OUTstd_logic
in BF_SYSMON_15_PSTD_LOGIC
in CLK_320MHz64_LHC_BF_QUAD_111_DIRstd_logic
out MP1_F11_QUAD_111_TRN_1_DIRstd_logic
out MP1_F03_QUAD_110_TRN_1_CMPstd_logic
out BF_REQ_CABLE_2_INPUTstd_logic
out MP2_F03_QUAD_113_TRN_1_CMPstd_logic
out readout_rst_outstd_logic
out data_vme_outstd_logic_vector (15 downto 0)
out pll_locked_ds2std_logic
in OCB_GEO_ADRS_0std_logic
out spy_write_inhibitstd_logic
out DFETAP1MONITORstd_logic_vector (4 downto 0)
out MP2_F10_QUAD_114_TRN_2_DIRstd_logic
in DFETAP2std_logic_vector (4 downto 0)
in indatastd_logic_vector (TX_indata_length - 1 downto 0)
out BF_DOUT_CTP_63std_logic
in BF_SYSMON_03_PSTD_LOGIC
in spy_write_inhibitstd_logic
in BF_SYSMON_04_PSTD_LOGIC
in BCIDstd_logic_vector (11 downto 0)
out BF_DOUT_CTP_40std_logic
in dataiarr_4Xword (max_jems - 1 downto 0)
out PLLLKDET_diagstd_logic
in BF_SYSMON_04_PSTD_LOGIC
out BF_ROI_DATA_OUT_CMPstd_logic
out BF_DOUT_CTP_15std_logic
out BF_DOUT_CTP_62std_logic
out byte_pos_outstd_logic_vector (5 downto 0)
out overflowstd_logic_vector (num_copies - 1 downto 0)
out BF_DOUT_CTP_33std_logic
in addr_vmestd_logic_vector (15 downto 0)
in BF_SYSMON_15_NSTD_LOGIC
out MP2_F00_QUAD_115_TRN_3_DIRstd_logic
in addr_vmestd_logic_vector (15 downto 0)
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out word_sel_outstd_logic_vector (1 downto 0)
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
unsigned (15 downto 0) test_rw_counter
in DAQ_INstd_logic_vector (19 downto 0)
out DFESENSCALstd_logic_vector (2 downto 0)
in CLK_40MHz08_DSKW_1_BF_LOGIC_CMPstd_logic
out buf_clk40_90ostd_logic
out BF_DOUT_CTP_48std_logic
in dataiarr_4Xword (max_jems - 1 downto 0)
out BF_DOUT_CTP_44std_logic
in BF_SYSMON_08_PSTD_LOGIC
out BF_DOUT_CTP_52std_logic
std_logic_vector (1762 downto 0) bus_drive_from_below_top
out DAQ_ENCODED_DIAGstd_logic_vector (23 downto 0)
out BF_REQ_CTP_2_INPUTstd_logic
out DAQ_BYTEstd_logic_vector (7 downto 0)
out MP1_F02_QUAD_112_TRN_2_CMPstd_logic
out MP2_F00_QUAD_115_TRN_3_CMPstd_logic
in BF_SYSMON_12_NSTD_LOGIC
in thresholdsarr_16 (max_jems * 25 * 4 - 1 downto 0)
out MP2_F05_QUAD_113_TRN_3_CMPstd_logic
out MP1_F08_QUAD_111_TRN_3_DIRstd_logic
std_logic write_detect_inreg_test
in clk40MHz_m180ostd_logic
in data_vme_instd_logic_vector (15 downto 0)
inout OCB_Dstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_02std_logic
out MP1_F01_QUAD_110_TRN_0_CMPstd_logic
inout data_vmestd_logic_vector (15 downto 0)
in data_vme_instd_logic_vector (15 downto 0)
in data_to_vmestd_logic_vector (width - 1 downto 0)
in CLK_40MHz08_DSKW_1_BF_LOGIC_DIRstd_logic
out BF_DOUT_CTP_13std_logic
out MP2_F02_QUAD_115_TRN_2_CMPstd_logic
out MP2_F06_QUAD_115_TRN_1_CMPstd_logic
out buf_clk40_ds2std_logic
out BF_DOUT_CTP_59std_logic
in CLK_40MHz08_DSKW_2_BF_LOGIC_DIRstd_logic
in BF_TO_TP_ROI_SLINK_RETURN_DIRstd_logic
out BF_DOUT_CTP_56std_logic
in GTXTXRESET_INstd_logic
out MP2_F07_QUAD_113_TRN_2_CMPstd_logic
in addr_vmestd_logic_vector (15 downto 0)
out BF_DOUT_CTP_11std_logic
in counter_resetstd_logic
out BF_DOUT_CTP_36std_logic
out MP1_F03_QUAD_110_TRN_1_DIRstd_logic
out data_outstd_logic_vector (19 downto 0)
in bus_drive_from_belowstd_logic_vector
in BF_SYSMON_12_NSTD_LOGIC
ADDR_REG_RW_PIPELINE_DELAY_LENGTHinteger :=0
in overflowstd_logic_vector (num_copies - 1 downto 0)
out MP2_F06_QUAD_115_TRN_1_DIRstd_logic
out BF_DOUT_CTP_12std_logic