1 --------------------------------------------------------------------------------
5 -- Create Date: 21:51:17 02/02/2010
7 -- Module Name: C:/DESIGN/PP_Design/vtrig/v0/vtrg/CMX_top_Base_tb.vhd
13 -- VHDL Test Bench Created by ISE for module: trigger
18 -- Revision 0.01 - File Created
19 -- Additional Comments:
22 -- This testbench has been automatically generated using types std_logic and
23 -- std_logic_vector for the ports of the unit under test. Xilinx recommends
24 -- that these types always be used for the top-level I/O of a design in order
25 -- to guarantee that the testbench will bind correctly to the post-implementation
27 --------------------------------------------------------------------------------
30 USE ieee.std_logic_1164.
ALL;
31 USE ieee.std_logic_unsigned.
all;
32 USE ieee.numeric_std.
ALL;
33 use ieee.std_logic_textio.
all;
49 -- Component Declaration for the Unit Under Test (UUT)
82 variable temp: (inp'range) := (others => 'X');
84 for i in inp'range loop
85 if (inp(i) = '1') then
87 elsif (inp(i) = '0') then
94 ---------------------------------------------------------------------------
95 -- Function INT2SLV converts an integer to a std_logic_vector
96 ---------------------------------------------------------------------------
102 variable result: (size-1 downto 0);
107 for i in 0 to size-1 loop
108 if (temp mod 2) = 1 then
116 elsif (temp > 'low) then
117 temp := (temp - 1) / 2;
-- simulate ASR
119 temp := temp / 2;
-- simulate ASR
126 ---------------------------------------------------------------------------
127 -- Function INT2SLV16 converts an integer to a 16 bit std_logic_vector
128 ---------------------------------------------------------------------------
145 signal CLK80 : := '0';
147 -- Clock period definitions
155 FILE data_jem0: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test0.txt";
156 FILE data_jem1: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test1.txt";
157 FILE data_jem2: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test2.txt";
158 FILE data_jem3: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test3.txt";
159 FILE data_jem4: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test4.txt";
160 FILE data_jem5: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test5.txt";
161 FILE data_jem6: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test6.txt";
162 FILE data_jem7: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test7.txt";
163 FILE data_jem8: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test8.txt";
164 FILE data_jem9: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test9.txt";
165 FILE data_jem10: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test10.txt";
166 FILE data_jem11: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test11.txt";
167 FILE data_jem12: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test12.txt";
168 FILE data_jem13: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test13.txt";
169 FILE data_jem14: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test14.txt";
170 FILE data_jem15: TEXT
open READ_MODE
is "../../Jet_common/trunk/data/test15.txt";
194 type mystring is array(15 downto 0) of (24 downto 1);
--always counts from one
198 -- Clock period definitions
201 constant OFFSET : := 0 ns;
202 constant zero : :='0';
203 signal zeros : (15 downto 0) := (others => '0');
204 signal P : mat_var (numactchan-1 downto 0):=(others => (others => '0'));
210 ----------------------------------------------------------------------------
211 -- VME-- backplane (65 signals)
212 ----------------------------------------------------------------------------
213 --GEOADDR0: in std_logic; -- GeoAddr0
215 --VMEADDR: in std_logic_vector(23 downto 1); -- Address bus
239 --VMEDS_L: in std_logic; -- DS strobe VMEDS_L
241 --VMEWR_L: in std_logic; -- VME Write VMEWR_L
243 --VMERST_L: in std_logic; -- System reset VMERST_L
245 --VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA
246 OCB_D:
inout (
15 downto 0);
247 ----------------------------------------------------------------------------
652 --CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
653 --CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
658 --CLK_320MHz64_LHC_BF_LOGIC_DIR : in std_logic;
659 --CLK_320MHz64_LHC_BF_LOGIC_CMP : in std_logic;
868 signal OCB_A: (23 downto 0);
869 signal OCB_D: (15 downto 0);
874 --011 1000 0000 0010 1011 0001
886 -- Instantiate the Unit Under Test (UUT)
888 ----------------------------------------------------------------------------
889 -- VME-- backplane (65 signals)
890 ----------------------------------------------------------------------------
919 ----------------------------------------------------------------------------
1545 -- Clock process definitions
1557 -- Clock process definitions
1569 -- Clock process definitions
1578 END LOOP CLOCK_LOOP;
1582 -- Clock process definitions
1591 END LOOP CLOCK_LOOP;
1595 clock_gen: for i in 0 to 15 generate
1599 --strobe for vme the fixed vme write so reset is '0'
1600 zeros<=(others=>'0');
1608 OCB_D<=(others=>'0');
1616 OCB_D<=(others=>'0');
1624 OCB_D<=(to_unsigned(50,16));
1632 OCB_D<=(to_unsigned(350,16));
1673 -- Test Bench Statements, JEM0
1680 -- Add user defined stimulus here
1681 while true -- not endfile(data_jem0)
1688 file_close(data_jem0);
1690 wait;
-- will wait forever
1696 -- Test Bench Statements, JEM1
1702 -- Add user defined stimulus here
1703 while true -- not endfile(data_jem1)
1710 file_close(data_jem1);
1712 wait;
-- will wait forever
1716 -- Test Bench Statements, JEM2
1722 -- Add user defined stimulus here
1723 while true -- not endfile(data_jem2)
1730 file_close(data_jem2);
1732 wait;
-- will wait forever
1737 -- Test Bench Statements, JEM3
1743 -- Add user defined stimulus here
1744 while true -- not endfile(data_jem3)
1751 file_close(data_jem3);
1753 wait;
-- will wait forever
1757 -- Test Bench Statements, JEM4
1763 -- Add user defined stimulus here
1764 while true -- not endfile(data_jem4)
1771 file_close(data_jem4);
1773 wait;
-- will wait forever
1777 -- Test Bench Statements, JEM5
1783 -- Add user defined stimulus here
1784 while true -- not endfile(data_jem5)
1791 file_close(data_jem5);
1793 wait;
-- will wait forever
1797 -- Test Bench Statements, JEM6
1803 -- Add user defined stimulus here
1804 while true -- not endfile(data_jem6)
1811 file_close(data_jem6);
1813 wait;
-- will wait forever
1817 -- Test Bench Statements, JEM7
1823 -- Add user defined stimulus here
1824 while true -- not endfile(data_jem7)
1831 file_close(data_jem7);
1833 wait;
-- will wait forever
1837 -- Test Bench Statements, JEM8
1843 -- Add user defined stimulus here
1844 while true -- not endfile(data_jem8)
1851 file_close(data_jem8);
1853 wait;
-- will wait forever
1857 -- Test Bench Statements, JEM1
1862 -- Add user defined stimulus here
1863 while true -- not endfile(data_jem9)
1870 file_close(data_jem9);
1872 wait;
-- will wait forever
1876 -- Test Bench Statements, JEM10
1882 -- Add user defined stimulus here
1883 while true -- not endfile(data_jem10)
1890 file_close(data_jem10);
1892 wait;
-- will wait forever
1896 -- Test Bench Statements, JEM11
1902 -- Add user defined stimulus here
1903 while true -- not endfile(data_jem11)
1910 file_close(data_jem11);
1912 wait;
-- will wait forever
1916 -- Test Bench Statements, JEM1
1922 -- Add user defined stimulus here
1923 while true -- not endfile(data_jem12)
1930 file_close(data_jem12);
1932 wait;
-- will wait forever
1936 -- Test Bench Statements, JEM13
1942 -- Add user defined stimulus here
1943 while true -- not endfile(data_jem13)
1950 file_close(data_jem13);
1952 wait;
-- will wait forever
1955 -- Test Bench Statements, JEM14
1961 -- Add user defined stimulus here
1962 while true -- not endfile(data_jem14)
1969 file_close(data_jem14);
1971 wait;
-- will wait forever
1975 -- Test Bench Statements, JEM15
1981 -- Add user defined stimulus here
1982 while true -- not endfile(data_jem15)
1989 file_close(data_jem15);
1991 wait;
-- will wait forever
2000 -- PROCESS -- clock process for USR_CLK
2003 -- CLOCK_LOOP : LOOP
2005 -- WAIT FOR (PERIOD_USR_CLK - (PERIOD_USR_CLK * DUTY_CYCLE));
2007 -- WAIT FOR (PERIOD_USR_CLK * DUTY_CYCLE);
2008 -- END LOOP CLOCK_LOOP;
2012 -- -- Trigger Output
2016 -- if (USR_CLK='1' AND USR_CLK'EVENT) then
2017 -- if TRG_OUT='1' then
2018 -- write(trigsave, HT); -- put the tab
2019 -- write(trigsave,slv2int(EDEP(0,1)));
2020 -- writeline(data_trig_out,trigsave);
2023 -- END PROCESS tb_trigout;
out BF_DOUT_CTP_41std_logic
out BF_DOUT_CTP_01std_logic
out BF_TO_FROM_BSPT_2std_logic
time :=6.238 ns CLK160_period
out BF_DAQ_DATA_OUT_CMPstd_logic
in CLK_120MHz000_XTAL_1_BF_TRNCV_DIRstd_logic
in BF_TO_TP_ROI_SLINK_RETURN_CMPstd_logic
out BF_TO_FROM_BSPT_3std_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test15.txt" data_jem15
out BF_LED_REQ_4std_logic
in BF_TO_FROM_BSPT_0std_logic
out BF_DOUT_CTP_61std_logic
out BF_DOUT_CTP_34std_logic
out BF_DOUT_CTP_32std_logic
string (23 downto 1) memstring
out BF_TO_FROM_BSPT_6std_logic
std_logic_vector INT2SLV16val,
out BF_LED_REQ_1std_logic
out BF_DOUT_CTP_21std_logic
out BF_DOUT_CTP_46std_logic
out BF_DOUT_CTP_04std_logic
out BF_DOUT_CTP_65std_logic
out BF_DOUT_CTP_55std_logic
out BF_DOUT_CTP_19std_logic
out BF_DOUT_CTP_14std_logic
out BF_DOUT_CTP_47std_logic
time :=12.476 ns CLK80_period
out BF_LED_REQ_2std_logic
in BF_TO_TP_DAQ_SLINK_RETURN_DIRstd_logic
out BF_LED_REQ_0std_logic
out BF_DOUT_CTP_00std_logic
out BF_DOUT_CTP_49std_logic
out BF_DOUT_CTP_64std_logic
out BF_ROI_DATA_OUT_DIRstd_logic
out BF_DOUT_CTP_05std_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test14.txt" data_jem14
out BF_DOUT_CTP_50std_logic
out BF_DOUT_CTP_57std_logic
out BF_DOUT_CTP_42std_logic
std_logic :='0' CLK_120MHz000_XTAL_1_BF_TRNCV_DIR
out BF_DOUT_CTP_51std_logic
out BF_DOUT_CTP_54std_logic
in BF_TO_FROM_BSPT_1std_logic
out BF_DOUT_CTP_45std_logic
time :=8.334 ns CLK120_period
out BF_DOUT_CTP_60std_logic
out BF_DOUT_CTP_07std_logic
out BF_TO_FROM_BSPT_5std_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test9.txt" data_jem9
TEXT open READ_MODE is "../../Jet_common/trunk/data/test3.txt" data_jem3
out BF_DOUT_CTP_17std_logic
out BF_DOUT_CTP_31std_logic
out BF_DOUT_CTP_38std_logic
out BF_DOUT_CTP_37std_logic
out BF_DOUT_CTP_29std_logic
out BF_REQ_CABLE_3_INPUTstd_logic
out BF_DOUT_CTP_35std_logic
out BF_DOUT_CTP_26std_logic
out BF_DOUT_CTP_39std_logic
out BF_DOUT_CTP_23std_logic
out BF_DOUT_CTP_16std_logic
std_logic_vector str_to_stdvecinp,
std_logic :='0' CLK40_DIR
out BF_DOUT_CTP_28std_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test7.txt" data_jem7
time :=12.5 ns PERIOD_USR_CLK
TEXT open READ_MODE is "../../Jet_common/trunk/data/test4.txt" data_jem4
out BF_DOUT_CTP_24std_logic
in BF_TO_TP_DAQ_SLINK_RETURN_CMPstd_logic
out BF_DOUT_CTP_53std_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test5.txt" data_jem5
TEXT open READ_MODE is "../../Jet_common/trunk/data/test10.txt" data_jem10
out BF_REQ_CABLE_1_INPUTstd_logic
in CLK_120MHz000_XTAL_1_BF_TRNCV_CMPstd_logic
out BF_DOUT_CTP_18std_logic
out BF_DOUT_CTP_06std_logic
out BF_DOUT_CTP_27std_logic
out BF_DOUT_CTP_43std_logic
mat_var (numactchan - 1 downto 0) :=( others =>( others =>'0' ) ) P
time :=24.952 ns CLK40_DIR_period
out BF_DOUT_CTP_58std_logic
out BF_DOUT_CTP_10std_logic
in OCB_SYS_RESET_Bstd_logic
out BF_DOUT_CTP_03std_logic
in BUF_TTC_BNCH_CNT_RESstd_logic
out BF_REQ_CTP_1_INPUTstd_logic
out BF_LED_REQ_3std_logic
std_logic :='0' CLK_120MHz000_XTAL_1_BF_TRNCV_CMP
out BF_TO_FROM_BSPT_7std_logic
out BF_DOUT_CTP_25std_logic
std_logic BUF_TTC_BNCH_CNT_RES
std_logic_vector (23 downto 0) OCB_A
out BF_DOUT_CTP_20std_logic
std_logic_vector INT2SLVval,size,
out BF_DOUT_CTP_30std_logic
std_logic_vector (15 downto 0) OCB_D
in BUF_TTC_L1_ACCEPTstd_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test0.txt" data_jem0
out BF_DAQ_DATA_OUT_DIRstd_logic
out BF_DOUT_CTP_22std_logic
out BF_DOUT_CTP_08std_logic
out BF_TO_FROM_BSPT_4std_logic
out BF_DOUT_CTP_09std_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test12.txt" data_jem12
out BF_REQ_CABLE_2_INPUTstd_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test8.txt" data_jem8
in OCB_GEO_ADRS_0std_logic
out BF_DOUT_CTP_63std_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test6.txt" data_jem6
out BF_DOUT_CTP_40std_logic
std_logic_vector (15 downto 0) :=( others =>'0' ) zeros
std_logic :='0' CLK40_CMP
out BF_ROI_DATA_OUT_CMPstd_logic
out BF_DOUT_CTP_15std_logic
out BF_DOUT_CTP_62std_logic
out BF_DOUT_CTP_33std_logic
std_logic_vector (7 downto 0) OCB_A_BOARD_ADDR
in CLK_40MHz08_DSKW_1_BF_LOGIC_CMPstd_logic
out BF_DOUT_CTP_48std_logic
out BF_DOUT_CTP_44std_logic
out BF_DOUT_CTP_52std_logic
out BF_REQ_CTP_2_INPUTstd_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test13.txt" data_jem13
TEXT open READ_MODE is "../../Jet_common/trunk/data/test11.txt" data_jem11
inout OCB_Dstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_02std_logic
std_logic_vector (15 downto 0) OCB_A_LOCAL_ADDR
in CLK_40MHz08_DSKW_1_BF_LOGIC_DIRstd_logic
out BF_DOUT_CTP_13std_logic
TEXT open READ_MODE is "../../Jet_common/trunk/data/test1.txt" data_jem1
out BF_DOUT_CTP_59std_logic
in BF_TO_TP_ROI_SLINK_RETURN_DIRstd_logic
out BF_DOUT_CTP_56std_logic
out BF_DOUT_CTP_11std_logic
out BF_DOUT_CTP_36std_logic
array (15 downto 0 ) of string (24 downto 1) mystring
out BF_DOUT_CTP_12std_logic