1 --------------------------------------------------------------------------------
5 -- Create Date: 21:51:17 02/02/2010
7 -- Module Name: C:/DESIGN/PP_Design/vtrig/v0/vtrg/CMX_top_Base_tb.vhd
13 -- VHDL Test Bench Created by ISE for module: trigger
18 -- Revision 0.01 - File Created
19 -- Additional Comments:
22 -- This testbench has been automatically generated using types std_logic and
23 -- std_logic_vector for the ports of the unit under test. Xilinx recommends
24 -- that these types always be used for the top-level I/O of a design in order
25 -- to guarantee that the testbench will bind correctly to the post-implementation
27 --------------------------------------------------------------------------------
30 USE ieee.std_logic_1164.
ALL;
31 USE ieee.std_logic_unsigned.
all;
32 USE ieee.numeric_std.
ALL;
33 use ieee.std_logic_textio.
all;
49 -- Component Declaration for the Unit Under Test (UUT)
82 variable temp: (inp'range) := (others => 'X');
84 for i in inp'range loop
85 if (inp(i) = '1') then
87 elsif (inp(i) = '0') then
94 ---------------------------------------------------------------------------
95 -- Function INT2SLV converts an integer to a std_logic_vector
96 ---------------------------------------------------------------------------
102 variable result: (size-1 downto 0);
107 for i in 0 to size-1 loop
108 if (temp mod 2) = 1 then
116 elsif (temp > 'low) then
117 temp := (temp - 1) / 2;
-- simulate ASR
119 temp := temp / 2;
-- simulate ASR
126 ---------------------------------------------------------------------------
127 -- Function INT2SLV16 converts an integer to a 16 bit std_logic_vector
128 ---------------------------------------------------------------------------
145 signal CLK80 : := '0';
147 -- Clock period definitions.
148 -- Note: periods must be even multiples of 1 ps to make ISE happy
155 -- FILE ctp_out: TEXT open READ_MODE is "../../Jet_common/trunk/data/testctp.txt";
156 -- FILE data_jem0: TEXT open READ_MODE is "../../Jet_common/trunk/data/test0.txt";
157 -- FILE data_jem1: TEXT open READ_MODE is "../../Jet_common/trunk/data/test1.txt";
158 -- FILE data_jem2: TEXT open READ_MODE is "../../Jet_common/trunk/data/test2.txt";
159 -- FILE data_jem3: TEXT open READ_MODE is "../../Jet_common/trunk/data/test3.txt";
160 -- FILE data_jem4: TEXT open READ_MODE is "../../Jet_common/trunk/data/test4.txt";
161 -- FILE data_jem5: TEXT open READ_MODE is "../../Jet_common/trunk/data/test5.txt";
162 -- FILE data_jem6: TEXT open READ_MODE is "../../Jet_common/trunk/data/test6.txt";
163 -- FILE data_jem7: TEXT open READ_MODE is "../../Jet_common/trunk/data/test7.txt";
164 -- FILE data_jem8: TEXT open READ_MODE is "../../Jet_common/trunk/data/test8.txt";
165 -- FILE data_jem9: TEXT open READ_MODE is "../../Jet_common/trunk/data/test9.txt";
166 -- FILE data_jem10: TEXT open READ_MODE is "../../Jet_common/trunk/data/test10.txt";
167 -- FILE data_jem11: TEXT open READ_MODE is "../../Jet_common/trunk/data/test11.txt";
168 -- FILE data_jem12: TEXT open READ_MODE is "../../Jet_common/trunk/data/test12.txt";
169 -- FILE data_jem13: TEXT open READ_MODE is "../../Jet_common/trunk/data/test13.txt";
170 -- FILE data_jem14: TEXT open READ_MODE is "../../Jet_common/trunk/data/test14.txt";
171 -- FILE data_jem15: TEXT open READ_MODE is "../../Jet_common/trunk/data/test15.txt";
173 -- FILE ctp_out: TEXT open READ_MODE is "data/testctp.txt";
174 -- FILE data_jem0: TEXT open READ_MODE is "data/test0.txt";
175 -- FILE data_jem1: TEXT open READ_MODE is "data/test1.txt";
176 -- FILE data_jem2: TEXT open READ_MODE is "data/test2.txt";
177 -- FILE data_jem3: TEXT open READ_MODE is "data/test3.txt";
178 -- FILE data_jem4: TEXT open READ_MODE is "data/test4.txt";
179 -- FILE data_jem5: TEXT open READ_MODE is "data/test5.txt";
180 -- FILE data_jem6: TEXT open READ_MODE is "data/test6.txt";
181 -- FILE data_jem7: TEXT open READ_MODE is "data/test7.txt";
182 -- FILE data_jem8: TEXT open READ_MODE is "data/test8.txt";
183 -- FILE data_jem9: TEXT open READ_MODE is "data/test9.txt";
184 -- FILE data_jem10: TEXT open READ_MODE is "data/test10.txt";
185 -- FILE data_jem11: TEXT open READ_MODE is "data/test11.txt";
186 -- FILE data_jem12: TEXT open READ_MODE is "data/test12.txt";
187 -- FILE data_jem13: TEXT open READ_MODE is "data/test13.txt";
188 -- FILE data_jem14: TEXT open READ_MODE is "data/test14.txt";
189 -- FILE data_jem15: TEXT open READ_MODE is "data/test15.txt";
193 -- SHARED VARIABLE trigsave : LINE;
195 -- Clock and zero definitions
198 constant OFFSET : := 0 ns;
199 constant zero : :='0';
200 signal zeros : (15 downto 0) := (others => '0');
202 -- Other important signals
204 signal P : mat_var (numactchan-1 downto 0):=(others => (others => '0'));
208 signal ctp_error : ;
-- Mismatch between CTP output and input
209 constant ctp_delay : := 10;
-- delay between input and CTP output
215 ----------------------------------------------------------------------------
216 -- VME-- backplane (65 signals)
217 ----------------------------------------------------------------------------
218 --GEOADDR0: in std_logic; -- GeoAddr0
220 --VMEADDR: in std_logic_vector(23 downto 1); -- Address bus
244 --VMEDS_L: in std_logic; -- DS strobe VMEDS_L
246 --VMEWR_L: in std_logic; -- VME Write VMEWR_L
248 --VMERST_L: in std_logic; -- System reset VMERST_L
250 --VMEDATA: inout std_logic_vector(15 downto 0); -- Data bus VMEDATA
251 OCB_D:
inout (
15 downto 0);
252 ----------------------------------------------------------------------------
657 --CLK_40MHz08_DSKW_2_BF_LOGIC_DIR : in std_logic;
658 --CLK_40MHz08_DSKW_2_BF_LOGIC_CMP : in std_logic;
666 --CLK_320MHz64_LHC_BF_LOGIC_DIR : in std_logic;
667 --CLK_320MHz64_LHC_BF_LOGIC_CMP : in std_logic;
923 --clk40 : in std_logic;
924 RXN_IN :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0);
925 RXP_IN :
in ((num_GTX_per_group*num_GTX_groups)
-1 downto 0)
933 signal OCB_A: (23 downto 0);
934 signal OCB_D: (15 downto 0);
939 --011 1000 0000 0010 1011 0001
951 -- Instantiate the Unit Under Test (UUT)
953 ----------------------------------------------------------------------------
954 -- VME-- backplane (65 signals)
955 ----------------------------------------------------------------------------
984 ----------------------------------------------------------------------------
1663 --clk40 : in std_logic;
1664 RXN_IN =>
(others => '0'
),
-- not connected (unused)
1665 RXP_IN =>
(others => '0'
) -- not connected (unused)
1670 -- Clock process definitions
1682 -- Clock process definitions
1694 -- Clock process definitions
1714 clock_gen: for i in 0 to 15 generate
1715 P(i)<= clk80 & "ZZZZZZZZZZZZZZZZZZZZZZZZ";
1718 --strobe for vme the fixed vme write so reset is '0'
1719 zeros<=(others=>'0');
1747 OCB_D<=(others=>'0');
1755 OCB_D<=(others=>'0');
1763 OCB_D<=(to_unsigned(7,16));
1771 OCB_D<=(to_unsigned(350,16));
1851 type mystring
is array(15 downto 0) of (24 downto 1);
--always counts from one
1855 for i in 0 to 15 loop -- Blank backplane data
1856 P(i) <= 'Z' & "100000000000000000000000";
1859 WAIT until (clk160'event and clk160='1');
-- Synchronize with backplane timing
1860 -- while not endfile (data_jem0) loop -- assume all files have equal length
1861 -- -- Read lines from input files:
1862 -- readline(data_jem0,fileline_jem0);
1863 -- readline(data_jem1,fileline_jem1);
1864 -- readline(data_jem2,fileline_jem2);
1865 -- readline(data_jem3,fileline_jem3);
1866 -- readline(data_jem4,fileline_jem4);
1867 -- readline(data_jem5,fileline_jem5);
1868 -- readline(data_jem6,fileline_jem6);
1869 -- readline(data_jem7,fileline_jem7);
1870 -- readline(data_jem8,fileline_jem8);
1871 -- readline(data_jem9,fileline_jem9);
1872 -- readline(data_jem10,fileline_jem10);
1873 -- readline(data_jem11,fileline_jem11);
1874 -- readline(data_jem12,fileline_jem12);
1875 -- readline(data_jem13,fileline_jem13);
1876 -- readline(data_jem14,fileline_jem14);
1877 -- readline(data_jem15,fileline_jem15);
1878 -- -- Extract data strings from the lines
1879 -- read(fileline_jem0,dstring(0));
1880 -- read(fileline_jem1,dstring(1));
1881 -- read(fileline_jem2,dstring(2));
1882 -- read(fileline_jem3,dstring(3));
1883 -- read(fileline_jem4,dstring(4));
1884 -- read(fileline_jem5,dstring(5));
1885 -- read(fileline_jem6,dstring(6));
1886 -- read(fileline_jem7,dstring(7));
1887 -- read(fileline_jem8,dstring(8));
1888 -- read(fileline_jem9,dstring(9));
1889 -- read(fileline_jem10,dstring(10));
1890 -- read(fileline_jem11,dstring(11));
1891 -- read(fileline_jem12,dstring(12));
1892 -- read(fileline_jem13,dstring(13));
1893 -- read(fileline_jem14,dstring(14));
1894 -- read(fileline_jem15,dstring(15));
1895 -- -- Finally, enter the extracted data into the backplane inputs
1896 -- for i in 0 to 15 loop
1897 -- P(i) <= 'Z' & str_to_stdvec(dstring(i)(24 downto 1));
1899 -- WAIT until (clk160'event and clk160='1');
1901 for i in 0 to 15 loop -- Blank backplane data
1902 P(i) <= 'Z' & "100000000000000000000000";
1905 wait;
-- Wait forever
1906 end process JEM_INPUTS;
-- end of input stimulus process;
1908 -- invert the (already inverted) CTP output for convenience sake
1912 "000111111111111111111111111111111000111111111111111111111111111111");
1914 --CTP_OUTPUT : process
1916 -- VARIABLE fileline_ctp : LINE;
1917 -- VARIABLE ctpstring : string(32 downto 1);
1920 -- ctpvec_low <= (others => '0');
1921 -- ctpvec_high <= (others => '0');
1922 -- WAIT for 5500 ns;
1923 -- WAIT for clk40_DIR_period * ctp_delay;
1924 -- WAIT until (clk40_DIR'event and clk40_DIR='1'); -- Synchronize with backplane timing
1925 -- while not endfile (ctp_out) loop -- assume all files have equal length
1926 -- readline(ctp_out,fileline_ctp);
1927 -- read (fileline_ctp, ctpstring);
1928 -- ctpvec_low <= str_to_stdvec(ctpstring(32 downto 1));
1929 -- readline(ctp_out,fileline_ctp);
1930 -- read (fileline_ctp, ctpstring);
1931 -- ctpvec_high <= str_to_stdvec(ctpstring(32 downto 1));
1932 -- WAIT until (clk40_DIR'event and clk40_DIR='1');
1934 -- ctpvec_low <= (others => '0');
1935 -- ctpvec_high <= (others => '0');
1937 --end process CTP_OUTPUT;
1939 -- build the reference vector
1958 -- PROCESS -- clock process for USR_CLK
1961 -- CLOCK_LOOP : LOOP
1963 -- WAIT FOR (PERIOD_USR_CLK - (PERIOD_USR_CLK * DUTY_CYCLE));
1965 -- WAIT FOR (PERIOD_USR_CLK * DUTY_CYCLE);
1966 -- END LOOP CLOCK_LOOP;
1970 -- -- Trigger Output
1974 -- if (USR_CLK='1' AND USR_CLK'EVENT) then
1975 -- if TRG_OUT='1' then
1976 -- write(trigsave, HT); -- put the tab
1977 -- write(trigsave,slv2int(EDEP(0,1)));
1978 -- writeline(data_trig_out,trigsave);
1981 -- END PROCESS tb_trigout;
out BF_DOUT_CTP_41std_logic
out BF_DOUT_CTP_01std_logic
out BF_TO_FROM_BSPT_2std_logic
time :=6.238 ns CLK160_period
out BF_DAQ_DATA_OUT_CMPstd_logic
in CLK_120MHz000_XTAL_1_BF_TRNCV_DIRstd_logic
in BF_TO_TP_ROI_SLINK_RETURN_CMPstd_logic
out BF_TO_FROM_BSPT_3std_logic
out MP1_F11_QUAD_111_TRN_1_CMPstd_logic
out BF_LED_REQ_4std_logic
in BF_TO_FROM_BSPT_0std_logic
out BF_DOUT_CTP_61std_logic
out BF_DOUT_CTP_34std_logic
out MP1_F04_QUAD_112_TRN_0_DIRstd_logic
out BF_DOUT_CTP_32std_logic
out MP1_F07_QUAD_110_TRN_2_DIRstd_logic
out BF_TO_FROM_BSPT_6std_logic
std_logic_vector INT2SLV16val,
out BF_LED_REQ_1std_logic
out MP2_F01_QUAD_113_TRN_0_CMPstd_logic
out BF_DOUT_CTP_21std_logic
out MP1_F10_QUAD_111_TRN_2_DIRstd_logic
out BF_DOUT_CTP_46std_logic
out BF_DOUT_CTP_04std_logic
out BF_DOUT_CTP_65std_logic
out BF_DOUT_CTP_55std_logic
out BF_DOUT_CTP_19std_logic
out BF_DOUT_CTP_14std_logic
out BF_DOUT_CTP_47std_logic
time :=12.476 ns CLK80_period
out BF_LED_REQ_2std_logic
in BF_TO_TP_DAQ_SLINK_RETURN_DIRstd_logic
out MP2_F11_QUAD_114_TRN_1_DIRstd_logic
out BF_LED_REQ_0std_logic
out BF_DOUT_CTP_00std_logic
in CLK_320MHz64_LHC_BF_QUAD_114_DIRstd_logic
out MP2_F07_QUAD_113_TRN_2_DIRstd_logic
in RXP_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
out BF_DOUT_CTP_49std_logic
out BF_DOUT_CTP_64std_logic
out MP1_F04_QUAD_112_TRN_0_CMPstd_logic
out BF_ROI_DATA_OUT_DIRstd_logic
out MP1_F01_QUAD_110_TRN_0_DIRstd_logic
out BF_DOUT_CTP_05std_logic
out BF_DOUT_CTP_50std_logic
out MP2_F04_QUAD_115_TRN_0_CMPstd_logic
in CLK_40MHz08_DSKW_2_BF_LOGIC_CMPstd_logic
out MP2_F04_QUAD_115_TRN_0_DIRstd_logic
out BF_DOUT_CTP_57std_logic
out BF_DOUT_CTP_42std_logic
std_logic_vector (31 downto 0) ctpvec_low
std_logic :='0' CLK_120MHz000_XTAL_1_BF_TRNCV_DIR
out BF_DOUT_CTP_51std_logic
out BF_DOUT_CTP_54std_logic
out MP1_F02_QUAD_112_TRN_2_DIRstd_logic
in BF_TO_FROM_BSPT_1std_logic
out BF_DOUT_CTP_45std_logic
time :=8.334 ns CLK120_period
out MP2_F08_QUAD_114_TRN_3_DIRstd_logic
out BF_DOUT_CTP_60std_logic
out BF_DOUT_CTP_07std_logic
out BF_TO_FROM_BSPT_5std_logic
out MP2_F01_QUAD_113_TRN_0_DIRstd_logic
out MP1_F07_QUAD_110_TRN_2_CMPstd_logic
out BF_DOUT_CTP_17std_logic
out BF_DOUT_CTP_31std_logic
out BF_DOUT_CTP_38std_logic
out BF_DOUT_CTP_37std_logic
out MP2_F08_QUAD_114_TRN_3_CMPstd_logic
out BF_DOUT_CTP_29std_logic
out BF_REQ_CABLE_3_INPUTstd_logic
out BF_DOUT_CTP_35std_logic
out BF_DOUT_CTP_26std_logic
out BF_DOUT_CTP_39std_logic
out BF_DOUT_CTP_23std_logic
out MP2_F09_QUAD_114_TRN_0_DIRstd_logic
out BF_DOUT_CTP_16std_logic
out MP1_F00_QUAD_112_TRN_3_CMPstd_logic
std_logic_vector str_to_stdvecinp,
std_logic :='0' CLK40_DIR
out BF_DOUT_CTP_28std_logic
out BF_DOUT_CTP_24std_logic
in BF_TO_TP_DAQ_SLINK_RETURN_CMPstd_logic
out BF_DOUT_CTP_53std_logic
out MP2_F02_QUAD_115_TRN_2_DIRstd_logic
out BF_REQ_CABLE_1_INPUTstd_logic
out MP2_F09_QUAD_114_TRN_0_CMPstd_logic
in CLK_120MHz000_XTAL_1_BF_TRNCV_CMPstd_logic
out BF_DOUT_CTP_18std_logic
out BF_DOUT_CTP_06std_logic
out BF_DOUT_CTP_27std_logic
out BF_DOUT_CTP_43std_logic
mat_var (numactchan - 1 downto 0) :=( others =>( others =>'0' ) ) P
out MP2_F03_QUAD_113_TRN_1_DIRstd_logic
in RXN_INstd_logic_vector ((num_GTX_per_group * num_GTX_groups) - 1 downto 0)
time :=24.952 ns CLK40_DIR_period
out MP2_F11_QUAD_114_TRN_1_CMPstd_logic
out MP1_F00_QUAD_112_TRN_3_DIRstd_logic
out MP1_F06_QUAD_112_TRN_1_CMPstd_logic
out BF_DOUT_CTP_58std_logic
out BF_DOUT_CTP_10std_logic
in OCB_SYS_RESET_Bstd_logic
out BF_DOUT_CTP_03std_logic
in BUF_TTC_BNCH_CNT_RESstd_logic
out MP2_F10_QUAD_114_TRN_2_CMPstd_logic
out MP1_F10_QUAD_111_TRN_2_CMPstd_logic
out MP1_F09_QUAD_111_TRN_0_DIRstd_logic
out BF_REQ_CTP_1_INPUTstd_logic
out BF_LED_REQ_3std_logic
std_logic :='0' CLK_120MHz000_XTAL_1_BF_TRNCV_CMP
out BF_TO_FROM_BSPT_7std_logic
out BF_DOUT_CTP_25std_logic
in CLK_320MHz64_LHC_BF_QUAD_114_CMPstd_logic
std_logic_vector (31 downto 0) ctpvec_high
std_logic BUF_TTC_BNCH_CNT_RES
std_logic_vector (23 downto 0) OCB_A
out MP1_F05_QUAD_110_TRN_3_DIRstd_logic
out BF_DOUT_CTP_20std_logic
out MP1_F06_QUAD_112_TRN_1_DIRstd_logic
std_logic_vector INT2SLVval,size,
out BF_DOUT_CTP_30std_logic
out MP2_F05_QUAD_113_TRN_3_DIRstd_logic
std_logic_vector (15 downto 0) OCB_D
out MP1_F09_QUAD_111_TRN_0_CMPstd_logic
out MP1_F05_QUAD_110_TRN_3_CMPstd_logic
in BUF_TTC_L1_ACCEPTstd_logic
out BF_DAQ_DATA_OUT_DIRstd_logic
out BF_DOUT_CTP_22std_logic
out BF_DOUT_CTP_08std_logic
in CLK_320MHz64_LHC_BF_QUAD_111_CMPstd_logic
out BF_TO_FROM_BSPT_4std_logic
out BF_DOUT_CTP_09std_logic
out MP1_F08_QUAD_111_TRN_3_CMPstd_logic
in CLK_320MHz64_LHC_BF_QUAD_111_DIRstd_logic
out MP1_F11_QUAD_111_TRN_1_DIRstd_logic
out MP1_F03_QUAD_110_TRN_1_CMPstd_logic
out BF_REQ_CABLE_2_INPUTstd_logic
out MP2_F03_QUAD_113_TRN_1_CMPstd_logic
in OCB_GEO_ADRS_0std_logic
out MP2_F10_QUAD_114_TRN_2_DIRstd_logic
out BF_DOUT_CTP_63std_logic
out BF_DOUT_CTP_40std_logic
std_logic_vector (15 downto 0) :=( others =>'0' ) zeros
std_logic :='0' CLK40_CMP
out BF_ROI_DATA_OUT_CMPstd_logic
out BF_DOUT_CTP_15std_logic
out BF_DOUT_CTP_62std_logic
out BF_DOUT_CTP_33std_logic
std_logic_vector (65 downto 0) CTPout
out MP2_F00_QUAD_115_TRN_3_DIRstd_logic
std_logic_vector (7 downto 0) OCB_A_BOARD_ADDR
in CLK_40MHz08_DSKW_1_BF_LOGIC_CMPstd_logic
out BF_DOUT_CTP_48std_logic
out BF_DOUT_CTP_44std_logic
out BF_DOUT_CTP_52std_logic
std_logic_vector (65 downto 0) CTPout_ref
out BF_REQ_CTP_2_INPUTstd_logic
out MP1_F02_QUAD_112_TRN_2_CMPstd_logic
out MP2_F00_QUAD_115_TRN_3_CMPstd_logic
out MP2_F05_QUAD_113_TRN_3_CMPstd_logic
out MP1_F08_QUAD_111_TRN_3_DIRstd_logic
inout OCB_Dstd_logic_vector (15 downto 0)
out BF_DOUT_CTP_02std_logic
std_logic_vector (15 downto 0) OCB_A_LOCAL_ADDR
out MP1_F01_QUAD_110_TRN_0_CMPstd_logic
in CLK_40MHz08_DSKW_1_BF_LOGIC_DIRstd_logic
out BF_DOUT_CTP_13std_logic
out MP2_F02_QUAD_115_TRN_2_CMPstd_logic
out MP2_F06_QUAD_115_TRN_1_CMPstd_logic
out BF_DOUT_CTP_59std_logic
in CLK_40MHz08_DSKW_2_BF_LOGIC_DIRstd_logic
in BF_TO_TP_ROI_SLINK_RETURN_DIRstd_logic
out BF_DOUT_CTP_56std_logic
out MP2_F07_QUAD_113_TRN_2_CMPstd_logic
std_logic_vector (65 downto 0) CTPout_clean
out BF_DOUT_CTP_11std_logic
out BF_DOUT_CTP_36std_logic
out MP1_F03_QUAD_110_TRN_1_DIRstd_logic
array (15 downto 0 ) of string (24 downto 1) mystring
out MP2_F06_QUAD_115_TRN_1_DIRstd_logic
out BF_DOUT_CTP_12std_logic