CMX_flavor_package.vhd

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library work;

use work.CMXpackage.all;
use work.CMX_local_package.all;

package CMX_flavor_package is
  
  constant version_flavor_common : std_logic_vector(15 downto 0):=x"F0A5";
  CONSTANT max_jems            : integer := 16;

  constant num_thresholds : integer := 8;

  constant max_bits_ExEy : integer :=15;
  constant max_bits_TE : integer :=15;

  constant max_bits_XE2 : integer := max_bits_ExEy*2 +1;
  
  subtype T_SL      is std_logic;
  subtype T_SLV2    is std_logic_vector(1 downto 0);
  subtype T_SLV3    is std_logic_vector(2 downto 0);
  subtype T_SLV4    is std_logic_vector(3 downto 0);
  subtype T_SLV12   is std_logic_vector(11 downto 0);
  subtype T_SLV13   is std_logic_vector(12 downto 0);
  subtype T_SLV24   is std_logic_vector(23 downto 0);
  subtype T_SLV25   is std_logic_vector(24 downto 0);
  subtype T_SLV30   is std_logic_vector(29 downto 0);
  subtype T_SLV32   is std_logic_vector(31 downto 0);
  subtype T_SLV16   is std_logic_vector(15 downto 0);
  subtype T_SLV60   is std_logic_vector(59 downto 0);
  subtype T_SLV61   is std_logic_vector(60 downto 0);
  subtype T_SLV62   is std_logic_vector(61 downto 0);
  subtype T_SLV65   is std_logic_vector(64 downto 0);
  subtype T_SLV75   is std_logic_vector(74 downto 0);
  subtype T_SLV120  is std_logic_vector(119 downto 0);
  subtype T_SLV121  is std_logic_vector(120 downto 0);
  subtype T_SLV1936 is std_logic_vector(1935 downto 0);

  
  subtype sum_array is arr_ctr_15bit(9 downto 0);

  type energy_array is array (0 to 15) of std_logic_vector(41 downto 0);
  type thr_array is array (0 to 15) of std_logic_vector(31 downto 0);
  type xs_thr_param_array is array (0 to 7) of std_logic_vector(31 downto 0);

  type calc_parity_typa_a is array(integer range <>) of std_logic;
  type calc_parity_type is array(integer range <>) of calc_parity_typa_a(3 downto 0);

  type cnt_mult_arr is array(integer range <>) of std_logic_vector(31 downto 0);
  type cnt_mult_arr_2x16 is array(integer range <>) of std_logic_vector(15 downto 0);

  --This defines if the JEM at a given position is in the upper or lower half
  --bit set to true means that JEM is in the upper half
  constant BACKPLANE_MAP : std_logic_vector(15 downto 0):= x"00FF";
  
  function quad_rest(arg : unsigned; quadrant : std_logic; restricted_SUMET : std_logic; restricted_MISSET : std_logic; iterator : integer) return unsigned;
  function xor_reduce (arg : std_logic_vector ) return std_logic;
  function raw_encoder(arg : std_logic_vector) return std_logic_vector;
  function crate_cable_in(arg : std_logic_vector) return std_logic_vector;
  function crate_cable_out(arg : std_logic_vector) return std_logic_vector;
  --function  sqrt32( d : unsigned ) return unsigned;
  --function sqrt( d : unsigned ) return unsigned;
  --function divide(a : unsigned; b : unsigned) return unsigned; 

end CMX_flavor_package;


package body CMX_flavor_package is

  
  function quad_rest(arg : unsigned; quadrant : std_logic; restricted_SUMET : std_logic; restricted_MISSET : std_logic; iterator : integer) return unsigned is
    variable tmp : unsigned(arg'range);
    variable result : unsigned(19 downto 0);
  begin
    if (quadrant = '1') and (iterator = 0 or iterator = 2 or iterator = 4) then 
      --upper no res            --ex u          ey u             et      
      tmp := arg;
    elsif (quadrant = '0') and (iterator = 1 or iterator = 3 or iterator = 4)  then
      --lower no res              --ex l          ex l                   
      tmp := arg;
    elsif ((quadrant = '1') and (iterator = 5 or iterator = 7)) and restricted_MISSET = '1' then 
      --upper res
      tmp := arg;
    elsif ((quadrant = '0') and (iterator = 6 or iterator = 8)) and restricted_MISSET = '1' then
      --lower res
      tmp := arg;
    elsif ((iterator = 9) and restricted_SUMET = '1') then
      tmp := arg;
    else
      tmp := (others => '0'); 
    end if;
    result := tmp;
    return result;
  end;

  function xor_reduce (arg : std_logic_vector ) return std_logic is
    variable Upper, Lower : std_logic;
    variable Half : integer;
    variable BUS_int : std_logic_vector ( arg'length - 1 downto 0 );
    variable Result : std_logic;
  begin
    if (arg'LENGTH < 1) then -- In the case of a NULL range
      Result := '0';
    else
      BUS_int := to_ux01 (arg);
      if ( BUS_int'length = 1 ) then
        Result := BUS_int ( BUS_int'left );
      elsif ( BUS_int'length = 2 ) then
        Result := BUS_int ( BUS_int'right ) xor BUS_int ( BUS_int'left);
      else
        Half := ( BUS_int'length + 1 ) / 2 + BUS_int'right;
        Upper := xor_reduce ( BUS_int ( BUS_int'left downto Half ));
        Lower := xor_reduce ( BUS_int ( Half - 1 downto BUS_int'right));
        Result := Upper xor Lower;
      end if;
    end if;
    return Result;
  end;

  function raw_encoder(arg : std_logic_vector) return std_logic_vector is
    variable result : std_logic_vector(127 downto 0) := (others => '0');
  begin
    result(13 downto 0) := arg(13 downto 0);
    result(22 downto 14) := (others => '0');
    result(23) := arg(42);
    result(37 downto 24) := arg(27 downto 14);
    result(46 downto 38) := (others => '0');
    result(47) := arg(43);
    result(61 downto 48) := arg(41 downto 28);
    result(70 downto 62) := (others => '0');
    result(71) := arg(44);
    result(94 downto 72) := (others => '0');
    result(95) := arg(45);
    result(96) := xor_reduce(arg);
    result(127 downto 97) := (others => '0');
    return result;
  end;

  function crate_cable_out(arg : std_logic_vector) return std_logic_vector is
    variable result : std_logic_vector(26*4-1 downto 0) := (others => '0');
    variable c0m0_parity, c0m1_parity : std_logic_vector(25 downto 0) := (others => '0');
    variable c1m0_parity, c1m1_parity : std_logic_vector(25 downto 0) := (others => '0');
  begin
    -- c0m0_parity := arg(arg'HIGH-5) & arg(2*15+9 downto 2*15) & arg(14 downto 0);
    c0m0_parity := '0' & arg(2*15+9 downto 2*15) & arg(14 downto 0);
    result(25 downto 0) := c0m0_parity;
    
    -- c0m1_parity := arg(arg'HIGH-3) & arg(5*15+9 downto 5*15) & arg(3*15+14 downto 3*15); 
    c0m1_parity := '0' & arg(5*15+9 downto 5*15) & arg(3*15+14 downto 3*15); 
    result(51 downto 26) :=c0m1_parity;
    
    -- c1m0_parity := arg(arg'HIGH-4) & x"0" & "00" & arg(2*15+13 downto 2*15+10) & arg(1*15+14 downto 15);
    c1m0_parity := '0' & "00" & arg(arg'HIGH-1)& arg(arg'HIGH-2) & arg(arg'HIGH-4) & arg(arg'HIGH-5) & arg(2*15+13 downto 2*15+10) & arg(1*15+14 downto 15);
    result(77 downto 52) := c1m0_parity;
    
    -- c1m1_parity := x"0" & "000" & arg(5*15+13 downto 5*15+10) & arg(4*15+14 downto 4*15);
    c1m1_parity := '0' & x"0" & arg(arg'HIGH) & arg(arg'HIGH-3) & arg(5*15+13 downto 5*15+10) & arg(4*15+14 downto 4*15);
    result(103 downto 78) := c1m1_parity;
    return result;
  end;

  function crate_cable_in(arg : std_logic_vector) return std_logic_vector is
    variable result : std_logic_vector(6*15+6-1 downto 0) := (others => '0');
  begin
    --ex
    result(1*15-1 downto 0*15) := arg(14 downto 0);
    --ey
    result(2*15-1 downto 1*15) := arg(2*26+14 downto 2*26);
    --et
    result(3*15-1 downto 2*15) := '0' & arg(2*26+18 downto 2*26+15) & arg(24 downto 15); 
    
    result(4*15-1 downto 3*15) := arg(26+14 downto 26);
    result(5*15-1 downto 4*15) := arg(3*26+14 downto 3*26);
    result(6*15-1 downto 5*15) := '0' & arg(3*26+18 downto 3*26+15) & arg(26+24 downto 26+15); 
    -- result(6*15+2 downto 6*15) := arg(26+25) & arg(25) & arg(2*26+25) ; 
    result(6*15+5 downto 6*15) := arg(98) & arg(74) &arg(73) & arg(97) & arg(72) & arg(71) ;
    return result;
  end;
  
--function  sqrt  ( arg : unsigned ) return unsigned is
--  variable tmp : unsigned(15 downto 0):= '0' & arg;  
--  variable result : unsigned(7 downto 0):=(others => '0');  
--  variable left, right, r : unsigned(9 downto 0):=(others => '0');  --input to adder/sub.r-remainder.
--  variable i : integer:=0;      
--begin
--  for i in 0 to 7 loop
--    right(0) := '1';
--    right(1) := r(9);
--    right(9 downto 2) := result;
--    left(1 downto 0) := tmp (15 downto 14);
--    left(9 downto 2) := r (7 downto 0);
--    tmp(15 downto 2) := tmp(13 downto 0);  --shifting by 2 bit.
--    if ( r(9) = '1') then
--      r := left + right;
--    else
--      r := left - right;
--    end if;
--    result(7 downto 1) := result(6 downto 0);
--    result(0) := not r(9);
--  end loop;    
--  return result;
--end sqrt;
--
--function  sqrt32  ( d : UNSIGNED ) return UNSIGNED is
--  variable a : unsigned(31 downto 0):=d;  --original input.
--  variable q : unsigned(15 downto 0):=(others => '0');  --result.
--  variable left,right,r : unsigned(17 downto 0):=(others => '0');  --input to adder/sub.r-remainder.
--  variable i : integer:=0;
--begin
--  for i in 0 to 15 loop
--    right(0):='1';
--    right(1):=r(17);
--    right(17 downto 2):=q;
--    left(1 downto 0):=a(31 downto 30);
--    left(17 downto 2):=r(15 downto 0);
--    a(31 downto 2):=a(29 downto 0);  --shifting by 2 bit.
--    if ( r(17) = '1') then
--      r := left + right;
--    else
--      r := left - right;
--    end if;
--    q(15 downto 1) := q(14 downto 0);
--    q(0) := not r(17);
--  end loop;
--  return q;
--
--end sqrt32;
--
--function  divide  (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is
--  variable a1 : unsigned(a'length-1 downto 0):=a;
--  variable b1 : unsigned(b'length-1 downto 0):=b;
--  variable p1 : unsigned(b'length downto 0):= (others => '0');
--  variable i : integer:=0;
--begin
--  for i in 0 to b'length-1 loop
--    p1(b'length-1 downto 1) := p1(b'length-2 downto 0);
--    p1(0) := a1(a'length-1);
--    a1(a'length-1 downto 1) := a1(a'length-2 downto 0);
--    p1 := p1-b1;
--    if(p1(b'length-1) ='1') then
--      a1(0) :='0';
--      p1 := p1+b1;
--    else
--      a1(0) :='1';
--    end if;
--  end loop;
--  return a1;
--
--end divide;
--
--

end CMX_flavor_package;