Processes
PROCESS_18	( clk )
PROCESS_19	( state_reg , op_request , rw_request , write_detect_REG_RW_GENERIC_SPY_MEM_CONTROL , read_detect_REG_RW_GENERIC_SPY_MEM_WORD (num_words - 1 ) , write_detect_REG_RW_GENERIC_SPY_MEM_WORD (num_words - 1 ) , global_addr_counter )

Components
vme_local_switch	<Entity vme_local_switch>
vme_outreg_notri	<Entity vme_outreg_notri>
vme_outreg_notri_async	<Entity vme_outreg_notri_async>
vme_inreg_notri	<Entity vme_inreg_notri>
vme_inreg_notri_async	<Entity vme_inreg_notri_async>

Constants
data_length	integer := dina ' length
num_words	integer := integer ( ceil ( real ( data_length ) / real ( 16 ) ) )
num_rem_bits	integer := data_length rem 16
mem_select_width_uncorr	natural := ceil_log_2 ( num_external_RAMS )
mem_select_width_uncorr_trunc	natural := imin ( 5 , mem_select_width_uncorr )
global_addr_counter_limit	*unsigned := to_unsigned ( 256 num_external_RAMS , mem_select_width_uncorr + 1 + 8**

Types
state_spy_mem_control_type	( s_standby , s_inhibit_init , s_wait_for_vme_write , s_writing_ram , s_reading_ram , s_wait_for_vme_read )

Signals
state_reg	state_spy_mem_control_type
state_next	state_spy_mem_control_type
wea_sig	std_logic
ena_sig	std_logic
dina_sig	std_logic_vector ( data_length - 1 downto 0 )
data_vme_from_below	arr_16 ( num_words + 1 downto 0 )
bus_drive_from_below	std_logic_vector ( num_words + 1 downto 0 )
data_from_vme_REG_RW_GENERIC_SPY_MEM_WORD	arr_16 ( num_words - 1 downto 0 )
data_to_vme_REG_RW_GENERIC_SPY_MEM_WORD	arr_16 ( num_words - 1 downto 0 )
read_detect_REG_RW_GENERIC_SPY_MEM_WORD	std_logic_vector ( num_words - 1 downto 0 )
write_detect_REG_RW_GENERIC_SPY_MEM_WORD	std_logic_vector ( num_words - 1 downto 0 )
data_from_vme_REG_RW_GENERIC_SPY_MEM_CONTROL	std_logic_vector ( 15 downto 0 )
data_to_vme_REG_RW_GENERIC_SPY_MEM_CONTROL	std_logic_vector ( 15 downto 0 )
read_detect_REG_RW_GENERIC_SPY_MEM_CONTROL	std_logic
write_detect_REG_RW_GENERIC_SPY_MEM_CONTROL	std_logic
data_to_vme_REG_RO_GENERIC_SPY_MEM_STATUS	std_logic_vector ( 15 downto 0 )
status_summary	std_logic_vector ( 2 downto 0 )
global_addr_counter	unsigned ( 8 + mem_select_width_uncorr downto 0 )
global_addr_counter_next	unsigned ( 8 + mem_select_width_uncorr downto 0 )
inhibit_init_counter	unsigned ( 0 downto 0 )
op_request	std_logic
rw_request	std_logic
port_b_master_inhibit_sig	std_logic

Instantiations
vme_local_switch_inst	vme_local_switch <Entity vme_local_switch>
vme_inreg_reg_rw_generic_spy_mem_word	vme_inreg_notri <Entity vme_inreg_notri>
vme_inreg_reg_rw_generic_spy_mem_control	vme_inreg_notri <Entity vme_inreg_notri>
vme_outreg_reg_ro_generic_spy_mem_status	vme_outreg_notri_async <Entity vme_outreg_notri_async>

Detailed Description

Member Function Documentation

PROCESS_18 ( clk )

PROCESS_19	(	state_reg ,
		op_request ,
		rw_request ,
		write_detect_REG_RW_GENERIC_SPY_MEM_CONTROL ,
		read_detect_REG_RW_GENERIC_SPY_MEM_WORD (num_words - 1 ) ,
		write_detect_REG_RW_GENERIC_SPY_MEM_WORD (num_words - 1 ) ,
		global_addr_counter
	)