Index of /hep/d0/ftp/run2b/l1cal/hardware/adf_2/drawings

Icon  Name                                                 Last modified      Size  Description
[PARENTDIR] Parent Directory                                                          -   
[   ] adf_2_adc_10_bit.pdf                                 2004-11-01 17:08   27K  
[   ] adf_2_adc_10_bit.ps                                  2004-11-01 16:45   51K  
[IMG] adf_2_capture_tt_neg_10_1_20050310.gif               2005-03-11 11:13   11K  
[   ] adf_2_card_block_diagram.pdf                         2004-06-24 17:24   61K  
[   ] adf_2_card_block_diagram.ps                          2004-06-24 17:22  115K  
[   ] adf_2_circuit_board_1.pdf                            2004-11-03 16:40  1.2M  
[   ] adf_2_circuit_board_1.ps                             2004-11-03 16:38  1.8M  
[   ] adf_2_dc_dc_converter.pdf                            2004-04-08 10:46   43K  
[   ] adf_2_dc_dc_converter.ps                             2004-04-08 10:45   92K  
[   ] adf_2_differential_amp.pdf                           2004-12-14 11:12   25K  
[   ] adf_2_differential_amp.ps                            2004-12-14 11:10   48K  
[   ] adf_2_front_panel_silk_screen.pdf                    2005-03-25 09:34  7.0K  
[   ] adf_2_front_panel_silk_screen.ps                     2005-03-25 09:33   60K  
[   ] adf_2_front_panel_silk_screen_with_panel_outline.pdf 2005-03-25 09:41  8.1K  
[   ] adf_2_front_panel_silk_screen_with_panel_outline.ps  2005-03-25 09:40   62K  
[   ] adf_2_many_front_panels.pdf                          2005-03-24 11:47   53K  
[   ] adf_2_pal_signal_heirarchy.pdf                       2004-08-26 16:17   68K  
[   ] adf_2_pal_signal_heirarchy.ps                        2004-08-26 15:59  148K  
[   ] adf_2_pal_state_machine_timing_diagrams.pdf          2004-09-27 18:01   10K  
[   ] adf_2_pal_state_machine_timing_diagrams.ps           2004-09-27 18:00   21K  
[   ] adf_2_pal_top_level_schematic.ps                     2005-02-07 15:19  148K  
[   ] adf_2_pal_vme_invalid_cycle_timing_diagrams.pdf      2004-08-26 16:18   21K  
[   ] adf_2_pal_vme_invalid_cycle_timing_diagrams.ps       2004-08-26 16:16   40K  
[   ] adf_2_pal_vme_read_timing_diagrams.pdf               2004-08-26 16:18   24K  
[   ] adf_2_pal_vme_read_timing_diagrams.ps                2004-08-26 16:17   44K  
[   ] adf_2_pal_vme_write_timing_diagrams.pdf              2004-08-26 16:18   23K  
[   ] adf_2_pal_vme_write_timing_diagrams.ps               2004-08-26 16:14   44K  
[   ] adf_2_ped_dacs.pdf                                   2004-11-01 17:05   33K  
[   ] adf_2_ped_dacs.ps                                    2004-11-01 16:49   61K  
[   ] adf_2_power_up_supervisor.pdf                        2005-04-11 11:48   43K  
[   ] adf_2_power_up_supervisor.ps                         2005-04-11 11:44   83K  
[   ] adf_2_vme_timing_diagrams.ps                         2004-07-13 12:41   58K  
[   ] adf_crate_bx_clk_distribution.pdf                    2004-03-22 14:23   11K  
[   ] adf_crate_bx_clk_distribution.ps                     2004-03-22 14:22   25K  
[   ] board_control_pal_board_level_control.pdf            2004-06-11 14:22   34K  
[   ] board_control_pal_board_level_control.ps             2004-06-11 14:21   65K  
[   ] board_control_pal_fpga_configuration.pdf             2004-11-01 17:06   55K  
[   ] board_control_pal_fpga_configuration.ps              2004-11-01 16:53  105K  
[   ] board_control_pal_vme_interface.pdf                  2004-12-14 11:13   24K  
[   ] board_control_pal_vme_interface.ps                   2004-12-14 11:10   47K  
[   ] clock_bx_x8_generation.pdf                           2004-12-14 11:14   48K  
[   ] clock_bx_x8_generation.ps                            2004-12-14 11:11   92K  
[   ] clock_generation_timing.pdf                          2004-07-16 13:41   17K  
[   ] clock_generation_timing.ps                           2004-07-16 12:59   35K  
[   ] clock_signal_timing.pdf                              2004-07-16 13:42  7.5K  
[   ] clock_signal_timing.ps                               2004-07-16 13:00   16K  
[   ] data_path_fpga_output_to_channel_link.pdf            2005-08-16 13:57   39K  
[   ] data_path_fpga_output_to_channel_link.ps             2005-08-16 13:54   74K  
[   ] data_path_fpga_signal_processing.pdf                 2005-12-08 11:53   53K  
[   ] data_path_fpga_signal_processing.ps                  2005-12-08 11:48  101K  
[   ] et_lookup_memory_data.pdf                            2005-12-08 11:52   14K  
[   ] et_lookup_memory_data.ps                             2005-12-08 11:50   29K  
[   ] power_entry_and_dc_dc_converters.pdf                 2004-11-01 17:09   26K  
[   ] power_entry_and_dc_dc_converters.ps                  2004-11-01 16:59   51K  
[   ] run2b_l1_cal_trig_data_paths.pdf                     2006-04-21 13:44   10K  
[   ] scld_control_signal_distribution.pdf                 2004-12-14 11:14   52K  
[   ] scld_control_signal_distribution.ps                  2004-12-14 11:11   98K  
[   ] scld_logic_block_diagram.pdf                         2004-07-01 21:13   40K  
[   ] scld_logic_block_diagram.ps                          2004-07-01 21:13   77K  
[   ] scld_signal_timing.pdf                               2004-07-01 21:27   20K  
[   ] scld_signal_timing.ps                                2004-07-01 21:26   39K