Index of /people/edmunds/LArTPC/LArTPC_FPGA_Designs/LArTPC_T7_Design
Name Last modified Size Description
Parent Directory -
L1_Top.ps 2009-06-17 11:12 321K
Data_Path.ps 2009-06-17 11:12 207K
Timing_Generator_1_of_2.ps 2009-06-16 15:33 206K
Mem_A_Port_Adrs_Ctrl_1_of_2.ps 2009-06-16 15:06 163K
Chan_Lnk_Output_Shifter_1_of_2.ps 2009-06-16 14:25 159K
OCB_IF_4_of_6.ps 2009-06-16 14:09 155K
OCB_IF_6_of_6.ps 2009-06-16 14:09 155K
TT_Cell_9_of_9.ps 2009-06-16 15:49 152K
Mem_Blk_2k_10.ps 2009-06-16 15:06 151K
Channel_Link_Driver_1_of_2.ps 2009-06-16 14:17 147K
TT_Cell_2_of_9.ps 2009-06-17 11:12 147K
TT_Cell_1_of_9.ps 2009-06-17 11:12 146K
Channel_Link_Driver_2_of_2.ps 2009-06-16 14:17 138K
Frame_Shifter_and_Chan_Lnk.ps 2009-06-16 14:51 137K
OCB_IF_3_of_6.ps 2009-06-16 14:09 132K
Timing_Generator_2_of_2.ps 2009-06-16 15:33 130K
OCB_IF_1_of_6.ps 2009-06-16 14:09 123K
TT_Cell_4_of_9.ps 2009-06-16 15:49 112K
ADC_Data_Receiver.ps 2009-06-16 13:36 112K
BX_Number_Gen.ps 2009-06-16 14:17 109K
TT_Cell_6_of_9.ps 2009-06-16 15:49 107K
Mem_A_Port_Adrs_Ctrl_2_of_2.ps 2009-06-16 15:06 107K
OCB_IF_2_of_6.ps 2009-06-16 14:09 102K
TT_Cell_5_of_9.ps 2009-06-16 15:49 99K
PRN_Generator.ps 2009-06-16 15:20 98K
Shifter_for_One_Lane.ps 2009-06-16 15:33 96K
OCB_IF_7_of_7.ps 2009-06-16 14:09 95K
L1_Top.pdf 2009-06-17 11:13 95K
SCLD_Rec_Dist.ps 2009-06-16 15:20 89K
Align_ADC_Data.ps 2009-06-16 13:36 86K
Clock_Rec_Dist.ps 2009-06-16 14:25 85K
Chan_Lnk_Output_Shifter_2_of_2.ps 2009-06-16 14:25 80K
OCB_IF_5_of_6.ps 2009-06-16 14:09 80K
TT_Cell_3_of_9.ps 2009-06-16 15:49 78K
TT_Cell_8_of_9.ps 2009-06-16 15:49 76K
Drive_ADC_Clock.ps 2009-06-16 14:45 75K
TT_Cell_7_of_9.ps 2009-06-16 15:49 71K
Double_Buf_Update_Enable.ps 2009-06-16 14:37 68K
PRN_Shift_Control.ps 2009-06-16 15:20 67K
LED_Driver.ps 2009-06-16 15:05 66K
Timing_Generator_1_of_2.pdf 2009-06-16 15:34 61K
Data_Path.pdf 2009-06-17 11:13 60K
Access_Connector.ps 2009-06-16 13:23 57K
Control_Reg_16_Bit.ps 2009-06-16 14:37 57K
Status_to_BC_PAL.ps 2009-06-16 15:33 56K
Pull_Up_16_Bit.ps 2009-06-16 15:20 52K
Mem_A_Port_Adrs_Ctrl_1_of_2.pdf 2009-06-16 15:06 49K
Status_Reg_16_Bit.ps 2009-06-16 15:33 48K
Chan_Lnk_Output_Shifter_1_of_2.pdf 2009-06-16 14:26 47K
TT_Cell_9_of_9.pdf 2009-06-16 15:50 45K
Mem_Blk_2k_10.pdf 2009-06-16 15:07 45K
OCB_IF_6_of_6.pdf 2009-06-16 14:09 44K
OCB_IF_4_of_6.pdf 2009-06-16 14:09 44K
TT_Cell_1_of_9.pdf 2009-06-17 11:14 44K
TT_Cell_2_of_9.pdf 2009-06-17 11:15 43K
Channel_Link_Driver_1_of_2.pdf 2009-06-16 14:18 43K
Frame_Shifter_and_Chan_Lnk.pdf 2009-06-16 14:51 40K
Channel_Link_Driver_2_of_2.pdf 2009-06-16 14:18 40K
OCB_IF_3_of_6.pdf 2009-06-16 14:09 38K
Timing_Generator_2_of_2.pdf 2009-06-16 15:34 38K
OCB_IF_1_of_6.pdf 2009-06-16 14:09 37K
TT_Cell_4_of_9.pdf 2009-06-16 15:49 34K
ADC_Data_Receiver.pdf 2009-06-16 13:37 33K
BX_Number_Gen.pdf 2009-06-16 14:18 32K
Mem_A_Port_Adrs_Ctrl_2_of_2.pdf 2009-06-16 15:06 32K
TT_Cell_6_of_9.pdf 2009-06-16 15:50 31K
OCB_IF_2_of_6.pdf 2009-06-16 14:09 30K
PRN_Generator.pdf 2009-06-16 15:20 30K
TT_Cell_5_of_9.pdf 2009-06-16 15:49 30K
Shifter_for_One_Lane.pdf 2009-06-16 15:33 29K
OCB_IF_7_of_7.pdf 2009-06-16 14:09 28K
Align_ADC_Data.pdf 2009-06-16 13:38 27K
SCLD_Rec_Dist.pdf 2009-06-16 15:21 26K
Clock_Rec_Dist.pdf 2009-06-16 14:25 26K
Chan_Lnk_Output_Shifter_2_of_2.pdf 2009-06-16 14:26 24K
OCB_IF_5_of_6.pdf 2009-06-16 14:09 24K
TT_Cell_3_of_9.pdf 2009-06-16 15:49 24K
TT_Cell_8_of_9.pdf 2009-06-16 15:50 23K
Drive_ADC_Clock.pdf 2009-06-16 14:46 22K
TT_Cell_7_of_9.pdf 2009-06-16 15:50 22K
Double_Buf_Update_Enable.pdf 2009-06-16 14:37 21K
PRN_Shift_Control.pdf 2009-06-16 15:21 20K
LED_Driver.pdf 2009-06-16 15:06 20K
Control_Reg_16_Bit.pdf 2009-06-16 14:37 17K
Access_Connector.pdf 2009-06-16 13:25 17K
Status_to_BC_PAL.pdf 2009-06-16 15:33 17K
Pull_Up_16_Bit.pdf 2009-06-16 15:21 15K
Status_Reg_16_Bit.pdf 2009-06-16 15:33 14K